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[31.208.27.151]) by smtp.gmail.com with ESMTPSA id u12sm2751423lff.126.2021.04.08.02.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Apr 2021 02:21:21 -0700 (PDT) Date: Thu, 8 Apr 2021 11:21:20 +0200 From: Francisco Iglesias To: =?iso-8859-1?Q?C=E9dric?= Le Goater Subject: Re: [PATCH 21/24] hw/block: m25p80: Add support for mt25qu02g Message-ID: <20210408092119.GA24687@fralle-msi> References: <20210407171637.777743-1-clg@kaod.org> <20210407171637.777743-22-clg@kaod.org> <20210408080001.2r4gxygjsuorvaxs@debian> <0d5e9101-7ae9-8892-cc00-d83f958ffca8@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <0d5e9101-7ae9-8892-cc00-d83f958ffca8@kaod.org> User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=frasse.iglesias@gmail.com; helo=mail-lf1-x12d.google.com X-Spam_score_int: -1020 X-Spam_score: -102.1 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-102.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jeffery , qemu-devel@nongnu.org, Francisco Iglesias , qemu-arm@nongnu.org, Alistair Francis , Joel Stanley Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Cedric, On [2021 Apr 08] Thu 10:40:18, Cédric Le Goater wrote: > On 4/8/21 10:00 AM, Francisco Iglesias wrote: > > Hello Cedric! > > > > On Wed, Apr 07, 2021 at 07:16:34PM +0200, Cédric Le Goater wrote: > >> The Micron mt25qu02g is a 3V 2Gb serial NOR flash memory supporting > >> dual I/O and quad I/O, 4KB, 32KB, 64KB sector erase. It also supports > >> 4B opcodes. > >> > >> Cc: Alistair Francis > >> Cc: Francisco Iglesias > >> Signed-off-by: Cédric Le Goater > >> --- > >> hw/block/m25p80.c | 1 + > >> 1 file changed, 1 insertion(+) > >> > >> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c > >> index 183d3f44c259..2afb939ae28e 100644 > >> --- a/hw/block/m25p80.c > >> +++ b/hw/block/m25p80.c > >> @@ -259,6 +259,7 @@ static const FlashPartInfo known_devices[] = { > >> { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, > >> { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, > >> { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, > >> + { INFO_STACKED("mt25qu02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K, 2) }, > > > > Is it possible it should be as below instead? > > > > { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, > > > > 's/0x20ba22/0x20bb22/' (or 's/mt25qu02g/mt25ql02g/') since 'u' looks to stand > > for 1.7-2.0 V and 'bb' for 1.8 V (see page 2 and 32 in [1]). > > Here is what I am seeing : > > mt25ql02g 0x20ba22 3V > mt25qu02g 0x20bb22 1.8V > > Do we agree ? Yes :) Best regards, Francisco > > > s/ER_4K/ER_4K | ER_32K/ since ERASE_32K is supported (see page 36). > > yes. I should have added that ! > > > If you find above changes ok and go with them please add: > > > > Reviewed-by: Francisco Iglesias > > Sure, > > Thanks, > > C. > > > > Best regards, > > Francisco Iglesias > > > > [1] Micron Serial NOR Flash Memory 1.8V, Multiple I/O, 64KB Sector Erase MT25QU02GCBB > > https://4donline.ihs.com/images/VipMasterIC/IC/MICT/MICT-S-A0008500026/MICT-S-A0008511423-1.pdf?hkey=52A5661711E402568146F3353EA87419 > > > >> > >> /* Spansion -- single (large) sector size only, at least > >> * for the chips listed here (without boot sectors). > >> -- > >> 2.26.3 > >> > >