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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 05/13] target/arm: Move gen_aa32 functions to translate-a32.h
Date: Tue, 13 Apr 2021 17:07:51 +0100	[thread overview]
Message-ID: <20210413160759.5917-6-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210413160759.5917-1-peter.maydell@linaro.org>

Move the various gen_aa32* functions and macros out of translate.c
and into translate-a32.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a32.h | 44 ++++++++++++++++++++++++++++++++++
 target/arm/translate.c     | 49 +++++++-------------------------------
 2 files changed, 52 insertions(+), 41 deletions(-)

diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index cb451f70a42..e0e03245f6f 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -57,4 +57,48 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
     return tmp;
 }
 
+void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+                     int index, MemOp opc);
+void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+                     int index, MemOp opc);
+void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+                     int index, MemOp opc);
+void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+                     int index, MemOp opc);
+
+#define DO_GEN_LD(SUFF, OPC)                                             \
+static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val,      \
+                                     TCGv_i32 a32, int index)            \
+{                                                                        \
+    gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
+}
+
+#define DO_GEN_ST(SUFF, OPC)                                             \
+static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val,      \
+                                     TCGv_i32 a32, int index)            \
+{                                                                        \
+    gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
+}
+
+DO_GEN_LD(8u, MO_UB)
+DO_GEN_LD(16u, MO_UW)
+DO_GEN_LD(32u, MO_UL)
+DO_GEN_ST(8, MO_UB)
+DO_GEN_ST(16, MO_UW)
+DO_GEN_ST(32, MO_UL)
+
+#undef DO_GEN_LD
+
+static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
+                                 TCGv_i32 a32, int index)
+{
+    gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);
+}
+
+static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
+                                 TCGv_i32 a32, int index)
+{
+    gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
+}
+
 #endif
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 168427159ab..fd248b101f2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -879,8 +879,8 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
     return addr;
 }
 
-static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
-                            int index, MemOp opc)
+void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+                     int index, MemOp opc)
 {
     TCGv addr;
 
@@ -894,8 +894,8 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
     tcg_temp_free(addr);
 }
 
-static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
-                            int index, MemOp opc)
+void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
+                     int index, MemOp opc)
 {
     TCGv addr;
 
@@ -909,20 +909,6 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
     tcg_temp_free(addr);
 }
 
-#define DO_GEN_LD(SUFF, OPC)                                             \
-static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val,      \
-                                     TCGv_i32 a32, int index)            \
-{                                                                        \
-    gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
-}
-
-#define DO_GEN_ST(SUFF, OPC)                                             \
-static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val,      \
-                                     TCGv_i32 a32, int index)            \
-{                                                                        \
-    gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
-}
-
 static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
 {
     /* Not needed for user-mode BE32, where we use MO_BE instead.  */
@@ -931,8 +917,8 @@ static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
     }
 }
 
-static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
-                            int index, MemOp opc)
+void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+                     int index, MemOp opc)
 {
     TCGv addr = gen_aa32_addr(s, a32, opc);
     tcg_gen_qemu_ld_i64(val, addr, index, opc);
@@ -940,14 +926,8 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
     tcg_temp_free(addr);
 }
 
-static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
-                                 TCGv_i32 a32, int index)
-{
-    gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);
-}
-
-static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
-                            int index, MemOp opc)
+void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+                     int index, MemOp opc)
 {
     TCGv addr = gen_aa32_addr(s, a32, opc);
 
@@ -963,19 +943,6 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
     tcg_temp_free(addr);
 }
 
-static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
-                                 TCGv_i32 a32, int index)
-{
-    gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
-}
-
-DO_GEN_LD(8u, MO_UB)
-DO_GEN_LD(16u, MO_UW)
-DO_GEN_LD(32u, MO_UL)
-DO_GEN_ST(8, MO_UB)
-DO_GEN_ST(16, MO_UW)
-DO_GEN_ST(32, MO_UL)
-
 static inline void gen_hvc(DisasContext *s, int imm16)
 {
     /* The pre HVC helper handles cases when HVC gets trapped
-- 
2.20.1



  parent reply	other threads:[~2021-04-13 16:10 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-13 16:07 [PATCH 00/13] target/arm: Split translate-*.c.inc into separate compilation units Peter Maydell
2021-04-13 16:07 ` [PATCH 01/13] target/arm: Move constant expanders to translate.h Peter Maydell
2021-04-13 16:59   ` Philippe Mathieu-Daudé
2021-04-27 16:29   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 02/13] target/arm: Share unallocated_encoding() and gen_exception_insn() Peter Maydell
2021-04-27 16:36   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 03/13] target/arm: Make functions used by m-nocp global Peter Maydell
2021-04-27 16:42   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 04/13] target/arm: Split m-nocp trans functions into their own file Peter Maydell
2021-04-27 16:40   ` Richard Henderson
2021-04-13 16:07 ` Peter Maydell [this message]
2021-04-27 16:44   ` [PATCH 05/13] target/arm: Move gen_aa32 functions to translate-a32.h Richard Henderson
2021-04-27 16:46     ` Peter Maydell
2021-04-13 16:07 ` [PATCH 06/13] target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc Peter Maydell
2021-04-13 17:00   ` Philippe Mathieu-Daudé
2021-04-27 16:47   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 07/13] target/arm: Make functions used by translate-vfp global Peter Maydell
2021-04-13 17:01   ` Philippe Mathieu-Daudé
2021-04-27 17:03   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 08/13] target/arm: Make translate-vfp.c.inc its own compilation unit Peter Maydell
2021-04-13 17:02   ` Philippe Mathieu-Daudé
2021-04-27 17:06   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 09/13] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc Peter Maydell
2021-04-13 17:02   ` Philippe Mathieu-Daudé
2021-04-13 17:03   ` Philippe Mathieu-Daudé
2021-04-27 17:06   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 10/13] target/arm: Delete unused typedef Peter Maydell
2021-04-27 17:07   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 11/13] target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h Peter Maydell
2021-04-27 17:07   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 12/13] target/arm: Make functions used by translate-neon global Peter Maydell
2021-04-13 17:04   ` Philippe Mathieu-Daudé
2021-04-27 17:07   ` Richard Henderson
2021-04-13 16:07 ` [PATCH 13/13] target/arm: Make translate-neon.c.inc its own compilation unit Peter Maydell
2021-04-13 17:04   ` Philippe Mathieu-Daudé
2021-04-27 17:08   ` Richard Henderson

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