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From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Roman Bolshakov <r.bolshakov@yadro.com>,
	Claudio Fontana <cfontana@suse.de>,
	Eduardo Habkost <ehabkost@redhat.com>,
	qemu-devel@nongnu.org
Subject: [RFC v13 28/80] target/arm: split 32bit and 64bit arm dump state
Date: Wed, 14 Apr 2021 13:25:58 +0200	[thread overview]
Message-ID: <20210414112650.18003-29-cfontana@suse.de> (raw)
In-Reply-To: <20210414112650.18003-1-cfontana@suse.de>

Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
 target/arm/cpu32.h |   2 +-
 target/arm/cpu.c   | 225 ---------------------------------------------
 target/arm/cpu32.c |  85 ++++++++++++++++-
 target/arm/cpu64.c | 142 ++++++++++++++++++++++++++++
 4 files changed, 227 insertions(+), 227 deletions(-)

diff --git a/target/arm/cpu32.h b/target/arm/cpu32.h
index 211fad6f55..128d0c9247 100644
--- a/target/arm/cpu32.h
+++ b/target/arm/cpu32.h
@@ -21,7 +21,7 @@
 #ifndef ARM_CPU32_H
 #define ARM_CPU32_H
 
-void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags);
+void arm32_cpu_dump_state(CPUState *cs, FILE *f, int flags);
 void arm32_cpu_class_init(ObjectClass *oc, void *data);
 void arm32_cpu_register(const ARMCPUInfo *info);
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d88074b677..e9dc5da4ca 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -19,7 +19,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/qemu-print.h"
 #include "qemu-common.h"
 #include "target/arm/idau.h"
 #include "qemu/module.h"
@@ -717,230 +716,6 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 #endif
 }
 
-#ifdef TARGET_AARCH64
-
-static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-{
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
-    uint32_t psr = pstate_read(env);
-    int i;
-    int el = arm_current_el(env);
-    const char *ns_status;
-
-    qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
-    for (i = 0; i < 32; i++) {
-        if (i == 31) {
-            qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
-        } else {
-            qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
-                         (i + 2) % 3 ? " " : "\n");
-        }
-    }
-
-    if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
-        ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
-    } else {
-        ns_status = "";
-    }
-    qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
-                 psr,
-                 psr & PSTATE_N ? 'N' : '-',
-                 psr & PSTATE_Z ? 'Z' : '-',
-                 psr & PSTATE_C ? 'C' : '-',
-                 psr & PSTATE_V ? 'V' : '-',
-                 ns_status,
-                 el,
-                 psr & PSTATE_SP ? 'h' : 't');
-
-    if (cpu_isar_feature(aa64_bti, cpu)) {
-        qemu_fprintf(f, "  BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
-    }
-    if (!(flags & CPU_DUMP_FPU)) {
-        qemu_fprintf(f, "\n");
-        return;
-    }
-    if (fp_exception_el(env, el) != 0) {
-        qemu_fprintf(f, "    FPU disabled\n");
-        return;
-    }
-    qemu_fprintf(f, "     FPCR=%08x FPSR=%08x\n",
-                 vfp_get_fpcr(env), vfp_get_fpsr(env));
-
-    if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
-        int j, zcr_len = sve_zcr_len_for_el(env, el);
-
-        for (i = 0; i <= FFR_PRED_NUM; i++) {
-            bool eol;
-            if (i == FFR_PRED_NUM) {
-                qemu_fprintf(f, "FFR=");
-                /* It's last, so end the line.  */
-                eol = true;
-            } else {
-                qemu_fprintf(f, "P%02d=", i);
-                switch (zcr_len) {
-                case 0:
-                    eol = i % 8 == 7;
-                    break;
-                case 1:
-                    eol = i % 6 == 5;
-                    break;
-                case 2:
-                case 3:
-                    eol = i % 3 == 2;
-                    break;
-                default:
-                    /* More than one quadword per predicate.  */
-                    eol = true;
-                    break;
-                }
-            }
-            for (j = zcr_len / 4; j >= 0; j--) {
-                int digits;
-                if (j * 4 + 4 <= zcr_len + 1) {
-                    digits = 16;
-                } else {
-                    digits = (zcr_len % 4 + 1) * 4;
-                }
-                qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
-                             env->vfp.pregs[i].p[j],
-                             j ? ":" : eol ? "\n" : " ");
-            }
-        }
-
-        for (i = 0; i < 32; i++) {
-            if (zcr_len == 0) {
-                qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
-                             i, env->vfp.zregs[i].d[1],
-                             env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
-            } else if (zcr_len == 1) {
-                qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
-                             ":%016" PRIx64 ":%016" PRIx64 "\n",
-                             i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
-                             env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
-            } else {
-                for (j = zcr_len; j >= 0; j--) {
-                    bool odd = (zcr_len - j) % 2 != 0;
-                    if (j == zcr_len) {
-                        qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
-                    } else if (!odd) {
-                        if (j > 0) {
-                            qemu_fprintf(f, "   [%x-%x]=", j, j - 1);
-                        } else {
-                            qemu_fprintf(f, "     [%x]=", j);
-                        }
-                    }
-                    qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
-                                 env->vfp.zregs[i].d[j * 2 + 1],
-                                 env->vfp.zregs[i].d[j * 2],
-                                 odd || j == 0 ? "\n" : ":");
-                }
-            }
-        }
-    } else {
-        for (i = 0; i < 32; i++) {
-            uint64_t *q = aa64_vfp_qreg(env, i);
-            qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
-                         i, q[1], q[0], (i & 1 ? "\n" : " "));
-        }
-    }
-}
-
-#else
-
-static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-{
-    g_assert_not_reached();
-}
-
-#endif
-
-void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-{
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
-    int i;
-
-    if (is_a64(env)) {
-        aarch64_cpu_dump_state(cs, f, flags);
-        return;
-    }
-
-    for (i = 0; i < 16; i++) {
-        qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
-        if ((i % 4) == 3) {
-            qemu_fprintf(f, "\n");
-        } else {
-            qemu_fprintf(f, " ");
-        }
-    }
-
-    if (arm_feature(env, ARM_FEATURE_M)) {
-        uint32_t xpsr = xpsr_read(env);
-        const char *mode;
-        const char *ns_status = "";
-
-        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
-            ns_status = env->v7m.secure ? "S " : "NS ";
-        }
-
-        if (xpsr & XPSR_EXCP) {
-            mode = "handler";
-        } else {
-            if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
-                mode = "unpriv-thread";
-            } else {
-                mode = "priv-thread";
-            }
-        }
-
-        qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
-                     xpsr,
-                     xpsr & XPSR_N ? 'N' : '-',
-                     xpsr & XPSR_Z ? 'Z' : '-',
-                     xpsr & XPSR_C ? 'C' : '-',
-                     xpsr & XPSR_V ? 'V' : '-',
-                     xpsr & XPSR_T ? 'T' : 'A',
-                     ns_status,
-                     mode);
-    } else {
-        uint32_t psr = cpsr_read(env);
-        const char *ns_status = "";
-
-        if (arm_feature(env, ARM_FEATURE_EL3) &&
-            (psr & CPSR_M) != ARM_CPU_MODE_MON) {
-            ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
-        }
-
-        qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
-                     psr,
-                     psr & CPSR_N ? 'N' : '-',
-                     psr & CPSR_Z ? 'Z' : '-',
-                     psr & CPSR_C ? 'C' : '-',
-                     psr & CPSR_V ? 'V' : '-',
-                     psr & CPSR_T ? 'T' : 'A',
-                     ns_status,
-                     aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
-    }
-
-    if (flags & CPU_DUMP_FPU) {
-        int numvfpregs = 0;
-        if (cpu_isar_feature(aa32_simd_r32, cpu)) {
-            numvfpregs = 32;
-        } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
-            numvfpregs = 16;
-        }
-        for (i = 0; i < numvfpregs; i++) {
-            uint64_t v = *aa32_vfp_dreg(env, i);
-            qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
-                         i * 2, (uint32_t)v,
-                         i * 2 + 1, (uint32_t)(v >> 32),
-                         i, v);
-        }
-        qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
-    }
-}
-
 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
 {
     uint32_t Aff1 = idx / clustersz;
diff --git a/target/arm/cpu32.c b/target/arm/cpu32.c
index 39fb112a04..c03f420ba2 100644
--- a/target/arm/cpu32.c
+++ b/target/arm/cpu32.c
@@ -58,6 +58,89 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
     return g_strdup("arm");
 }
 
+void arm32_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    int i;
+
+    assert(!is_a64(env));
+
+    for (i = 0; i < 16; i++) {
+        qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
+        if ((i % 4) == 3) {
+            qemu_fprintf(f, "\n");
+        } else {
+            qemu_fprintf(f, " ");
+        }
+    }
+
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        uint32_t xpsr = xpsr_read(env);
+        const char *mode;
+        const char *ns_status = "";
+
+        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+            ns_status = env->v7m.secure ? "S " : "NS ";
+        }
+
+        if (xpsr & XPSR_EXCP) {
+            mode = "handler";
+        } else {
+            if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
+                mode = "unpriv-thread";
+            } else {
+                mode = "priv-thread";
+            }
+        }
+
+        qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
+                     xpsr,
+                     xpsr & XPSR_N ? 'N' : '-',
+                     xpsr & XPSR_Z ? 'Z' : '-',
+                     xpsr & XPSR_C ? 'C' : '-',
+                     xpsr & XPSR_V ? 'V' : '-',
+                     xpsr & XPSR_T ? 'T' : 'A',
+                     ns_status,
+                     mode);
+    } else {
+        uint32_t psr = cpsr_read(env);
+        const char *ns_status = "";
+
+        if (arm_feature(env, ARM_FEATURE_EL3) &&
+            (psr & CPSR_M) != ARM_CPU_MODE_MON) {
+            ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
+        }
+
+        qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
+                     psr,
+                     psr & CPSR_N ? 'N' : '-',
+                     psr & CPSR_Z ? 'Z' : '-',
+                     psr & CPSR_C ? 'C' : '-',
+                     psr & CPSR_V ? 'V' : '-',
+                     psr & CPSR_T ? 'T' : 'A',
+                     ns_status,
+                     aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
+    }
+
+    if (flags & CPU_DUMP_FPU) {
+        int numvfpregs = 0;
+        if (cpu_isar_feature(aa32_simd_r32, cpu)) {
+            numvfpregs = 32;
+        } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
+            numvfpregs = 16;
+        }
+        for (i = 0; i < numvfpregs; i++) {
+            uint64_t v = *aa32_vfp_dreg(env, i);
+            qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
+                         i * 2, (uint32_t)v,
+                         i * 2 + 1, (uint32_t)(v >> 32),
+                         i, v);
+        }
+        qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
+    }
+}
+
 void arm32_cpu_class_init(ObjectClass *oc, void *data)
 {
     CPUClass *cc = CPU_CLASS(oc);
@@ -67,7 +150,7 @@ void arm32_cpu_class_init(ObjectClass *oc, void *data)
     cc->gdb_num_core_regs = 26;
     cc->gdb_core_xml_file = "arm-core.xml";
     cc->gdb_arch_name = arm_gdb_arch_name;
-    cc->dump_state = arm_cpu_dump_state;
+    cc->dump_state = arm32_cpu_dump_state;
 }
 
 static void arm32_cpu_instance_init(Object *obj)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index bdbbda566b..90edd5ecc1 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -20,7 +20,9 @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
+#include "qemu/qemu-print.h"
 #include "cpu.h"
+#include "cpu32.h"
 #ifdef CONFIG_TCG
 #include "hw/core/tcg-cpu-ops.h"
 #endif /* CONFIG_TCG */
@@ -814,6 +816,145 @@ static gchar *aarch64_gdb_arch_name(CPUState *cs)
     return g_strdup("aarch64");
 }
 
+static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    uint32_t psr = pstate_read(env);
+    int i;
+    int el = arm_current_el(env);
+    const char *ns_status;
+
+    qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
+    for (i = 0; i < 32; i++) {
+        if (i == 31) {
+            qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
+        } else {
+            qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
+                         (i + 2) % 3 ? " " : "\n");
+        }
+    }
+
+    if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
+        ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
+    } else {
+        ns_status = "";
+    }
+    qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
+                 psr,
+                 psr & PSTATE_N ? 'N' : '-',
+                 psr & PSTATE_Z ? 'Z' : '-',
+                 psr & PSTATE_C ? 'C' : '-',
+                 psr & PSTATE_V ? 'V' : '-',
+                 ns_status,
+                 el,
+                 psr & PSTATE_SP ? 'h' : 't');
+
+    if (cpu_isar_feature(aa64_bti, cpu)) {
+        qemu_fprintf(f, "  BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
+    }
+    if (!(flags & CPU_DUMP_FPU)) {
+        qemu_fprintf(f, "\n");
+        return;
+    }
+    if (fp_exception_el(env, el) != 0) {
+        qemu_fprintf(f, "    FPU disabled\n");
+        return;
+    }
+    qemu_fprintf(f, "     FPCR=%08x FPSR=%08x\n",
+                 vfp_get_fpcr(env), vfp_get_fpsr(env));
+
+    if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
+        int j, zcr_len = sve_zcr_len_for_el(env, el);
+
+        for (i = 0; i <= FFR_PRED_NUM; i++) {
+            bool eol;
+            if (i == FFR_PRED_NUM) {
+                qemu_fprintf(f, "FFR=");
+                /* It's last, so end the line.  */
+                eol = true;
+            } else {
+                qemu_fprintf(f, "P%02d=", i);
+                switch (zcr_len) {
+                case 0:
+                    eol = i % 8 == 7;
+                    break;
+                case 1:
+                    eol = i % 6 == 5;
+                    break;
+                case 2:
+                case 3:
+                    eol = i % 3 == 2;
+                    break;
+                default:
+                    /* More than one quadword per predicate.  */
+                    eol = true;
+                    break;
+                }
+            }
+            for (j = zcr_len / 4; j >= 0; j--) {
+                int digits;
+                if (j * 4 + 4 <= zcr_len + 1) {
+                    digits = 16;
+                } else {
+                    digits = (zcr_len % 4 + 1) * 4;
+                }
+                qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
+                             env->vfp.pregs[i].p[j],
+                             j ? ":" : eol ? "\n" : " ");
+            }
+        }
+
+        for (i = 0; i < 32; i++) {
+            if (zcr_len == 0) {
+                qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
+                             i, env->vfp.zregs[i].d[1],
+                             env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
+            } else if (zcr_len == 1) {
+                qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
+                             ":%016" PRIx64 ":%016" PRIx64 "\n",
+                             i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
+                             env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
+            } else {
+                for (j = zcr_len; j >= 0; j--) {
+                    bool odd = (zcr_len - j) % 2 != 0;
+                    if (j == zcr_len) {
+                        qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
+                    } else if (!odd) {
+                        if (j > 0) {
+                            qemu_fprintf(f, "   [%x-%x]=", j, j - 1);
+                        } else {
+                            qemu_fprintf(f, "     [%x]=", j);
+                        }
+                    }
+                    qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
+                                 env->vfp.zregs[i].d[j * 2 + 1],
+                                 env->vfp.zregs[i].d[j * 2],
+                                 odd || j == 0 ? "\n" : ":");
+                }
+            }
+        }
+    } else {
+        for (i = 0; i < 32; i++) {
+            uint64_t *q = aa64_vfp_qreg(env, i);
+            qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
+                         i, q[1], q[0], (i & 1 ? "\n" : " "));
+        }
+    }
+}
+
+static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+
+    if (is_a64(env)) {
+        aarch64_cpu_dump_state(cs, f, flags);
+    } else {
+        arm32_cpu_dump_state(cs, f, flags);
+    }
+}
+
 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
 {
     CPUClass *cc = CPU_CLASS(oc);
@@ -823,6 +964,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
     cc->gdb_num_core_regs = 34;
     cc->gdb_core_xml_file = "aarch64-core.xml";
     cc->gdb_arch_name = aarch64_gdb_arch_name;
+    cc->dump_state = arm_cpu_dump_state;
 
     object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64,
                                    aarch64_cpu_set_aarch64);
-- 
2.26.2



  parent reply	other threads:[~2021-04-14 11:58 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14 11:25 [RFC v13 00/80] arm cleanup experiment for kvm-only build Claudio Fontana
2021-04-14 11:25 ` [RFC v13 01/80] target/arm: move translate modules to tcg/ Claudio Fontana
2021-04-14 11:25 ` [RFC v13 02/80] target/arm: move helpers " Claudio Fontana
2021-04-14 11:25 ` [RFC v13 03/80] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-14 11:25 ` [RFC v13 04/80] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-04-14 11:25 ` [RFC v13 05/80] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-14 11:25 ` [RFC v13 06/80] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-14 11:25 ` [RFC v13 07/80] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-14 11:25 ` [RFC v13 08/80] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-14 11:25 ` [RFC v13 09/80] target/arm: only build psci for TCG Claudio Fontana
2021-04-14 11:25 ` [RFC v13 10/80] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-04-14 11:25 ` [RFC v13 11/80] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 12/80] target/arm: move physical address translation " Claudio Fontana
2021-04-14 11:25 ` [RFC v13 13/80] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-04-14 11:25 ` [RFC v13 14/80] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-04-14 11:25 ` [RFC v13 15/80] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-04-14 11:25 ` [RFC v13 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-04-14 11:25 ` [RFC v13 17/80] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-04-14 11:25 ` [RFC v13 18/80] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-04-14 11:25 ` [RFC v13 19/80] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-04-14 11:25 ` [RFC v13 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 21/80] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-04-14 11:25 ` [RFC v13 22/80] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 23/80] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 24/80] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-04-14 11:25 ` [RFC v13 25/80] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 26/80] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-04-14 11:25 ` [RFC v13 27/80] target/arm: new cpu32 ARM 32 bit CPU Class Claudio Fontana
2021-04-14 11:25 ` Claudio Fontana [this message]
2021-04-14 11:25 ` [RFC v13 29/80] target/arm: move a15 cpu model away from the TCG-only models Claudio Fontana
2021-04-14 11:26 ` [RFC v13 30/80] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-04-14 11:26 ` [RFC v13 31/80] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-04-14 11:26 ` [RFC v13 32/80] target/arm: fix comments style of fp_exception_el before moving it Claudio Fontana
2021-04-14 11:26 ` [RFC v13 33/80] target/arm: move fp_exception_el out of TCG helpers Claudio Fontana
2021-04-14 11:26 ` [RFC v13 34/80] target/arm: remove now useless ifndef from fp_exception_el Claudio Fontana
2021-04-14 11:26 ` [RFC v13 35/80] target/arm: make further preparation for the exception code to move Claudio Fontana
2021-04-14 11:26 ` [RFC v13 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-04-14 11:26 ` [RFC v13 37/80] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 38/80] target/arm: rename handle_semihosting to tcg_handle_semihosting Claudio Fontana
2021-04-14 11:26 ` [RFC v13 39/80] target/arm: replace CONFIG_TCG with tcg_enabled Claudio Fontana
2021-04-14 11:26 ` [RFC v13 40/80] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 41/80] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-04-14 11:26 ` [RFC v13 43/80] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-04-14 11:26 ` [RFC v13 44/80] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-04-14 11:26 ` [RFC v13 45/80] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/ Claudio Fontana
2021-04-14 11:26 ` [RFC v13 46/80] target/arm: cleanup cpu includes Claudio Fontana
2021-04-14 11:26 ` [RFC v13 47/80] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-04-14 11:26 ` [RFC v13 48/80] target/arm: remove kvm-stub.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 49/80] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-04-14 11:26 ` [RFC v13 50/80] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-04-14 11:26 ` [RFC v13 51/80] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-04-14 11:26 ` [RFC v13 52/80] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-04-14 11:26 ` [RFC v13 53/80] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-04-14 11:26 ` [RFC v13 54/80] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-04-14 11:26 ` [RFC v13 55/80] target/arm: create kvm cpu accel class Claudio Fontana
2021-04-14 11:26 ` [RFC v13 56/80] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-04-14 11:26 ` [RFC v13 57/80] target/arm: add tcg cpu accel class Claudio Fontana
2021-04-14 11:26 ` [RFC v13 58/80] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-04-14 11:26 ` [RFC v13 59/80] target/arm: cpu-sve: new module Claudio Fontana
2021-04-14 11:26 ` [RFC v13 60/80] target/arm: cpu-sve: rename functions according to module prefix Claudio Fontana
2021-04-14 11:26 ` [RFC v13 61/80] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-04-14 11:26 ` [RFC v13 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool Claudio Fontana
2021-04-14 11:26 ` [RFC v13 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules Claudio Fontana
2021-04-14 11:26 ` [RFC v13 67/80] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 68/80] target/arm: tcg-sve: import narrow_vq and change_el functions Claudio Fontana
2021-04-14 11:26 ` [RFC v13 69/80] target/arm: tcg-sve: rename the " Claudio Fontana
2021-04-14 11:26 ` [RFC v13 70/80] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-04-14 11:26 ` [RFC v13 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Claudio Fontana
2021-04-14 11:26 ` [RFC v13 72/80] target/arm: cpu-common: wrap a64-only check with is_a64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 73/80] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-04-14 11:26 ` [RFC v13 74/80] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig Claudio Fontana
2021-04-14 11:26 ` [RFC v13 75/80] target/arm: move arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 76/80] target/arm: cpu64: rename arm_cpu_finalize_features Claudio Fontana
2021-04-14 11:26 ` [RFC v13 77/80] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features Claudio Fontana
2021-04-14 11:26 ` [RFC v13 78/80] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-04-14 11:26 ` [RFC v13 79/80] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-04-14 11:26 ` [RFC v13 80/80] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana

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