From: Ilya Leoshkevich <iii@linux.ibm.com>
To: Cornelia Huck <cohuck@redhat.com>, Thomas Huth <thuth@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
David Hildenbrand <david@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Peter Maydell <peter.maydell@linaro.org>,
Max Filippov <jcmvbkbc@gmail.com>
Cc: Christian Borntraeger <borntraeger@de.ibm.com>,
qemu-s390x@nongnu.org, qemu-arm@nongnu.org,
qemu-devel@nongnu.org, Ilya Leoshkevich <iii@linux.ibm.com>
Subject: [PATCH v4 2/4] target/arm: Make sure that commpage's tb->size != 0
Date: Thu, 15 Apr 2021 15:03:03 +0200 [thread overview]
Message-ID: <20210415130305.28640-3-iii@linux.ibm.com> (raw)
In-Reply-To: <20210415130305.28640-1-iii@linux.ibm.com>
tb_gen_code() assumes that tb->size must never be zero, otherwise it
may produce spurious exceptions. For ARM this may happen when creating
a translation block for the commpage.
Fix by pretending that commpage translation blocks have at least one
instruction.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
target/arm/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 62b1c2081b..885f69b044 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9060,6 +9060,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
unsigned int insn;
if (arm_pre_translate_insn(dc)) {
+ dc->base.pc_next += 4;
return;
}
--
2.29.2
next prev parent reply other threads:[~2021-04-15 13:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-15 13:03 [PATCH v4 0/4] accel/tcg: Make sure that tb->size != 0 after translation Ilya Leoshkevich
2021-04-15 13:03 ` [PATCH v4 1/4] target/s390x: Fix translation exception on illegal instruction Ilya Leoshkevich
2021-04-15 13:03 ` Ilya Leoshkevich [this message]
2021-04-16 14:10 ` [PATCH v4 2/4] target/arm: Make sure that commpage's tb->size != 0 Peter Maydell
2021-04-16 15:38 ` Ilya Leoshkevich
2021-04-15 13:03 ` [PATCH v4 3/4] target/xtensa: Make sure that " Ilya Leoshkevich
2021-04-15 20:14 ` Max Filippov
2021-04-15 13:03 ` [PATCH v4 4/4] accel/tcg: Assert that tb->size != 0 after translation Ilya Leoshkevich
2021-04-15 15:39 ` [PATCH v4 0/4] accel/tcg: Make sure " Cornelia Huck
2021-04-16 11:53 ` Ilya Leoshkevich
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