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From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Roman Bolshakov <r.bolshakov@yadro.com>,
	Claudio Fontana <cfontana@suse.de>,
	Eduardo Habkost <ehabkost@redhat.com>,
	qemu-devel@nongnu.org
Subject: [RFC v14 29/80] target/arm: move a15 cpu model away from the TCG-only models
Date: Fri, 16 Apr 2021 18:27:33 +0200
Message-ID: <20210416162824.25131-30-cfontana@suse.de> (raw)
In-Reply-To: <20210416162824.25131-1-cfontana@suse.de>

Cortex-A15 is the only ARM cpu class we need in KVM too.

We will be able to move it to tcg/ once the board code and configurations
are fixed.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
 target/arm/cpu32.h   |  4 +++
 target/arm/cpu32.c   | 73 ++++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu_tcg.c | 67 ----------------------------------------
 3 files changed, 77 insertions(+), 67 deletions(-)

diff --git a/target/arm/cpu32.h b/target/arm/cpu32.h
index 128d0c9247..abd575d47d 100644
--- a/target/arm/cpu32.h
+++ b/target/arm/cpu32.h
@@ -21,8 +21,12 @@
 #ifndef ARM_CPU32_H
 #define ARM_CPU32_H
 
+#include "cpregs.h"
+
 void arm32_cpu_dump_state(CPUState *cs, FILE *f, int flags);
 void arm32_cpu_class_init(ObjectClass *oc, void *data);
 void arm32_cpu_register(const ARMCPUInfo *info);
+void cortex_a15_initfn(Object *obj);
+extern const ARMCPRegInfo cortexa15_cp_reginfo[];
 
 #endif /* ARM_CPU32_H */
diff --git a/target/arm/cpu32.c b/target/arm/cpu32.c
index c03f420ba2..a6ba91ae08 100644
--- a/target/arm/cpu32.c
+++ b/target/arm/cpu32.c
@@ -43,8 +43,81 @@
 #include "cpu-mmu.h"
 #include "cpu32.h"
 
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+
+#ifndef CONFIG_USER_ONLY
+static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    MachineState *ms = MACHINE(qdev_get_machine());
+
+    /*
+     * Linux wants the number of processors from here.
+     * Might as well set the interrupt-controller bit too.
+     */
+    return ((ms->smp.cpus - 1) << 24) | (1 << 23);
+}
+#endif
+
+const ARMCPRegInfo cortexa15_cp_reginfo[] = {
+#ifndef CONFIG_USER_ONLY
+    { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
+      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
+      .writefn = arm_cp_write_ignore, },
+#endif
+    { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    REGINFO_SENTINEL
+};
+
+void cortex_a15_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a15";
+    set_feature(&cpu->env, ARM_FEATURE_V7VE);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
+    cpu->midr = 0x412fc0f1;
+    cpu->reset_fpsid = 0x410430f0;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x11111111;
+    cpu->ctr = 0x8444c004;
+    cpu->reset_sctlr = 0x00c50078;
+    cpu->isar.id_pfr0 = 0x00001131;
+    cpu->isar.id_pfr1 = 0x00011011;
+    cpu->isar.id_dfr0 = 0x02010555;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x20000000;
+    cpu->isar.id_mmfr2 = 0x01240000;
+    cpu->isar.id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232041;
+    cpu->isar.id_isar3 = 0x11112131;
+    cpu->isar.id_isar4 = 0x10011142;
+    cpu->isar.dbgdidr = 0x3515f021;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
+    define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
+}
+
+#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
+
 /* we can move this to tcg/ after the cleanup of ARM boards configurations */
 static const ARMCPUInfo arm32_cpus[] = {
+#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
+#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
 };
 
 static gchar *arm_gdb_arch_name(CPUState *cs)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 0d5c8340b7..d120250b18 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -378,30 +378,6 @@ static void cortex_a9_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 }
 
-#ifndef CONFIG_USER_ONLY
-static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
-    MachineState *ms = MACHINE(qdev_get_machine());
-
-    /*
-     * Linux wants the number of processors from here.
-     * Might as well set the interrupt-controller bit too.
-     */
-    return ((ms->smp.cpus - 1) << 24) | (1 << 23);
-}
-#endif
-
-static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
-#ifndef CONFIG_USER_ONLY
-    { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
-      .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
-      .writefn = arm_cp_write_ignore, },
-#endif
-    { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-    REGINFO_SENTINEL
-};
-
 static void cortex_a7_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -448,48 +424,6 @@ static void cortex_a7_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
 }
 
-static void cortex_a15_initfn(Object *obj)
-{
-    ARMCPU *cpu = ARM_CPU(obj);
-
-    cpu->dtb_compatible = "arm,cortex-a15";
-    set_feature(&cpu->env, ARM_FEATURE_V7VE);
-    set_feature(&cpu->env, ARM_FEATURE_NEON);
-    set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
-    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
-    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-    set_feature(&cpu->env, ARM_FEATURE_EL2);
-    set_feature(&cpu->env, ARM_FEATURE_EL3);
-    set_feature(&cpu->env, ARM_FEATURE_PMU);
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
-    cpu->midr = 0x412fc0f1;
-    cpu->reset_fpsid = 0x410430f0;
-    cpu->isar.mvfr0 = 0x10110222;
-    cpu->isar.mvfr1 = 0x11111111;
-    cpu->ctr = 0x8444c004;
-    cpu->reset_sctlr = 0x00c50078;
-    cpu->isar.id_pfr0 = 0x00001131;
-    cpu->isar.id_pfr1 = 0x00011011;
-    cpu->isar.id_dfr0 = 0x02010555;
-    cpu->id_afr0 = 0x00000000;
-    cpu->isar.id_mmfr0 = 0x10201105;
-    cpu->isar.id_mmfr1 = 0x20000000;
-    cpu->isar.id_mmfr2 = 0x01240000;
-    cpu->isar.id_mmfr3 = 0x02102211;
-    cpu->isar.id_isar0 = 0x02101110;
-    cpu->isar.id_isar1 = 0x13112111;
-    cpu->isar.id_isar2 = 0x21232041;
-    cpu->isar.id_isar3 = 0x11112131;
-    cpu->isar.id_isar4 = 0x10011142;
-    cpu->isar.dbgdidr = 0x3515f021;
-    cpu->clidr = 0x0a200023;
-    cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
-    cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
-    cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
-    define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
-}
-
 static void cortex_m0_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -1021,7 +955,6 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
-    { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
                              .class_init = arm_v7m_class_init },
     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
-- 
2.26.2



  parent reply index

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-16 16:27 [RFC v14 00/80] arm cleanup experiment for kvm-only build Claudio Fontana
2021-04-16 16:27 ` [RFC v14 01/80] target/arm: move translate modules to tcg/ Claudio Fontana
2021-04-16 16:27 ` [RFC v14 02/80] target/arm: move helpers " Claudio Fontana
2021-04-16 16:27 ` [RFC v14 03/80] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-16 16:27 ` [RFC v14 04/80] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-04-20  9:53   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 05/80] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-16 16:27 ` [RFC v14 06/80] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-16 16:27 ` [RFC v14 07/80] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-16 16:27 ` [RFC v14 08/80] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-16 16:27 ` [RFC v14 09/80] target/arm: only build psci for TCG Claudio Fontana
2021-04-20 10:28   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 10/80] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 11/80] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-04-20 10:30   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 12/80] target/arm: move physical address translation " Claudio Fontana
2021-04-16 16:27 ` [RFC v14 13/80] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-04-20 10:33   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 14/80] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-04-20 10:56   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 15/80] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-04-20 10:57   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-04-16 16:27 ` [RFC v14 17/80] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-04-16 16:27 ` [RFC v14 18/80] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-04-16 16:27 ` [RFC v14 19/80] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-04-16 16:27 ` [RFC v14 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 21/80] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 22/80] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 23/80] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 24/80] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 25/80] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 26/80] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-04-16 16:27 ` [RFC v14 27/80] target/arm: new cpu32 ARM 32 bit CPU Class Claudio Fontana
2021-04-16 16:27 ` [RFC v14 28/80] target/arm: split 32bit and 64bit arm dump state Claudio Fontana
2021-04-16 16:27 ` Claudio Fontana [this message]
2021-04-16 16:27 ` [RFC v14 30/80] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-04-16 16:27 ` [RFC v14 31/80] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 32/80] target/arm: fix comments style of fp_exception_el before moving it Claudio Fontana
2021-04-16 16:27 ` [RFC v14 33/80] target/arm: move fp_exception_el out of TCG helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 34/80] target/arm: remove now useless ifndef from fp_exception_el Claudio Fontana
2021-04-16 16:27 ` [RFC v14 35/80] target/arm: make further preparation for the exception code to move Claudio Fontana
2021-04-16 16:27 ` [RFC v14 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-04-16 16:27 ` [RFC v14 37/80] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 38/80] target/arm: rename handle_semihosting to tcg_handle_semihosting Claudio Fontana
2021-04-16 16:27 ` [RFC v14 39/80] target/arm: replace CONFIG_TCG with tcg_enabled Claudio Fontana
2021-04-16 16:27 ` [RFC v14 40/80] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 41/80] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-04-16 16:27 ` [RFC v14 43/80] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-04-16 16:27 ` [RFC v14 44/80] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-04-16 16:27 ` [RFC v14 45/80] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/ Claudio Fontana
2021-04-16 16:27 ` [RFC v14 46/80] target/arm: cleanup cpu includes Claudio Fontana
2021-04-16 16:27 ` [RFC v14 47/80] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-04-16 16:27 ` [RFC v14 48/80] target/arm: remove kvm-stub.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 49/80] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-04-16 16:27 ` [RFC v14 50/80] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-04-16 16:27 ` [RFC v14 51/80] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-04-16 16:27 ` [RFC v14 52/80] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-04-19 10:22   ` Thomas Huth
2021-04-19 10:24     ` Claudio Fontana
2021-04-19 10:29       ` Thomas Huth
2021-04-19 10:33         ` Claudio Fontana
2021-04-20  9:34           ` Alex Bennée
2021-04-20 10:53             ` Claudio Fontana
2021-04-16 16:27 ` [RFC v14 53/80] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-04-16 16:27 ` [RFC v14 54/80] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-05-05 12:27   ` Philippe Mathieu-Daudé
2021-04-16 16:27 ` [RFC v14 55/80] target/arm: create kvm cpu accel class Claudio Fontana
2021-04-16 16:28 ` [RFC v14 56/80] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-04-16 16:28 ` [RFC v14 57/80] target/arm: add tcg cpu accel class Claudio Fontana
2021-04-16 16:28 ` [RFC v14 58/80] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-04-16 16:28 ` [RFC v14 59/80] target/arm: cpu-sve: new module Claudio Fontana
2021-04-16 16:28 ` [RFC v14 60/80] target/arm: cpu-sve: rename functions according to module prefix Claudio Fontana
2021-04-16 16:28 ` [RFC v14 61/80] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-04-16 16:28 ` [RFC v14 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool Claudio Fontana
2021-04-16 16:28 ` [RFC v14 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules Claudio Fontana
2021-04-16 16:28 ` [RFC v14 67/80] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 68/80] target/arm: tcg-sve: import narrow_vq and change_el functions Claudio Fontana
2021-04-16 16:28 ` [RFC v14 69/80] target/arm: tcg-sve: rename the " Claudio Fontana
2021-04-16 16:28 ` [RFC v14 70/80] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-04-16 16:28 ` [RFC v14 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Claudio Fontana
2021-04-16 16:28 ` [RFC v14 72/80] target/arm: cpu-common: wrap a64-only check with is_a64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 73/80] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-04-16 16:28 ` [RFC v14 74/80] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig Claudio Fontana
2021-04-16 16:28 ` [RFC v14 75/80] target/arm: move arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 76/80] target/arm: cpu64: rename arm_cpu_finalize_features Claudio Fontana
2021-04-16 16:28 ` [RFC v14 77/80] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features Claudio Fontana
2021-04-16 16:28 ` [RFC v14 78/80] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-04-16 16:28 ` [RFC v14 79/80] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-04-16 16:28 ` [RFC v14 80/80] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana

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