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From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Roman Bolshakov <r.bolshakov@yadro.com>,
	Claudio Fontana <cfontana@suse.de>,
	Eduardo Habkost <ehabkost@redhat.com>,
	qemu-devel@nongnu.org
Subject: [RFC v14 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el
Date: Fri, 16 Apr 2021 18:28:15 +0200
Message-ID: <20210416162824.25131-72-cfontana@suse.de> (raw)
In-Reply-To: <20210416162824.25131-1-cfontana@suse.de>

use a canonical module prefix followed by the get_zcr_len_for_el()
method name. Also rename the static internal auxiliary function,
where the module prefix is not necessary.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu-sve.h     | 2 +-
 target/arm/arch_dump.c   | 2 +-
 target/arm/cpu-sve.c     | 6 +++---
 target/arm/cpu64.c       | 2 +-
 target/arm/tcg/cpregs.c  | 4 ++--
 target/arm/tcg/helper.c  | 4 ++--
 target/arm/tcg/tcg-sve.c | 4 ++--
 7 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h
index 1512c56a6b..c83508ea0a 100644
--- a/target/arm/cpu-sve.h
+++ b/target/arm/cpu-sve.h
@@ -35,6 +35,6 @@ void cpu_sve_add_props(Object *obj);
 void cpu_sve_add_props_max(Object *obj);
 
 /* return the vector length for EL */
-uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
+uint32_t cpu_sve_get_zcr_len_for_el(CPUARMState *env, int el);
 
 #endif /* CPU_SVE_H */
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
index 9b2e76f5a7..f192c8df97 100644
--- a/target/arm/arch_dump.c
+++ b/target/arm/arch_dump.c
@@ -168,7 +168,7 @@ static off_t sve_fpcr_offset(uint32_t vq)
 
 static uint32_t sve_current_vq(CPUARMState *env)
 {
-    return sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
+    return cpu_sve_get_zcr_len_for_el(env, arm_current_el(env)) + 1;
 }
 
 static size_t sve_size_vq(uint32_t vq)
diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c
index e8e817e110..1bc8c0bdb0 100644
--- a/target/arm/cpu-sve.c
+++ b/target/arm/cpu-sve.c
@@ -289,7 +289,7 @@ void cpu_sve_add_props_max(Object *obj)
     object_property_add(obj, "sve-max-vq", "uint32", get_prop_max_vq, set_prop_max_vq, NULL, NULL);
 }
 
-static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+static uint32_t get_valid_len(ARMCPU *cpu, uint32_t start_len)
 {
     uint32_t end_len;
 
@@ -304,7 +304,7 @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
 /*
  * Given that SVE is enabled, return the vector length for EL.
  */
-uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
+uint32_t cpu_sve_get_zcr_len_for_el(CPUARMState *env, int el)
 {
     ARMCPU *cpu = env_archcpu(env);
     uint32_t zcr_len = cpu->sve_max_vq - 1;
@@ -319,5 +319,5 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
         zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
     }
 
-    return sve_zcr_get_valid_len(cpu, zcr_len);
+    return get_valid_len(cpu, zcr_len);
 }
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 8c96a108fc..b1b5cf5cc9 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -535,7 +535,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
                  vfp_get_fpcr(env), vfp_get_fpsr(env));
 
     if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
-        int j, zcr_len = sve_zcr_len_for_el(env, el);
+        int j, zcr_len = cpu_sve_get_zcr_len_for_el(env, el);
 
         for (i = 0; i <= FFR_PRED_NUM; i++) {
             bool eol;
diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c
index 0f4460e28a..c4117b68f5 100644
--- a/target/arm/tcg/cpregs.c
+++ b/target/arm/tcg/cpregs.c
@@ -5802,7 +5802,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                       uint64_t value)
 {
     int cur_el = arm_current_el(env);
-    int old_len = sve_zcr_len_for_el(env, cur_el);
+    int old_len = cpu_sve_get_zcr_len_for_el(env, cur_el);
     int new_len;
 
     /* Bits other than [3:0] are RAZ/WI.  */
@@ -5813,7 +5813,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
      * Because we arrived here, we know both FP and SVE are enabled;
      * otherwise we would have trapped access to the ZCR_ELn register.
      */
-    new_len = sve_zcr_len_for_el(env, cur_el);
+    new_len = cpu_sve_get_zcr_len_for_el(env, cur_el);
     if (new_len < old_len) {
         tcg_sve_narrow_vq(env, new_len + 1);
     }
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 04ea37e101..a10b8a62dc 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -186,7 +186,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
          * We report in Vector Granules (VG) which is 64bit in a Z reg
          * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
          */
-        int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
+        int vq = cpu_sve_get_zcr_len_for_el(env, arm_current_el(env)) + 1;
         return gdb_get_reg64(buf, vq * 2);
     }
     default:
@@ -1023,7 +1023,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
         if (sve_el != 0 && fp_el == 0) {
             zcr_len = 0;
         } else {
-            zcr_len = sve_zcr_len_for_el(env, el);
+            zcr_len = cpu_sve_get_zcr_len_for_el(env, el);
         }
         flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
         flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c
index 25d5a5867c..80a37caf6e 100644
--- a/target/arm/tcg/tcg-sve.c
+++ b/target/arm/tcg/tcg-sve.c
@@ -155,10 +155,10 @@ void tcg_sve_change_el(CPUARMState *env, int old_el,
      */
     old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
     old_len = (old_a64 && !sve_exception_el(env, old_el)
-               ? sve_zcr_len_for_el(env, old_el) : 0);
+               ? cpu_sve_get_zcr_len_for_el(env, old_el) : 0);
     new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
     new_len = (new_a64 && !sve_exception_el(env, new_el)
-               ? sve_zcr_len_for_el(env, new_el) : 0);
+               ? cpu_sve_get_zcr_len_for_el(env, new_el) : 0);
 
     /* When changing vector length, clear inaccessible state.  */
     if (new_len < old_len) {
-- 
2.26.2



  parent reply index

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-16 16:27 [RFC v14 00/80] arm cleanup experiment for kvm-only build Claudio Fontana
2021-04-16 16:27 ` [RFC v14 01/80] target/arm: move translate modules to tcg/ Claudio Fontana
2021-04-16 16:27 ` [RFC v14 02/80] target/arm: move helpers " Claudio Fontana
2021-04-16 16:27 ` [RFC v14 03/80] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-16 16:27 ` [RFC v14 04/80] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-04-20  9:53   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 05/80] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-16 16:27 ` [RFC v14 06/80] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-16 16:27 ` [RFC v14 07/80] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-16 16:27 ` [RFC v14 08/80] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-16 16:27 ` [RFC v14 09/80] target/arm: only build psci for TCG Claudio Fontana
2021-04-20 10:28   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 10/80] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 11/80] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-04-20 10:30   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 12/80] target/arm: move physical address translation " Claudio Fontana
2021-04-16 16:27 ` [RFC v14 13/80] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-04-20 10:33   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 14/80] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-04-20 10:56   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 15/80] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-04-20 10:57   ` Alex Bennée
2021-04-16 16:27 ` [RFC v14 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-04-16 16:27 ` [RFC v14 17/80] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-04-16 16:27 ` [RFC v14 18/80] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-04-16 16:27 ` [RFC v14 19/80] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-04-16 16:27 ` [RFC v14 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 21/80] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 22/80] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 23/80] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 24/80] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 25/80] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-04-16 16:27 ` [RFC v14 26/80] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-04-16 16:27 ` [RFC v14 27/80] target/arm: new cpu32 ARM 32 bit CPU Class Claudio Fontana
2021-04-16 16:27 ` [RFC v14 28/80] target/arm: split 32bit and 64bit arm dump state Claudio Fontana
2021-04-16 16:27 ` [RFC v14 29/80] target/arm: move a15 cpu model away from the TCG-only models Claudio Fontana
2021-04-16 16:27 ` [RFC v14 30/80] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-04-16 16:27 ` [RFC v14 31/80] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 32/80] target/arm: fix comments style of fp_exception_el before moving it Claudio Fontana
2021-04-16 16:27 ` [RFC v14 33/80] target/arm: move fp_exception_el out of TCG helpers Claudio Fontana
2021-04-16 16:27 ` [RFC v14 34/80] target/arm: remove now useless ifndef from fp_exception_el Claudio Fontana
2021-04-16 16:27 ` [RFC v14 35/80] target/arm: make further preparation for the exception code to move Claudio Fontana
2021-04-16 16:27 ` [RFC v14 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-04-16 16:27 ` [RFC v14 37/80] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 38/80] target/arm: rename handle_semihosting to tcg_handle_semihosting Claudio Fontana
2021-04-16 16:27 ` [RFC v14 39/80] target/arm: replace CONFIG_TCG with tcg_enabled Claudio Fontana
2021-04-16 16:27 ` [RFC v14 40/80] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 41/80] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-04-16 16:27 ` [RFC v14 43/80] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-04-16 16:27 ` [RFC v14 44/80] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-04-16 16:27 ` [RFC v14 45/80] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/ Claudio Fontana
2021-04-16 16:27 ` [RFC v14 46/80] target/arm: cleanup cpu includes Claudio Fontana
2021-04-16 16:27 ` [RFC v14 47/80] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-04-16 16:27 ` [RFC v14 48/80] target/arm: remove kvm-stub.c Claudio Fontana
2021-04-16 16:27 ` [RFC v14 49/80] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-04-16 16:27 ` [RFC v14 50/80] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-04-16 16:27 ` [RFC v14 51/80] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-04-16 16:27 ` [RFC v14 52/80] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-04-19 10:22   ` Thomas Huth
2021-04-19 10:24     ` Claudio Fontana
2021-04-19 10:29       ` Thomas Huth
2021-04-19 10:33         ` Claudio Fontana
2021-04-20  9:34           ` Alex Bennée
2021-04-20 10:53             ` Claudio Fontana
2021-04-16 16:27 ` [RFC v14 53/80] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-04-16 16:27 ` [RFC v14 54/80] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-05-05 12:27   ` Philippe Mathieu-Daudé
2021-04-16 16:27 ` [RFC v14 55/80] target/arm: create kvm cpu accel class Claudio Fontana
2021-04-16 16:28 ` [RFC v14 56/80] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-04-16 16:28 ` [RFC v14 57/80] target/arm: add tcg cpu accel class Claudio Fontana
2021-04-16 16:28 ` [RFC v14 58/80] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-04-16 16:28 ` [RFC v14 59/80] target/arm: cpu-sve: new module Claudio Fontana
2021-04-16 16:28 ` [RFC v14 60/80] target/arm: cpu-sve: rename functions according to module prefix Claudio Fontana
2021-04-16 16:28 ` [RFC v14 61/80] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-04-16 16:28 ` [RFC v14 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool Claudio Fontana
2021-04-16 16:28 ` [RFC v14 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules Claudio Fontana
2021-04-16 16:28 ` [RFC v14 67/80] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 68/80] target/arm: tcg-sve: import narrow_vq and change_el functions Claudio Fontana
2021-04-16 16:28 ` [RFC v14 69/80] target/arm: tcg-sve: rename the " Claudio Fontana
2021-04-16 16:28 ` [RFC v14 70/80] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-04-16 16:28 ` Claudio Fontana [this message]
2021-04-16 16:28 ` [RFC v14 72/80] target/arm: cpu-common: wrap a64-only check with is_a64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 73/80] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-04-16 16:28 ` [RFC v14 74/80] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig Claudio Fontana
2021-04-16 16:28 ` [RFC v14 75/80] target/arm: move arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-04-16 16:28 ` [RFC v14 76/80] target/arm: cpu64: rename arm_cpu_finalize_features Claudio Fontana
2021-04-16 16:28 ` [RFC v14 77/80] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features Claudio Fontana
2021-04-16 16:28 ` [RFC v14 78/80] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-04-16 16:28 ` [RFC v14 79/80] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-04-16 16:28 ` [RFC v14 80/80] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana

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