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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Stephen Long <steplong@quicinc.com>
Subject: [PATCH v5 25/81] target/arm: Implement SVE2 floating-point pairwise
Date: Fri, 16 Apr 2021 14:01:44 -0700
Message-ID: <20210416210240.1591291-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210416210240.1591291-1-richard.henderson@linaro.org>

From: Stephen Long <steplong@quicinc.com>

Signed-off-by: Stephen Long <steplong@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Load all inputs before writing any output (laurent desnogues)
---
 target/arm/helper-sve.h    | 35 +++++++++++++++++++++++++++++
 target/arm/sve.decode      |  8 +++++++
 target/arm/sve_helper.c    | 46 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-sve.c | 25 +++++++++++++++++++++
 4 files changed, 114 insertions(+)

diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index b302203ce8..a033b5f6b2 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2443,3 +2443,38 @@ DEF_HELPER_FLAGS_3(sve2_uqxtnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(sve2_sqxtunt_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(sve2_sqxtunt_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(sve2_sqxtunt_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 19866ec4c6..9c75ac94c0 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1284,3 +1284,11 @@ UQXTNB          01000101 .. 1 ..... 010 010 ..... .....  @rd_rn_tszimm_shl
 UQXTNT          01000101 .. 1 ..... 010 011 ..... .....  @rd_rn_tszimm_shl
 SQXTUNB         01000101 .. 1 ..... 010 100 ..... .....  @rd_rn_tszimm_shl
 SQXTUNT         01000101 .. 1 ..... 010 101 ..... .....  @rd_rn_tszimm_shl
+
+## SVE2 floating-point pairwise operations
+
+FADDP           01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm
+FMAXNMP         01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm
+FMINNMP         01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm
+FMAXP           01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm
+FMINP           01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 7dca67785a..11f228144c 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -890,6 +890,52 @@ DO_ZPZZ_PAIR_D(sve2_sminp_zpzz_d, int64_t, DO_MIN)
 #undef DO_ZPZZ_PAIR
 #undef DO_ZPZZ_PAIR_D
 
+#define DO_ZPZZ_PAIR_FP(NAME, TYPE, H, OP)                              \
+void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg,               \
+                  void *status, uint32_t desc)                          \
+{                                                                       \
+    intptr_t i, opr_sz = simd_oprsz(desc);                              \
+    for (i = 0; i < opr_sz; ) {                                         \
+        uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));                 \
+        do {                                                            \
+            TYPE n0 = *(TYPE *)(vn + H(i));                             \
+            TYPE m0 = *(TYPE *)(vm + H(i));                             \
+            TYPE n1 = *(TYPE *)(vn + H(i + sizeof(TYPE)));              \
+            TYPE m1 = *(TYPE *)(vm + H(i + sizeof(TYPE)));              \
+            if (pg & 1) {                                               \
+                *(TYPE *)(vd + H(i)) = OP(n0, n1, status);              \
+            }                                                           \
+            i += sizeof(TYPE), pg >>= sizeof(TYPE);                     \
+            if (pg & 1) {                                               \
+                *(TYPE *)(vd + H(i)) = OP(m0, m1, status);              \
+            }                                                           \
+            i += sizeof(TYPE), pg >>= sizeof(TYPE);                     \
+        } while (i & 15);                                               \
+    }                                                                   \
+}
+
+DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_h, float16, H1_2, float16_add)
+DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_s, float32, H1_4, float32_add)
+DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_d, float64,     , float64_add)
+
+DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_h, float16, H1_2, float16_maxnum)
+DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_s, float32, H1_4, float32_maxnum)
+DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_d, float64,     , float64_maxnum)
+
+DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_h, float16, H1_2, float16_minnum)
+DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_s, float32, H1_4, float32_minnum)
+DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_d, float64,     , float64_minnum)
+
+DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_h, float16, H1_2, float16_max)
+DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_s, float32, H1_4, float32_max)
+DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_d, float64,     , float64_max)
+
+DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_h, float16, H1_2, float16_min)
+DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_s, float32, H1_4, float32_min)
+DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_d, float64,     , float64_min)
+
+#undef DO_ZPZZ_PAIR_FP
+
 /* Three-operand expander, controlled by a predicate, in which the
  * third operand is "wide".  That is, for D = N op M, the same 64-bit
  * value of M is used with all of the narrower values of N.
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index b8ced82e4e..1670bcadb1 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6697,3 +6697,28 @@ static bool trans_SQXTUNT(DisasContext *s, arg_rri_esz *a)
     };
     return do_sve2_narrow_extract(s, a, ops);
 }
+
+static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a,
+                            gen_helper_gvec_4_ptr *fn)
+{
+    if (!dc_isar_feature(aa64_sve2, s)) {
+        return false;
+    }
+    return do_zpzz_fp(s, a, fn);
+}
+
+#define DO_SVE2_ZPZZ_FP(NAME, name)                                         \
+static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a)                  \
+{                                                                           \
+    static gen_helper_gvec_4_ptr * const fns[4] = {                         \
+        NULL,                            gen_helper_sve2_##name##_zpzz_h,   \
+        gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d    \
+    };                                                                      \
+    return do_sve2_zpzz_fp(s, a, fns[a->esz]);                              \
+}
+
+DO_SVE2_ZPZZ_FP(FADDP, faddp)
+DO_SVE2_ZPZZ_FP(FMAXNMP, fmaxnmp)
+DO_SVE2_ZPZZ_FP(FMINNMP, fminnmp)
+DO_SVE2_ZPZZ_FP(FMAXP, fmaxp)
+DO_SVE2_ZPZZ_FP(FMINP, fminp)
-- 
2.25.1



  parent reply index

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-16 21:01 [PATCH v5 for-6.1 00/81] target/arm: Implement SVE2 Richard Henderson
2021-04-16 21:01 ` [PATCH v5 01/81] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 Richard Henderson
2021-04-16 21:01 ` [PATCH v5 02/81] target/arm: Implement SVE2 Integer Multiply - Unpredicated Richard Henderson
2021-04-16 21:01 ` [PATCH v5 03/81] target/arm: Implement SVE2 integer pairwise add and accumulate long Richard Henderson
2021-04-16 21:01 ` [PATCH v5 04/81] target/arm: Implement SVE2 integer unary operations (predicated) Richard Henderson
2021-04-16 21:01 ` [PATCH v5 05/81] target/arm: Split out saturating/rounding shifts from neon Richard Henderson
2021-04-16 21:01 ` [PATCH v5 06/81] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) Richard Henderson
2021-04-16 21:01 ` [PATCH v5 07/81] target/arm: Implement SVE2 integer halving add/subtract (predicated) Richard Henderson
2021-04-16 21:01 ` [PATCH v5 08/81] target/arm: Implement SVE2 integer pairwise arithmetic Richard Henderson
2021-04-16 21:01 ` [PATCH v5 09/81] target/arm: Implement SVE2 saturating add/subtract (predicated) Richard Henderson
2021-04-16 21:01 ` [PATCH v5 10/81] target/arm: Implement SVE2 integer add/subtract long Richard Henderson
2021-04-16 21:01 ` [PATCH v5 11/81] target/arm: Implement SVE2 integer add/subtract interleaved long Richard Henderson
2021-04-16 21:01 ` [PATCH v5 12/81] target/arm: Implement SVE2 integer add/subtract wide Richard Henderson
2021-04-16 21:01 ` [PATCH v5 13/81] target/arm: Implement SVE2 integer multiply long Richard Henderson
2021-04-16 21:01 ` [PATCH v5 14/81] target/arm: Implement PMULLB and PMULLT Richard Henderson
2021-04-16 21:01 ` [PATCH v5 15/81] target/arm: Implement SVE2 bitwise shift left long Richard Henderson
2021-04-16 21:01 ` [PATCH v5 16/81] target/arm: Implement SVE2 bitwise exclusive-or interleaved Richard Henderson
2021-04-16 21:01 ` [PATCH v5 17/81] target/arm: Implement SVE2 bitwise permute Richard Henderson
2021-04-16 21:01 ` [PATCH v5 18/81] target/arm: Implement SVE2 complex integer add Richard Henderson
2021-04-16 21:01 ` [PATCH v5 19/81] target/arm: Implement SVE2 integer absolute difference and accumulate long Richard Henderson
2021-04-16 21:01 ` [PATCH v5 20/81] target/arm: Implement SVE2 integer add/subtract long with carry Richard Henderson
2021-04-16 21:01 ` [PATCH v5 21/81] target/arm: Implement SVE2 bitwise shift right and accumulate Richard Henderson
2021-04-16 21:01 ` [PATCH v5 22/81] target/arm: Implement SVE2 bitwise shift and insert Richard Henderson
2021-04-16 21:01 ` [PATCH v5 23/81] target/arm: Implement SVE2 integer absolute difference and accumulate Richard Henderson
2021-04-16 21:01 ` [PATCH v5 24/81] target/arm: Implement SVE2 saturating extract narrow Richard Henderson
2021-04-16 21:01 ` Richard Henderson [this message]
2021-04-16 21:01 ` [PATCH v5 26/81] target/arm: Implement SVE2 SHRN, RSHRN Richard Henderson
2021-04-16 21:01 ` [PATCH v5 27/81] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN Richard Henderson
2021-04-16 21:01 ` [PATCH v5 28/81] target/arm: Implement SVE2 UQSHRN, UQRSHRN Richard Henderson
2021-04-16 21:01 ` [PATCH v5 29/81] target/arm: Implement SVE2 SQSHRN, SQRSHRN Richard Henderson
2021-04-16 21:01 ` [PATCH v5 30/81] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS Richard Henderson
2021-04-16 21:01 ` [PATCH v5 31/81] target/arm: Implement SVE2 WHILERW, WHILEWR Richard Henderson
2021-04-16 21:01 ` [PATCH v5 32/81] target/arm: Implement SVE2 bitwise ternary operations Richard Henderson
2021-04-16 21:01 ` [PATCH v5 33/81] target/arm: Implement SVE2 MATCH, NMATCH Richard Henderson
2021-04-16 21:01 ` [PATCH v5 34/81] target/arm: Implement SVE2 saturating multiply-add long Richard Henderson
2021-04-16 21:01 ` [PATCH v5 35/81] target/arm: Implement SVE2 saturating multiply-add high Richard Henderson
2021-04-16 21:01 ` [PATCH v5 36/81] target/arm: Implement SVE2 integer multiply-add long Richard Henderson
2021-04-16 21:01 ` [PATCH v5 37/81] target/arm: Implement SVE2 complex integer multiply-add Richard Henderson
2021-04-16 21:01 ` [PATCH v5 38/81] target/arm: Implement SVE2 ADDHNB, ADDHNT Richard Henderson
2021-04-16 21:01 ` [PATCH v5 39/81] target/arm: Implement SVE2 RADDHNB, RADDHNT Richard Henderson
2021-04-16 21:01 ` [PATCH v5 40/81] target/arm: Implement SVE2 SUBHNB, SUBHNT Richard Henderson
2021-04-16 21:02 ` [PATCH v5 41/81] target/arm: Implement SVE2 RSUBHNB, RSUBHNT Richard Henderson
2021-04-16 21:02 ` [PATCH v5 42/81] target/arm: Implement SVE2 HISTCNT, HISTSEG Richard Henderson
2021-04-16 21:02 ` [PATCH v5 43/81] target/arm: Implement SVE2 XAR Richard Henderson
2021-04-16 21:02 ` [PATCH v5 44/81] target/arm: Implement SVE2 scatter store insns Richard Henderson
2021-04-16 21:02 ` [PATCH v5 45/81] target/arm: Implement SVE2 gather load insns Richard Henderson
2021-04-16 21:02 ` [PATCH v5 46/81] target/arm: Implement SVE2 FMMLA Richard Henderson
2021-04-16 21:02 ` [PATCH v5 47/81] target/arm: Implement SVE2 SPLICE, EXT Richard Henderson
2021-04-16 21:02 ` [PATCH v5 48/81] target/arm: Pass separate addend to {U, S}DOT helpers Richard Henderson
2021-04-16 21:02 ` [PATCH v5 49/81] target/arm: Pass separate addend to FCMLA helpers Richard Henderson
2021-05-13 10:48   ` Peter Maydell
2021-04-16 21:02 ` [PATCH v5 50/81] target/arm: Split out formats for 2 vectors + 1 index Richard Henderson
2021-04-16 21:02 ` [PATCH v5 51/81] target/arm: Split out formats for 3 " Richard Henderson
2021-04-16 21:02 ` [PATCH v5 52/81] target/arm: Implement SVE2 integer multiply (indexed) Richard Henderson
2021-04-16 21:02 ` [PATCH v5 53/81] target/arm: Implement SVE2 integer multiply-add (indexed) Richard Henderson
2021-04-16 21:02 ` [PATCH v5 54/81] target/arm: Implement SVE2 saturating multiply-add high (indexed) Richard Henderson
2021-04-16 21:02 ` [PATCH v5 55/81] target/arm: Implement SVE2 saturating multiply-add (indexed) Richard Henderson
2021-04-16 21:02 ` [PATCH v5 56/81] target/arm: Implement SVE2 saturating multiply (indexed) Richard Henderson
2021-04-16 21:02 ` [PATCH v5 57/81] target/arm: Implement SVE2 signed saturating doubling multiply high Richard Henderson
2021-04-16 21:02 ` [PATCH v5 58/81] target/arm: Implement SVE2 saturating multiply high (indexed) Richard Henderson
2021-04-16 21:02 ` [PATCH v5 59/81] target/arm: Implement SVE mixed sign dot product (indexed) Richard Henderson
2021-04-16 21:02 ` [PATCH v5 60/81] target/arm: Implement SVE mixed sign dot product Richard Henderson
2021-04-16 21:02 ` [PATCH v5 61/81] target/arm: Implement SVE2 crypto unary operations Richard Henderson
2021-04-16 21:02 ` [PATCH v5 62/81] target/arm: Implement SVE2 crypto destructive binary operations Richard Henderson
2021-04-16 21:02 ` [PATCH v5 63/81] target/arm: Implement SVE2 crypto constructive " Richard Henderson
2021-04-16 21:02 ` [PATCH v5 64/81] target/arm: Implement SVE2 TBL, TBX Richard Henderson
2021-04-16 21:02 ` [PATCH v5 65/81] target/arm: Implement SVE2 FCVTNT Richard Henderson
2021-04-16 21:02 ` [PATCH v5 66/81] target/arm: Implement SVE2 FCVTLT Richard Henderson
2021-04-16 21:02 ` [PATCH v5 67/81] target/arm: Implement SVE2 FCVTXNT, FCVTX Richard Henderson
2021-04-16 21:02 ` [PATCH v5 68/81] target/arm: Implement SVE2 FLOGB Richard Henderson
2021-04-16 21:02 ` [PATCH v5 69/81] target/arm: Share table of sve load functions Richard Henderson
2021-04-16 21:02 ` [PATCH v5 70/81] target/arm: Implement SVE2 LD1RO Richard Henderson
2021-04-16 21:02 ` [PATCH v5 71/81] target/arm: Implement 128-bit ZIP, UZP, TRN Richard Henderson
2021-04-16 21:02 ` [PATCH v5 72/81] target/arm: Implement SVE2 bitwise shift immediate Richard Henderson
2021-04-16 21:02 ` [PATCH v5 73/81] target/arm: Implement SVE2 fp multiply-add long Richard Henderson
2021-04-16 21:02 ` [PATCH v5 74/81] target/arm: Implement aarch64 SUDOT, USDOT Richard Henderson
2021-04-16 21:02 ` [PATCH v5 75/81] target/arm: Split out do_neon_ddda_fpst Richard Henderson
2021-04-16 21:02 ` [PATCH v5 76/81] target/arm: Remove unused fpst from VDOT_scalar Richard Henderson
2021-04-16 21:02 ` [PATCH v5 77/81] target/arm: Fix decode for VDOT (indexed) Richard Henderson
2021-04-16 21:02 ` [PATCH v5 78/81] target/arm: Split decode of VSDOT and VUDOT Richard Henderson
2021-04-16 21:02 ` [PATCH v5 79/81] target/arm: Implement aarch32 VSUDOT, VUSDOT Richard Henderson
2021-04-16 21:18 ` [PATCH v5 80/81] target/arm: Implement integer matrix multiply accumulate Richard Henderson
2021-04-16 21:19 ` [PATCH v5 81/81] target/arm: Enable SVE2 and some extensions Richard Henderson
2021-04-16 22:46 ` [PATCH v5 for-6.1 00/81] target/arm: Implement SVE2 no-reply

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