From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 09/29] target/mips: Extract load/store helpers to ldst_helper.c
Date: Mon, 19 Apr 2021 00:50:38 +0200 [thread overview]
Message-ID: <20210418225058.1257014-10-f4bug@amsat.org> (raw)
In-Reply-To: <20210418225058.1257014-1-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/ldst_helper.c | 304 ++++++++++++++++++++++++++++++++++++++
target/mips/op_helper.c | 274 ----------------------------------
target/mips/meson.build | 1 +
3 files changed, 305 insertions(+), 274 deletions(-)
create mode 100644 target/mips/ldst_helper.c
diff --git a/target/mips/ldst_helper.c b/target/mips/ldst_helper.c
new file mode 100644
index 00000000000..3fbcc3509ab
--- /dev/null
+++ b/target/mips/ldst_helper.c
@@ -0,0 +1,304 @@
+/*
+ * MIPS emulation load/store helpers for QEMU.
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
+#include "exec/memop.h"
+#include "internal.h"
+
+#ifndef CONFIG_USER_ONLY
+
+static inline hwaddr do_translate_address(CPUMIPSState *env,
+ target_ulong address,
+ MMUAccessType access_type,
+ uintptr_t retaddr)
+{
+ hwaddr paddr;
+ CPUState *cs = env_cpu(env);
+
+ paddr = cpu_mips_translate_address(env, address, access_type);
+
+ if (paddr == -1LL) {
+ cpu_loop_exit_restore(cs, retaddr);
+ } else {
+ return paddr;
+ }
+}
+
+#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
+{ \
+ if (arg & almask) { \
+ if (!(env->hflags & MIPS_HFLAG_DM)) { \
+ env->CP0_BadVAddr = arg; \
+ } \
+ do_raise_exception(env, EXCP_AdEL, GETPC()); \
+ } \
+ env->CP0_LLAddr = do_translate_address(env, arg, MMU_DATA_LOAD, GETPC()); \
+ env->lladdr = arg; \
+ env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
+ return env->llval; \
+}
+HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
+#ifdef TARGET_MIPS64
+HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
+#endif
+#undef HELPER_LD_ATOMIC
+
+#endif /* !CONFIG_USER_ONLY */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+#define GET_LMASK(v) ((v) & 3)
+#define GET_OFFSET(addr, offset) (addr + (offset))
+#else
+#define GET_LMASK(v) (((v) & 3) ^ 3)
+#define GET_OFFSET(addr, offset) (addr - (offset))
+#endif
+
+void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+ int mem_idx)
+{
+ cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
+
+ if (GET_LMASK(arg2) <= 2) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK(arg2) <= 1) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK(arg2) == 0) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
+ mem_idx, GETPC());
+ }
+}
+
+void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+ int mem_idx)
+{
+ cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
+
+ if (GET_LMASK(arg2) >= 1) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK(arg2) >= 2) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK(arg2) == 3) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
+ mem_idx, GETPC());
+ }
+}
+
+#if defined(TARGET_MIPS64)
+/*
+ * "half" load and stores. We must do the memory access inline,
+ * or fault handling won't work.
+ */
+#ifdef TARGET_WORDS_BIGENDIAN
+#define GET_LMASK64(v) ((v) & 7)
+#else
+#define GET_LMASK64(v) (((v) & 7) ^ 7)
+#endif
+
+void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+ int mem_idx)
+{
+ cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
+
+ if (GET_LMASK64(arg2) <= 6) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) <= 5) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) <= 4) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) <= 3) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) <= 2) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) <= 1) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) <= 0) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1,
+ mem_idx, GETPC());
+ }
+}
+
+void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
+ int mem_idx)
+{
+ cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
+
+ if (GET_LMASK64(arg2) >= 1) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) >= 2) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) >= 3) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) >= 4) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) >= 5) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) >= 6) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48),
+ mem_idx, GETPC());
+ }
+
+ if (GET_LMASK64(arg2) == 7) {
+ cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56),
+ mem_idx, GETPC());
+ }
+}
+#endif /* TARGET_MIPS64 */
+
+static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
+
+void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
+ uint32_t mem_idx)
+{
+ target_ulong base_reglist = reglist & 0xf;
+ target_ulong do_r31 = reglist & 0x10;
+
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
+ target_ulong i;
+
+ for (i = 0; i < base_reglist; i++) {
+ env->active_tc.gpr[multiple_regs[i]] =
+ (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
+ addr += 4;
+ }
+ }
+
+ if (do_r31) {
+ env->active_tc.gpr[31] =
+ (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
+ }
+}
+
+void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
+ uint32_t mem_idx)
+{
+ target_ulong base_reglist = reglist & 0xf;
+ target_ulong do_r31 = reglist & 0x10;
+
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
+ target_ulong i;
+
+ for (i = 0; i < base_reglist; i++) {
+ cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
+ mem_idx, GETPC());
+ addr += 4;
+ }
+ }
+
+ if (do_r31) {
+ cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
+ }
+}
+
+#if defined(TARGET_MIPS64)
+void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
+ uint32_t mem_idx)
+{
+ target_ulong base_reglist = reglist & 0xf;
+ target_ulong do_r31 = reglist & 0x10;
+
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
+ target_ulong i;
+
+ for (i = 0; i < base_reglist; i++) {
+ env->active_tc.gpr[multiple_regs[i]] =
+ cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
+ addr += 8;
+ }
+ }
+
+ if (do_r31) {
+ env->active_tc.gpr[31] =
+ cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
+ }
+}
+
+void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
+ uint32_t mem_idx)
+{
+ target_ulong base_reglist = reglist & 0xf;
+ target_ulong do_r31 = reglist & 0x10;
+
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
+ target_ulong i;
+
+ for (i = 0; i < base_reglist; i++) {
+ cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
+ mem_idx, GETPC());
+ addr += 8;
+ }
+ }
+
+ if (do_r31) {
+ cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
+ }
+}
+
+#endif /* TARGET_MIPS64 */
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index f7da8c83aee..9b6f570c897 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -285,280 +285,6 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
return (int64_t)(int32_t)(uint32_t)tmp5;
}
-#ifndef CONFIG_USER_ONLY
-
-static inline hwaddr do_translate_address(CPUMIPSState *env,
- target_ulong address,
- MMUAccessType access_type,
- uintptr_t retaddr)
-{
- hwaddr paddr;
- CPUState *cs = env_cpu(env);
-
- paddr = cpu_mips_translate_address(env, address, access_type);
-
- if (paddr == -1LL) {
- cpu_loop_exit_restore(cs, retaddr);
- } else {
- return paddr;
- }
-}
-
-#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
-target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
-{ \
- if (arg & almask) { \
- if (!(env->hflags & MIPS_HFLAG_DM)) { \
- env->CP0_BadVAddr = arg; \
- } \
- do_raise_exception(env, EXCP_AdEL, GETPC()); \
- } \
- env->CP0_LLAddr = do_translate_address(env, arg, MMU_DATA_LOAD, GETPC()); \
- env->lladdr = arg; \
- env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
- return env->llval; \
-}
-HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
-#ifdef TARGET_MIPS64
-HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
-#endif
-#undef HELPER_LD_ATOMIC
-#endif
-
-#ifdef TARGET_WORDS_BIGENDIAN
-#define GET_LMASK(v) ((v) & 3)
-#define GET_OFFSET(addr, offset) (addr + (offset))
-#else
-#define GET_LMASK(v) (((v) & 3) ^ 3)
-#define GET_OFFSET(addr, offset) (addr - (offset))
-#endif
-
-void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
- int mem_idx)
-{
- cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
-
- if (GET_LMASK(arg2) <= 2) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK(arg2) <= 1) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK(arg2) == 0) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
- mem_idx, GETPC());
- }
-}
-
-void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
- int mem_idx)
-{
- cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
-
- if (GET_LMASK(arg2) >= 1) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK(arg2) >= 2) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK(arg2) == 3) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
- mem_idx, GETPC());
- }
-}
-
-#if defined(TARGET_MIPS64)
-/*
- * "half" load and stores. We must do the memory access inline,
- * or fault handling won't work.
- */
-#ifdef TARGET_WORDS_BIGENDIAN
-#define GET_LMASK64(v) ((v) & 7)
-#else
-#define GET_LMASK64(v) (((v) & 7) ^ 7)
-#endif
-
-void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
- int mem_idx)
-{
- cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
-
- if (GET_LMASK64(arg2) <= 6) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) <= 5) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) <= 4) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) <= 3) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) <= 2) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) <= 1) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) <= 0) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1,
- mem_idx, GETPC());
- }
-}
-
-void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
- int mem_idx)
-{
- cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
-
- if (GET_LMASK64(arg2) >= 1) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) >= 2) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) >= 3) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) >= 4) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) >= 5) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) >= 6) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48),
- mem_idx, GETPC());
- }
-
- if (GET_LMASK64(arg2) == 7) {
- cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56),
- mem_idx, GETPC());
- }
-}
-#endif /* TARGET_MIPS64 */
-
-static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
-
-void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
- uint32_t mem_idx)
-{
- target_ulong base_reglist = reglist & 0xf;
- target_ulong do_r31 = reglist & 0x10;
-
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
- target_ulong i;
-
- for (i = 0; i < base_reglist; i++) {
- env->active_tc.gpr[multiple_regs[i]] =
- (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
- addr += 4;
- }
- }
-
- if (do_r31) {
- env->active_tc.gpr[31] =
- (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
- }
-}
-
-void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
- uint32_t mem_idx)
-{
- target_ulong base_reglist = reglist & 0xf;
- target_ulong do_r31 = reglist & 0x10;
-
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
- target_ulong i;
-
- for (i = 0; i < base_reglist; i++) {
- cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
- mem_idx, GETPC());
- addr += 4;
- }
- }
-
- if (do_r31) {
- cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
- }
-}
-
-#if defined(TARGET_MIPS64)
-void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
- uint32_t mem_idx)
-{
- target_ulong base_reglist = reglist & 0xf;
- target_ulong do_r31 = reglist & 0x10;
-
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
- target_ulong i;
-
- for (i = 0; i < base_reglist; i++) {
- env->active_tc.gpr[multiple_regs[i]] =
- cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
- addr += 8;
- }
- }
-
- if (do_r31) {
- env->active_tc.gpr[31] =
- cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
- }
-}
-
-void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
- uint32_t mem_idx)
-{
- target_ulong base_reglist = reglist & 0xf;
- target_ulong do_r31 = reglist & 0x10;
-
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
- target_ulong i;
-
- for (i = 0; i < base_reglist; i++) {
- cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
- mem_idx, GETPC());
- addr += 8;
- }
- }
-
- if (do_r31) {
- cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
- }
-}
-#endif
-
void helper_fork(target_ulong arg1, target_ulong arg2)
{
diff --git a/target/mips/meson.build b/target/mips/meson.build
index daf5f1d55bc..15c2f835c68 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -18,6 +18,7 @@
mips_tcg_ss.add(files(
'dsp_helper.c',
'fpu_helper.c',
+ 'ldst_helper.c',
'lmmi_helper.c',
'msa_helper.c',
'msa_translate.c',
--
2.26.3
next prev parent reply other threads:[~2021-04-18 22:57 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-18 22:50 [PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 01/29] target/mips: Simplify meson TCG rules Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 02/29] target/mips: Move IEEE rounding mode array to new source file Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 03/29] target/mips: Move msa_reset() " Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 04/29] target/mips: Make CPU/FPU regnames[] arrays global Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 05/29] target/mips: Optimize CPU/FPU regnames[] arrays Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 06/29] target/mips: Restrict mips_cpu_dump_state() to cpu.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 07/29] target/mips: Turn printfpr() macro into a proper function Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 08/29] target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h" Philippe Mathieu-Daudé
2021-04-18 22:50 ` Philippe Mathieu-Daudé [this message]
2021-04-18 22:50 ` [PATCH v2 10/29] meson: Introduce meson_user_arch source set for arch-specific user-mode Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 11/29] target/mips: Introduce tcg-internal.h for TCG specific declarations Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 12/29] target/mips: Add simple user-mode mips_cpu_do_interrupt() Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 13/29] target/mips: Add simple user-mode mips_cpu_tlb_fill() Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 14/29] target/mips: Move cpu_signal_handler definition around Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 15/29] target/mips: Move sysemu specific files under sysemu/ subfolder Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 16/29] target/mips: Move physical addressing code to sysemu/physaddr.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 17/29] target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 18/29] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 19/29] target/mips: Restrict mmu_init() to TCG Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 20/29] target/mips: Move tlb_helper.c to tcg/sysemu/ Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 21/29] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 22/29] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 23/29] target/mips: Move helper_cache() " Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 24/29] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 25/29] target/mips: Move exception management code to exception.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 26/29] target/mips: Move CP0 helpers to sysemu/cp0.c Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 27/29] target/mips: Move TCG source files under tcg/ sub directory Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 28/29] hw/mips: Restrict non-virtualized machines to TCG Philippe Mathieu-Daudé
2021-04-18 22:50 ` [PATCH v2 29/29] gitlab-ci: Add KVM mips64el cross-build jobs Philippe Mathieu-Daudé
2021-04-19 10:25 ` Thomas Huth
2021-04-18 23:03 ` [PATCH v2 00/29] target/mips: Re-org to allow KVM-only builds no-reply
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