From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v3 14/30] target/mips: Add simple user-mode mips_cpu_tlb_fill()
Date: Mon, 19 Apr 2021 21:18:07 +0200 [thread overview]
Message-ID: <20210419191823.1555482-15-f4bug@amsat.org> (raw)
In-Reply-To: <20210419191823.1555482-1-f4bug@amsat.org>
tlb_helper.c's #ifdef'ry hides a quite simple user-mode
implementation of mips_cpu_tlb_fill().
Copy the user-mode implementation (without #ifdef'ry) to
tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry.
This will allow us to restrict tlb_helper.c to sysemu.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/user/tlb_helper.c | 36 +++++++++++++++++++++++++++++++
target/mips/tlb_helper.c | 10 ---------
2 files changed, 36 insertions(+), 10 deletions(-)
diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c
index 453b9e9b930..b835144b820 100644
--- a/target/mips/tcg/user/tlb_helper.c
+++ b/target/mips/tcg/user/tlb_helper.c
@@ -22,6 +22,42 @@
#include "exec/exec-all.h"
#include "internal.h"
+static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
+ MMUAccessType access_type)
+{
+ CPUState *cs = env_cpu(env);
+
+ env->error_code = 0;
+ if (access_type == MMU_INST_FETCH) {
+ env->error_code |= EXCP_INST_NOTAVAIL;
+ }
+
+ /* Reference to kernel address from user mode or supervisor mode */
+ /* Reference to supervisor address from user mode */
+ if (access_type == MMU_DATA_STORE) {
+ cs->exception_index = EXCP_AdES;
+ } else {
+ cs->exception_index = EXCP_AdEL;
+ }
+
+ /* Raise exception */
+ if (!(env->hflags & MIPS_HFLAG_DM)) {
+ env->CP0_BadVAddr = address;
+ }
+}
+
+bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ /* data access */
+ raise_mmu_exception(env, address, access_type);
+ do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
+}
+
void mips_cpu_do_interrupt(CPUState *cs)
{
cs->exception_index = EXCP_NONE;
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 78720c4d20a..afc019c80dd 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -403,8 +403,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}
-#endif /* !CONFIG_USER_ONLY */
-
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
MMUAccessType access_type, int tlb_error)
{
@@ -484,8 +482,6 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
env->error_code = error_code;
}
-#if !defined(CONFIG_USER_ONLY)
-
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -833,7 +829,6 @@ refill:
return true;
}
#endif
-#endif /* !CONFIG_USER_ONLY */
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
@@ -841,14 +836,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
{
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;
-#if !defined(CONFIG_USER_ONLY)
hwaddr physical;
int prot;
-#endif
int ret = TLBRET_BADADDR;
/* data access */
-#if !defined(CONFIG_USER_ONLY)
/* XXX: put correct access by using cpu_restore_state() correctly */
ret = get_physical_address(env, &physical, &prot, address,
access_type, mmu_idx);
@@ -896,13 +888,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
if (probe) {
return false;
}
-#endif
raise_mmu_exception(env, address, access_type, ret);
do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
}
-#ifndef CONFIG_USER_ONLY
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
MMUAccessType access_type, uintptr_t retaddr)
{
--
2.26.3
next prev parent reply other threads:[~2021-04-19 19:39 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-19 19:17 [PATCH v3 00/30] target/mips: Re-org to allow KVM-only builds Philippe Mathieu-Daudé
2021-04-19 19:17 ` [PATCH v3 01/30] target/mips: Simplify meson TCG rules Philippe Mathieu-Daudé
2021-04-19 19:17 ` [PATCH v3 02/30] target/mips: Move IEEE rounding mode array to new source file Philippe Mathieu-Daudé
2021-04-19 19:17 ` [PATCH v3 03/30] target/mips: Move msa_reset() " Philippe Mathieu-Daudé
2021-04-19 19:17 ` [PATCH v3 04/30] target/mips: Make CPU/FPU regnames[] arrays global Philippe Mathieu-Daudé
2021-04-19 19:17 ` [PATCH v3 05/30] target/mips: Optimize CPU/FPU regnames[] arrays Philippe Mathieu-Daudé
2021-04-19 19:22 ` Richard Henderson
2021-04-19 19:17 ` [PATCH v3 06/30] target/mips: Restrict mips_cpu_dump_state() to cpu.c Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 07/30] target/mips: Turn printfpr() macro into a proper function Philippe Mathieu-Daudé
2021-04-19 19:24 ` Richard Henderson
2021-04-19 19:18 ` [PATCH v3 08/30] target/mips: Declare mips_cpu_set_error_pc() inlined in "internal.h" Philippe Mathieu-Daudé
2021-04-19 19:27 ` Richard Henderson
2021-04-19 20:42 ` Philippe Mathieu-Daudé
2021-04-20 14:03 ` Richard Henderson
2021-04-19 19:18 ` [PATCH v3 09/30] target/mips: Merge do_translate_address into cpu_mips_translate_address Philippe Mathieu-Daudé
2021-04-19 19:31 ` Richard Henderson
2021-04-19 19:18 ` [PATCH v3 10/30] target/mips: Extract load/store helpers to ldst_helper.c Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 11/30] meson: Introduce meson_user_arch source set for arch-specific user-mode Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 12/30] target/mips: Introduce tcg-internal.h for TCG specific declarations Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 13/30] target/mips: Add simple user-mode mips_cpu_do_interrupt() Philippe Mathieu-Daudé
2021-04-19 19:18 ` Philippe Mathieu-Daudé [this message]
2021-04-19 19:18 ` [PATCH v3 15/30] target/mips: Move cpu_signal_handler definition around Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 16/30] target/mips: Move sysemu specific files under sysemu/ subfolder Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 17/30] target/mips: Move physical addressing code to sysemu/physaddr.c Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 18/30] target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG Philippe Mathieu-Daudé
2021-04-19 19:33 ` Richard Henderson
2021-04-19 19:18 ` [PATCH v3 19/30] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder Philippe Mathieu-Daudé
2021-04-19 19:34 ` Richard Henderson
2021-04-19 19:18 ` [PATCH v3 20/30] target/mips: Restrict mmu_init() to TCG Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 21/30] target/mips: Move tlb_helper.c to tcg/sysemu/ Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 22/30] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 23/30] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 24/30] target/mips: Move helper_cache() " Philippe Mathieu-Daudé
2021-04-19 20:14 ` Richard Henderson
2021-04-19 19:18 ` [PATCH v3 25/30] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 26/30] target/mips: Move exception management code to exception.c Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 27/30] target/mips: Move CP0 helpers to sysemu/cp0.c Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 28/30] target/mips: Move TCG source files under tcg/ sub directory Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 29/30] hw/mips: Restrict non-virtualized machines to TCG Philippe Mathieu-Daudé
2021-04-19 19:18 ` [PATCH v3 30/30] gitlab-ci: Add KVM mips64el cross-build jobs Philippe Mathieu-Daudé
2021-04-19 19:33 ` [PATCH v3 00/30] target/mips: Re-org to allow KVM-only builds no-reply
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