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From: Emmanuel Blot <emmanuel.blot@sifive.com>
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Emmanuel Blot <emmanuel.blot@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH] target/riscv: fix a typo with interrupt names
Date: Wed, 21 Apr 2021 15:32:36 +0200	[thread overview]
Message-ID: <20210421133236.11323-1-emmanuel.blot@sifive.com> (raw)

Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b6..c79503ce967 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = {
     "vs_timer",
     "m_timer",
     "u_external",
+    "s_external",
     "vs_external",
-    "h_external",
     "m_external",
     "reserved",
     "reserved",
-- 
2.31.1



             reply	other threads:[~2021-04-21 13:34 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-21 13:32 Emmanuel Blot [this message]
2021-04-22  0:24 ` [PATCH] target/riscv: fix a typo with interrupt names Alistair Francis

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