From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com,
kupokupokupopo@gmail.com, palmer@dabbelt.com
Subject: [PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation
Date: Wed, 28 Apr 2021 07:18:42 +0300 [thread overview]
Message-ID: <20210428041848.12982-1-space.monkey.delivers@gmail.com> (raw)
v8-resend:
Resending to trigger recheck due to minor codestyle issues.
v8:
Hi folks,
Finally we were able to assign v0.1 draft for Pointer Masking extension for RISC-V: https://github.com/riscv/riscv-j-extension/blob/master/pointer-masking-proposal.adoc
This is supposed to be the first series of patches with initial support for PM. It obviously misses support for hypervisor mode, vector load/stores and some other features, while using temporary csr numbers(they're to be assigned by the committee a bit later).
With this patch series we were able to run a bunch of tests with HWASAN checks enabled.
I hope I've managed to addressed @Alistair's previous comments in this version.
Thanks!
v7:
Hi folks,
Sorry it took me almost 3 month to provide the reply and fixes: it was a really busy EOY.
This series contains fixed @Alistair suggestion on enabling J-ext.
As for @Richard comments:
- Indeed I've missed appending review-by to the approved commits. Now I've restored them except for the fourth commit. @Richard could you please tell if you think it's still ok to commit it as is, or should I support masking mem ops for RVV first?
- These patches don't have any support for load/store masking for RVV and RVH extensions, so no support for special load/store for Hypervisor in particular.
If this patch series would be accepted, I think my further attention would be to:
- Support pm for memory operations for RVV
- Add proper csr and support pm for memory operations for Hypervisor mode
- Support address wrapping on unaligned accesses as @Richard mentioned previously
Thanks!
Alexey Baturo (5):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
the h-mode
[RISCV_PM] Print new PM CSRs in QEMU logs
[RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
instructions
[RISCV_PM] Allow experimental J-ext to be turned on
Anatoly Parshintsev (1):
[RISCV_PM] Implement address masking functions required for RISC-V
Pointer Masking extension
target/riscv/cpu.c | 32 ++++
target/riscv/cpu.h | 34 ++++
target/riscv/cpu_bits.h | 66 +++++++
target/riscv/csr.c | 236 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 3 +
target/riscv/insn_trans/trans_rvd.c.inc | 2 +
target/riscv/insn_trans/trans_rvf.c.inc | 2 +
target/riscv/insn_trans/trans_rvi.c.inc | 2 +
target/riscv/translate.c | 42 +++++
9 files changed, 419 insertions(+)
--
2.20.1
next reply other threads:[~2021-04-28 4:20 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-28 4:18 Alexey Baturo [this message]
2021-04-28 4:18 ` [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2021-04-28 4:18 ` [PATCH RESEND v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-05-12 5:54 ` Alistair Francis
2021-04-28 4:18 ` [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2021-04-28 4:18 ` [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-04-28 4:18 ` [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2021-05-12 5:59 ` Alistair Francis
2021-04-28 4:18 ` [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
-- strict thread matches above, loose matches on Subject: below --
2021-04-28 4:07 [PATCH RESEND v8 0/6] RISC-V Pointer Masking implementation Alexey Baturo
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