From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH v2 7/8] hw/riscv: Use macros for BIOS image names
Date: Fri, 30 Apr 2021 15:13:01 +0800 [thread overview]
Message-ID: <20210430071302.1489082-7-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
The OpenSBI BIOS image names are used by many RISC-V machines.
Let's define macros for them.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/riscv/boot.h | 5 +++++
hw/riscv/sifive_u.c | 6 ++----
hw/riscv/spike.c | 6 ++----
hw/riscv/virt.c | 6 ++----
4 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 11a21dd584..0e89400b09 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -24,6 +24,11 @@
#include "hw/loader.h"
#include "hw/riscv/riscv_hart.h"
+#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
+#define RISCV32_BIOS_ELF "opensbi-riscv32-generic-fw_dynamic.elf"
+#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
+#define RISCV64_BIOS_ELF "opensbi-riscv64-generic-fw_dynamic.elf"
+
bool riscv_is_32bit(RISCVHartArrayState *harts);
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b55e56890c..f30cc8004b 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -561,12 +561,10 @@ static void sifive_u_machine_init(MachineState *machine)
if (riscv_is_32bit(&s->soc.u_cpus)) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv32-generic-fw_dynamic.bin",
- start_addr, NULL);
+ RISCV32_BIOS_BIN, start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv64-generic-fw_dynamic.bin",
- start_addr, NULL);
+ RISCV64_BIOS_BIN, start_addr, NULL);
}
if (machine->kernel_filename) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index f094bb2158..98932fba62 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -259,13 +259,11 @@ static void spike_board_init(MachineState *machine)
*/
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv32-generic-fw_dynamic.elf",
- memmap[SPIKE_DRAM].base,
+ RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv64-generic-fw_dynamic.elf",
- memmap[SPIKE_DRAM].base,
+ RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 8a8ff04dab..b03c5f8b5b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -682,12 +682,10 @@ static void virt_machine_init(MachineState *machine)
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv32-generic-fw_dynamic.bin",
- start_addr, NULL);
+ RISCV32_BIOS_BIN, start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv64-generic-fw_dynamic.bin",
- start_addr, NULL);
+ RISCV64_BIOS_BIN, start_addr, NULL);
}
if (machine->kernel_filename) {
--
2.25.1
next prev parent reply other threads:[~2021-04-30 7:14 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 7:12 [PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Bin Meng
2021-04-30 7:12 ` [PATCH v2 2/8] hw/riscv: virt: " Bin Meng
2021-04-30 7:12 ` [PATCH v2 3/8] hw/riscv: Support the official CLINT DT bindings Bin Meng
2021-04-30 7:12 ` [PATCH v2 4/8] hw/riscv: Support the official PLIC " Bin Meng
2021-04-30 7:12 ` [PATCH v2 5/8] docs/system/riscv: Correct the indentation level of supported devices Bin Meng
2021-05-03 3:00 ` Alistair Francis
2021-04-30 7:13 ` [PATCH v2 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage Bin Meng
2021-04-30 7:13 ` Bin Meng [this message]
2021-04-30 7:13 ` [PATCH v2 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot Bin Meng
2021-05-31 2:33 ` [PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Bin Meng
2021-06-01 6:41 ` Alistair Francis
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