From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
To: qemu-devel@nongnu.org
Cc: farosas@linux.ibm.com, richard.henderson@linaro.org,
luis.pires@eldorado.org.br, lucas.araujo@eldorado.org.br,
fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org,
"Bruno Larsen \(billionai\)" <bruno.larsen@eldorado.org.br>,
matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au
Subject: [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration
Date: Fri, 30 Apr 2021 16:35:31 -0300 [thread overview]
Message-ID: <20210430193533.82136-6-bruno.larsen@eldorado.org.br> (raw)
In-Reply-To: <20210430193533.82136-1-bruno.larsen@eldorado.org.br>
Since vscr is not an spr, its initialization was removed from the
spr registration functions, and moved to the relevant init_procs.
We may look into adding vscr to the reset path instead of the init
path (as suggested by David Gibson), but this looked like a good
enough solution for now.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
---
target/ppc/translate_init.c.inc | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 67529e8648..b922b04f25 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -941,8 +941,6 @@ static void gen_spr_74xx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Not strictly an SPR */
- vscr_init(env, 0x00010000);
}
static void gen_l3_ctrl(CPUPPCState *env)
@@ -5790,6 +5788,7 @@ static void init_proc_7400(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
@@ -5869,6 +5868,7 @@ static void init_proc_7410(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
@@ -5954,6 +5954,7 @@ static void init_proc_7440(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
@@ -6062,6 +6063,7 @@ static void init_proc_7450(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* Level 3 cache control */
gen_l3_ctrl(env);
/* L3ITCR1 */
@@ -6196,6 +6198,7 @@ static void init_proc_7445(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* LDSTCR */
/* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
@@ -6333,6 +6336,7 @@ static void init_proc_7455(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* Level 3 cache control */
gen_l3_ctrl(env);
/* LDSTCR */
@@ -6472,6 +6476,7 @@ static void init_proc_7457(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* Level 3 cache control */
gen_l3_ctrl(env);
/* L3ITCR1 */
@@ -6635,6 +6640,7 @@ static void init_proc_e600(CPUPPCState *env)
gen_tbl(env);
/* 74xx specific SPR */
gen_spr_74xx(env);
+ vscr_init(env, 0x00010000);
/* XXX : not implemented */
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
@@ -6833,11 +6839,6 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_VRSAVE, 0x00000000);
- /*
- * Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors.
- */
- vscr_init(env, 0x00010000);
}
static void gen_spr_book3s_dbg(CPUPPCState *env)
@@ -7457,6 +7458,11 @@ static void init_proc_book3s_common(CPUPPCState *env)
gen_spr_book3s_pmu_sup(env);
gen_spr_book3s_pmu_user(env);
gen_spr_book3s_ctrl(env);
+ /*
+ * Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors.
+ */
+ vscr_init(env, 0x00010000);
}
static void init_proc_970(CPUPPCState *env)
--
2.17.1
next prev parent reply other threads:[~2021-04-30 19:52 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 19:35 [PATCH v3 0/7] target/ppc: untangle CPU init from translation Bruno Larsen (billionai)
2021-04-30 19:35 ` [PATCH v3 1/7] target/ppc: Created !TCG SPR registration macro Bruno Larsen (billionai)
2021-05-01 0:27 ` Richard Henderson
2021-05-03 4:37 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 2/7] target/ppc: Isolated SPR read/write callbacks Bruno Larsen (billionai)
2021-05-01 0:55 ` Richard Henderson
2021-05-03 20:07 ` Bruno Piazera Larsen
2021-05-03 4:54 ` David Gibson
2021-05-03 20:15 ` Bruno Piazera Larsen
2021-05-04 0:28 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 3/7] target/ppc: remove unnecessary SPR functions Bruno Larsen (billionai)
2021-05-01 0:58 ` Richard Henderson
2021-05-03 4:39 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 4/7] target/ppc: turned SPR R/W callbacks not static Bruno Larsen (billionai)
2021-05-01 1:05 ` Richard Henderson
2021-05-03 11:28 ` Bruno Piazera Larsen
2021-05-03 15:25 ` Richard Henderson
2021-05-03 20:08 ` Bruno Piazera Larsen
2021-04-30 19:35 ` Bruno Larsen (billionai) [this message]
2021-05-01 1:06 ` [PATCH v3 5/7] target/ppc: removed VSCR from SPR registration Richard Henderson
2021-05-03 4:47 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 6/7] target/ppc: renamed SPR registration functions Bruno Larsen (billionai)
2021-05-03 4:49 ` David Gibson
2021-04-30 19:35 ` [PATCH v3 7/7] target/ppc: isolated cpu init from translation logic Bruno Larsen (billionai)
2021-05-01 1:11 ` Richard Henderson
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