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Tue, 04 May 2021 03:02:47 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id p10sm15055132wrr.58.2021.05.04.03.02.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 May 2021 03:02:39 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0C4A81FF9D; Tue, 4 May 2021 11:02:25 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v2 14/30] tests/tcg/tricore: Add build infrastructure Date: Tue, 4 May 2021 11:02:07 +0100 Message-Id: <20210504100223.25427-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210504100223.25427-1-alex.bennee@linaro.org> References: <20210504100223.25427-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, berrange@redhat.com, Bastian Koppelmann , f4bug@amsat.org, stefanha@redhat.com, crosa@redhat.com, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , aurelien@aurel32.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bastian Koppelmann this includes the Makefile and linker script to build all the tests. Reviewed-by: Alex Bennée Signed-off-by: Bastian Koppelmann Signed-off-by: Alex Bennée Message-Id: <20210305170045.869437-5-kbastian@mail.uni-paderborn.de> --- MAINTAINERS | 1 + tests/tcg/tricore/Makefile.softmmu-target | 15 ++++++ tests/tcg/tricore/link.ld | 60 +++++++++++++++++++++++ 3 files changed, 76 insertions(+) create mode 100644 tests/tcg/tricore/Makefile.softmmu-target create mode 100644 tests/tcg/tricore/link.ld diff --git a/MAINTAINERS b/MAINTAINERS index fc0b429b45..4d3727cad5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -378,6 +378,7 @@ S: Maintained F: target/tricore/ F: hw/tricore/ F: include/hw/tricore/ +F: tests/tcg/tricore/ Multiarch Linux User Tests M: Alex Bennée diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target new file mode 100644 index 0000000000..d64a99b95f --- /dev/null +++ b/tests/tcg/tricore/Makefile.softmmu-target @@ -0,0 +1,15 @@ +TESTS_PATH = $(SRC_PATH)/tests/tcg/tricore + +LDFLAGS = -T$(TESTS_PATH)/link.ld +ASFLAGS = + +QEMU_OPTS += -M tricore_testboard -nographic -kernel + +%.pS: $(TESTS_PATH)/%.S + $(HOST_CC) -E -o $@ $< + +%.o: %.pS + $(AS) $(ASFLAGS) -o $@ $< + +%.tst: %.o + $(LD) $(LDFLAGS) $< -o $@ diff --git a/tests/tcg/tricore/link.ld b/tests/tcg/tricore/link.ld new file mode 100644 index 0000000000..364bcdc00a --- /dev/null +++ b/tests/tcg/tricore/link.ld @@ -0,0 +1,60 @@ +/* Default linker script, for normal executables */ +OUTPUT_FORMAT("elf32-tricore") +OUTPUT_ARCH(tricore) +ENTRY(_start) + +/* the internal ram description */ +MEMORY +{ + text_ram (rx!p): org = 0x80000000, len = 15K + data_ram (w!xp): org = 0xd0000000, len = 130K +} +/* + * Define the sizes of the user and system stacks. + */ +__USTACK_SIZE = DEFINED (__USTACK_SIZE) ? __USTACK_SIZE : 1K ; +/* + * Define the start address and the size of the context save area. + */ +__CSA_BEGIN = 0xd0000000 ; +__CSA_SIZE = 8k ; +__CSA_END = __CSA_BEGIN + __CSA_SIZE ; + +SECTIONS +{ + .text : + { + *(.text) + . = ALIGN(8); + } > text_ram + + .rodata : + { + *(.rodata) + *(.rodata1) + } > data_ram + + .data : + { + . = ALIGN(8) ; + *(.data) + *(.data.*) + . = ALIGN(8) ; + __USTACK = . + __USTACK_SIZE -768; + + } > data_ram + /* + * Allocate space for BSS sections. + */ + .bss : + { + BSS_BASE = . ; + *(.bss) + *(COMMON) + . = ALIGN(8) ; + } > data_ram + /* Make sure CSA, stack and heap addresses are properly aligned. */ + _. = ASSERT ((__CSA_BEGIN & 0x3f) == 0 , "illegal CSA start address") ; + _. = ASSERT ((__CSA_SIZE & 0x3f) == 0 , "illegal CSA size") ; + +} -- 2.20.1