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[122.116.72.36]) by smtp.gmail.com with ESMTPSA id js6sm35877977pjb.0.2021.05.05.09.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 09:07:18 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v6 14/17] target/riscv: rvb: address calculation Date: Thu, 6 May 2021 00:06:15 +0800 Message-Id: <20210505160620.15723-15-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210505160620.15723-1-frank.chang@sifive.com> References: <20210505160620.15723-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++++ target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++++++ target/riscv/translate.c | 32 +++++++++++++++++++++++++ 3 files changed, 62 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e6dab8dbbc1..287920ee9bf 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -686,6 +686,9 @@ ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r +sh1add 0010000 .......... 010 ..... 0110011 @r +sh2add 0010000 .......... 100 ..... 0110011 @r +sh3add 0010000 .......... 110 ..... 0110011 @r bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh @@ -714,6 +717,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r +sh1add_uw 0010000 .......... 010 ..... 0111011 @r +sh2add_uw 0010000 .......... 100 ..... 0111011 @r +sh3add_uw 0010000 .......... 110 ..... 0111011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index ec9f9d2ef24..b27114a068d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -226,6 +226,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a) return gen_shifti(ctx, a, gen_helper_gorc); } +#define GEN_TRANS_SHADD(SHAMT) \ +static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \ +{ \ + REQUIRE_EXT(ctx, RVB); \ + return gen_arith(ctx, a, gen_sh##SHAMT##add); \ +} + +GEN_TRANS_SHADD(1) +GEN_TRANS_SHADD(2) +GEN_TRANS_SHADD(3) + static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -386,3 +397,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a) REQUIRE_EXT(ctx, RVB); return gen_shiftiw(ctx, a, gen_gorcw); } + +#define GEN_TRANS_SHADD_UW(SHAMT) \ +static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \ + arg_sh##SHAMT##add_uw *a) \ +{ \ + REQUIRE_64BIT(ctx); \ + REQUIRE_EXT(ctx, RVB); \ + return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \ +} + +GEN_TRANS_SHADD_UW(1) +GEN_TRANS_SHADD_UW(2) +GEN_TRANS_SHADD_UW(3) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 35d4d36eef8..ae9b5f7a2e2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -649,6 +649,21 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a) return true; } +#define GEN_SHADD(SHAMT) \ +static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t = tcg_temp_new(); \ + \ + tcg_gen_shli_tl(t, arg1, SHAMT); \ + tcg_gen_add_tl(ret, t, arg2); \ + \ + tcg_temp_free(t); \ +} + +GEN_SHADD(1) +GEN_SHADD(2) +GEN_SHADD(3) + static void gen_ctzw(TCGv ret, TCGv arg1) { tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); @@ -733,6 +748,23 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2) gen_helper_gorcw(ret, arg1, arg2); } +#define GEN_SHADD_UW(SHAMT) \ +static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t = tcg_temp_new(); \ + \ + tcg_gen_ext32u_tl(t, arg1); \ + \ + tcg_gen_shli_tl(t, t, SHAMT); \ + tcg_gen_add_tl(ret, t, arg2); \ + \ + tcg_temp_free(t); \ +} + +GEN_SHADD_UW(1) +GEN_SHADD_UW(2) +GEN_SHADD_UW(3) + static bool gen_arith(DisasContext *ctx, arg_r *a, void(*func)(TCGv, TCGv, TCGv)) { -- 2.17.1