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11 May 2021 03:01:49 -0700 IronPort-SDR: Z9KgeFdRYIColcrMZjxWZh+fdwvT5jtFAkxyZwI/2GxU4QURm3MrC/0EfT7wrLuPHILip5QiZS /LHTYq0U3ghAx7dY30OkN7BrwbSSyymp/EP20FBZcCU2Vfn4NArZLi+fdNx50YwbMObYJT/Q1k NddW6Yr9tJwtMJ9Hu6WDWOj6X1ELcDuN/bxHG3yC1Az4rLSDnpqUdVp3CLgVZKyKqE7py1n5qE xZHHXejWJGtkHLy4lIERAqQZeMCkMvmCxeNCrm4zrPByWcqQu4kxoA96PsskSd92nzXX+/B8YA sh0= WDCIronportException: Internal Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.48]) by uls-op-cesaip01.wdc.com with ESMTP; 11 May 2021 03:21:48 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro Date: Tue, 11 May 2021 20:19:42 +1000 Message-Id: <20210511101951.165287-34-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210511101951.165287-1-alistair.francis@wdc.com> References: <20210511101951.165287-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=7584e029c=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com --- target/riscv/cpu.h | 6 ------ target/riscv/cpu.c | 6 +++++- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index add734bbbd..7e879fb9ca 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -54,12 +54,6 @@ #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) -#if defined(TARGET_RISCV32) -#define RVXLEN RV32 -#elif defined(TARGET_RISCV64) -#define RVXLEN RV64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 04ac03f8c9..3191fd0082 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, target_ulong resetvec) static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#if defined(TARGET_RISCV32) + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#elif defined(TARGET_RISCV64) + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); +#endif set_priv_version(env, PRIV_VERSION_1_11_0); } -- 2.31.1