From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: richard.henderson@linaro.org, f4bug@amsat.org,
luis.pires@eldorado.org.br, lagarcia@br.ibm.com,
bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br,
david@gibson.dropbear.id.au
Subject: [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions
Date: Wed, 12 May 2021 15:54:35 -0300 [thread overview]
Message-ID: <20210512185441.3619828-26-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20210512185441.3619828-1-matheus.ferst@eldorado.org.br>
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- prefixed and non-prefixed loads unfolded.
---
target/ppc/insn64.decode | 15 +++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 16 ++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 56857b5e93..0c8264a194 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -24,6 +24,21 @@
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
+### Fixed-Point Load Instructions
+
+PLBZ 000001 10 0--.-- .................. \
+ 100010 ..... ..... ................ @PLS_D
+PLHZ 000001 10 0--.-- .................. \
+ 101000 ..... ..... ................ @PLS_D
+PLHA 000001 10 0--.-- .................. \
+ 101010 ..... ..... ................ @PLS_D
+PLWZ 000001 10 0--.-- .................. \
+ 100000 ..... ..... ................ @PLS_D
+PLWA 000001 00 0--.-- .................. \
+ 101001 ..... ..... ................ @PLS_D
+PLD 000001 00 0--.-- .................. \
+ 111001 ..... ..... ................ @PLS_D
+
### Fixed-Point Arithmetic Instructions
PADDI 000001 10 0--.-- .................. \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 4c3eff6979..67291e0b75 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -80,6 +80,16 @@ static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
}
+static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
+ bool store, MemOp mop)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return do_ldst_D(ctx, &d, update, store, mop);
+}
+
static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
bool store, MemOp mop)
{
@@ -91,35 +101,41 @@ TRANS(LBZ, do_ldst_D, false, false, MO_UB)
TRANS(LBZX, do_ldst_X, false, false, MO_UB)
TRANS(LBZU, do_ldst_D, true, false, MO_UB)
TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
+TRANS(PLBZ, do_ldst_PLS_D, false, false, MO_UB)
/* Load Halfword and Zero */
TRANS(LHZ, do_ldst_D, false, false, MO_UW)
TRANS(LHZX, do_ldst_X, false, false, MO_UW)
TRANS(LHZU, do_ldst_D, true, false, MO_UW)
TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
+TRANS(PLHZ, do_ldst_PLS_D, false, false, MO_UW)
/* Load Halfword Algebraic */
TRANS(LHA, do_ldst_D, false, false, MO_SW)
TRANS(LHAX, do_ldst_X, false, false, MO_SW)
TRANS(LHAU, do_ldst_D, true, false, MO_SW)
TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
+TRANS(PLHA, do_ldst_PLS_D, false, false, MO_SW)
/* Load Word and Zero */
TRANS(LWZ, do_ldst_D, false, false, MO_UL)
TRANS(LWZX, do_ldst_X, false, false, MO_UL)
TRANS(LWZU, do_ldst_D, true, false, MO_UL)
TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
+TRANS(PLWZ, do_ldst_PLS_D, false, false, MO_UL)
/* Load Word Algebraic */
TRANS64(LWA, do_ldst_D, false, false, MO_SL)
TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
+TRANS64(PLWA, do_ldst_PLS_D, false, false, MO_SL)
/* Load Doubleword */
TRANS64(LD, do_ldst_D, false, false, MO_Q)
TRANS64(LDX, do_ldst_X, false, false, MO_Q)
TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
+TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
/*
* Fixed-Point Arithmetic Instructions
--
2.25.1
next prev parent reply other threads:[~2021-05-12 19:29 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 01/31] target/ppc: Add cia field to DisasContext matheus.ferst
2021-05-13 4:03 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 02/31] target/ppc: Split out decode_legacy matheus.ferst
2021-05-13 4:03 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception* matheus.ferst
2021-05-13 4:06 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL matheus.ferst
2021-05-13 4:06 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP matheus.ferst
2021-05-13 4:07 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception matheus.ferst
2021-05-13 4:08 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 07/31] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} matheus.ferst
2021-05-13 4:10 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT matheus.ferst
2021-05-12 19:31 ` Bruno Piazera Larsen
2021-05-13 4:11 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 09/31] target/ppc: Remove unnecessary gen_io_end calls matheus.ferst
2021-05-13 4:12 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-12 19:21 ` Matheus K. Ferst
2021-05-13 4:14 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 11/31] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
2021-05-12 18:54 ` [PATCH v4 12/31] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
2021-05-12 18:54 ` [PATCH v4 13/31] target/ppc: Remove DisasContext.exception matheus.ferst
2021-05-12 18:54 ` [PATCH v4 14/31] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
2021-05-12 18:54 ` [PATCH v4 15/31] target/ppc: Tidy exception vs exit_tb matheus.ferst
2021-05-12 18:54 ` [PATCH v4 16/31] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
2021-05-12 18:54 ` [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check matheus.ferst
2021-05-12 19:45 ` Bruno Piazera Larsen
2021-05-12 18:54 ` [PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 19/31] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-05-12 18:54 ` [PATCH v4 20/31] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-05-12 18:54 ` [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-05-12 18:54 ` [PATCH v4 22/31] target/ppc: Implement PNOP matheus.ferst
2021-05-13 10:37 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 23/31] TCG: add tcg_constant_tl matheus.ferst
2021-05-13 10:42 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 24/31] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-05-12 18:54 ` matheus.ferst [this message]
2021-05-13 10:50 ` [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions Richard Henderson
2021-05-12 18:54 ` [PATCH v4 26/31] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-05-12 18:54 ` [PATCH v4 27/31] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-13 11:01 ` Richard Henderson
2021-05-13 11:43 ` Matheus K. Ferst
2021-05-12 18:54 ` [PATCH v4 29/31] target/ppc: Implement cfuged instruction matheus.ferst
2021-05-13 11:31 ` Richard Henderson
2021-05-13 12:24 ` Matheus K. Ferst
2021-05-14 0:01 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 30/31] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-13 11:36 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 31/31] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-13 11:40 ` Richard Henderson
2021-05-13 4:22 ` [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions David Gibson
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