* [PATCH v4 01/31] target/ppc: Add cia field to DisasContext
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 4:03 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 02/31] target/ppc: Split out decode_legacy matheus.ferst
` (30 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 36 +++++++++++++++++++-----------------
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 98850f0c30..9abe03222d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -154,6 +154,7 @@ void ppc_translate_init(void)
/* internal defines */
struct DisasContext {
DisasContextBase base;
+ target_ulong cia; /* current instruction address */
uint32_t opcode;
uint32_t exception;
/* Routine used to access memory */
@@ -253,7 +254,7 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
* faulting instruction
*/
if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_update_nip(ctx, ctx->base.pc_next - 4);
+ gen_update_nip(ctx, ctx->cia);
}
t0 = tcg_const_i32(excp);
t1 = tcg_const_i32(error);
@@ -272,7 +273,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
* faulting instruction
*/
if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_update_nip(ctx, ctx->base.pc_next - 4);
+ gen_update_nip(ctx, ctx->cia);
}
t0 = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
@@ -4140,7 +4141,7 @@ static void gen_eieio(DisasContext *ctx)
*/
if (!(ctx->insns_flags2 & PPC2_ISA300)) {
qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
- TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
+ TARGET_FMT_lx "\n", ctx->cia);
} else {
bar = TCG_MO_ST_LD;
}
@@ -4809,14 +4810,14 @@ static void gen_b(DisasContext *ctx)
li = LI(ctx->opcode);
li = (li ^ 0x02000000) - 0x02000000;
if (likely(AA(ctx->opcode) == 0)) {
- target = ctx->base.pc_next + li - 4;
+ target = ctx->cia + li;
} else {
target = li;
}
if (LK(ctx->opcode)) {
gen_setlr(ctx, ctx->base.pc_next);
}
- gen_update_cfar(ctx, ctx->base.pc_next - 4);
+ gen_update_cfar(ctx, ctx->cia);
gen_goto_tb(ctx, 0, target);
}
@@ -4915,11 +4916,11 @@ static void gen_bcond(DisasContext *ctx, int type)
}
tcg_temp_free_i32(temp);
}
- gen_update_cfar(ctx, ctx->base.pc_next - 4);
+ gen_update_cfar(ctx, ctx->cia);
if (type == BCOND_IM) {
target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
if (likely(AA(ctx->opcode) == 0)) {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
+ gen_goto_tb(ctx, 0, ctx->cia + li);
} else {
gen_goto_tb(ctx, 0, li);
}
@@ -5035,7 +5036,7 @@ static void gen_rfi(DisasContext *ctx)
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
- gen_update_cfar(ctx, ctx->base.pc_next - 4);
+ gen_update_cfar(ctx, ctx->cia);
gen_helper_rfi(cpu_env);
gen_sync_exception(ctx);
#endif
@@ -5052,7 +5053,7 @@ static void gen_rfid(DisasContext *ctx)
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
- gen_update_cfar(ctx, ctx->base.pc_next - 4);
+ gen_update_cfar(ctx, ctx->cia);
gen_helper_rfid(cpu_env);
gen_sync_exception(ctx);
#endif
@@ -5069,7 +5070,7 @@ static void gen_rfscv(DisasContext *ctx)
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
- gen_update_cfar(ctx, ctx->base.pc_next - 4);
+ gen_update_cfar(ctx, ctx->cia);
gen_helper_rfscv(cpu_env);
gen_sync_exception(ctx);
#endif
@@ -5112,7 +5113,7 @@ static void gen_scv(DisasContext *ctx)
/* Set the PC back to the faulting instruction. */
if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_update_nip(ctx, ctx->base.pc_next - 4);
+ gen_update_nip(ctx, ctx->cia);
}
gen_helper_scv(cpu_env, tcg_constant_i32(lev));
@@ -5320,7 +5321,7 @@ static inline void gen_op_mfspr(DisasContext *ctx)
if (sprn != SPR_PVR) {
qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
"%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
- ctx->base.pc_next - 4);
+ ctx->cia);
}
gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
@@ -5334,7 +5335,7 @@ static inline void gen_op_mfspr(DisasContext *ctx)
/* Not defined */
qemu_log_mask(LOG_GUEST_ERROR,
"Trying to read invalid spr %d (0x%03x) at "
- TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
+ TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
/*
* The behaviour depends on MSR:PR and SPR# bit 0x10, it can
@@ -5498,7 +5499,7 @@ static void gen_mtspr(DisasContext *ctx)
/* Privilege exception */
qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
"%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
- ctx->base.pc_next - 4);
+ ctx->cia);
gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
@@ -5512,7 +5513,7 @@ static void gen_mtspr(DisasContext *ctx)
/* Not defined */
qemu_log_mask(LOG_GUEST_ERROR,
"Trying to write invalid spr %d (0x%03x) at "
- TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
+ TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
/*
@@ -9339,6 +9340,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
+ ctx->cia = ctx->base.pc_next;
ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
need_byteswap(ctx));
@@ -9368,7 +9370,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
TARGET_FMT_lx " %d\n",
opc1(ctx->opcode), opc2(ctx->opcode),
opc3(ctx->opcode), opc4(ctx->opcode),
- ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
+ ctx->opcode, ctx->cia, (int)msr_ir);
} else {
uint32_t inval;
@@ -9385,7 +9387,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
TARGET_FMT_lx "\n", ctx->opcode & inval,
opc1(ctx->opcode), opc2(ctx->opcode),
opc3(ctx->opcode), opc4(ctx->opcode),
- ctx->opcode, ctx->base.pc_next - 4);
+ ctx->opcode, ctx->cia);
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
ctx->base.is_jmp = DISAS_NORETURN;
return;
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 01/31] target/ppc: Add cia field to DisasContext
2021-05-12 18:54 ` [PATCH v4 01/31] target/ppc: Add cia field to DisasContext matheus.ferst
@ 2021-05-13 4:03 ` David Gibson
0 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:03 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 8089 bytes --]
On Wed, May 12, 2021 at 03:54:11PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 36 +++++++++++++++++++-----------------
> 1 file changed, 19 insertions(+), 17 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 98850f0c30..9abe03222d 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -154,6 +154,7 @@ void ppc_translate_init(void)
> /* internal defines */
> struct DisasContext {
> DisasContextBase base;
> + target_ulong cia; /* current instruction address */
> uint32_t opcode;
> uint32_t exception;
> /* Routine used to access memory */
> @@ -253,7 +254,7 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
> * faulting instruction
> */
> if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_update_nip(ctx, ctx->base.pc_next - 4);
> + gen_update_nip(ctx, ctx->cia);
> }
> t0 = tcg_const_i32(excp);
> t1 = tcg_const_i32(error);
> @@ -272,7 +273,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
> * faulting instruction
> */
> if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_update_nip(ctx, ctx->base.pc_next - 4);
> + gen_update_nip(ctx, ctx->cia);
> }
> t0 = tcg_const_i32(excp);
> gen_helper_raise_exception(cpu_env, t0);
> @@ -4140,7 +4141,7 @@ static void gen_eieio(DisasContext *ctx)
> */
> if (!(ctx->insns_flags2 & PPC2_ISA300)) {
> qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
> - TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
> + TARGET_FMT_lx "\n", ctx->cia);
> } else {
> bar = TCG_MO_ST_LD;
> }
> @@ -4809,14 +4810,14 @@ static void gen_b(DisasContext *ctx)
> li = LI(ctx->opcode);
> li = (li ^ 0x02000000) - 0x02000000;
> if (likely(AA(ctx->opcode) == 0)) {
> - target = ctx->base.pc_next + li - 4;
> + target = ctx->cia + li;
> } else {
> target = li;
> }
> if (LK(ctx->opcode)) {
> gen_setlr(ctx, ctx->base.pc_next);
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> gen_goto_tb(ctx, 0, target);
> }
>
> @@ -4915,11 +4916,11 @@ static void gen_bcond(DisasContext *ctx, int type)
> }
> tcg_temp_free_i32(temp);
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> if (type == BCOND_IM) {
> target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
> if (likely(AA(ctx->opcode) == 0)) {
> - gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
> + gen_goto_tb(ctx, 0, ctx->cia + li);
> } else {
> gen_goto_tb(ctx, 0, li);
> }
> @@ -5035,7 +5036,7 @@ static void gen_rfi(DisasContext *ctx)
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfi(cpu_env);
> gen_sync_exception(ctx);
> #endif
> @@ -5052,7 +5053,7 @@ static void gen_rfid(DisasContext *ctx)
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfid(cpu_env);
> gen_sync_exception(ctx);
> #endif
> @@ -5069,7 +5070,7 @@ static void gen_rfscv(DisasContext *ctx)
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfscv(cpu_env);
> gen_sync_exception(ctx);
> #endif
> @@ -5112,7 +5113,7 @@ static void gen_scv(DisasContext *ctx)
>
> /* Set the PC back to the faulting instruction. */
> if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_update_nip(ctx, ctx->base.pc_next - 4);
> + gen_update_nip(ctx, ctx->cia);
> }
> gen_helper_scv(cpu_env, tcg_constant_i32(lev));
>
> @@ -5320,7 +5321,7 @@ static inline void gen_op_mfspr(DisasContext *ctx)
> if (sprn != SPR_PVR) {
> qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
> "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
> - ctx->base.pc_next - 4);
> + ctx->cia);
> }
> gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
> }
> @@ -5334,7 +5335,7 @@ static inline void gen_op_mfspr(DisasContext *ctx)
> /* Not defined */
> qemu_log_mask(LOG_GUEST_ERROR,
> "Trying to read invalid spr %d (0x%03x) at "
> - TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
> + TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
>
> /*
> * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
> @@ -5498,7 +5499,7 @@ static void gen_mtspr(DisasContext *ctx)
> /* Privilege exception */
> qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
> "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
> - ctx->base.pc_next - 4);
> + ctx->cia);
> gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
> }
> } else {
> @@ -5512,7 +5513,7 @@ static void gen_mtspr(DisasContext *ctx)
> /* Not defined */
> qemu_log_mask(LOG_GUEST_ERROR,
> "Trying to write invalid spr %d (0x%03x) at "
> - TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
> + TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
>
>
> /*
> @@ -9339,6 +9340,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
> ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
>
> + ctx->cia = ctx->base.pc_next;
> ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
> need_byteswap(ctx));
>
> @@ -9368,7 +9370,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> TARGET_FMT_lx " %d\n",
> opc1(ctx->opcode), opc2(ctx->opcode),
> opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
> + ctx->opcode, ctx->cia, (int)msr_ir);
> } else {
> uint32_t inval;
>
> @@ -9385,7 +9387,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> TARGET_FMT_lx "\n", ctx->opcode & inval,
> opc1(ctx->opcode), opc2(ctx->opcode),
> opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->opcode, ctx->base.pc_next - 4);
> + ctx->opcode, ctx->cia);
> gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> ctx->base.is_jmp = DISAS_NORETURN;
> return;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 02/31] target/ppc: Split out decode_legacy
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 01/31] target/ppc: Add cia field to DisasContext matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 4:03 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception* matheus.ferst
` (29 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 115 +++++++++++++++++++++++------------------
1 file changed, 64 insertions(+), 51 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9abe03222d..3ad4c7163d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -9253,6 +9253,62 @@ void ppc_cpu_dump_statistics(CPUState *cs, int flags)
#endif
}
+static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn)
+{
+ opc_handler_t **table, *handler;
+ uint32_t inval;
+
+ ctx->opcode = insn;
+
+ LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
+ insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn),
+ ctx->le_mode ? "little" : "big");
+
+ table = cpu->opcodes;
+ handler = table[opc1(insn)];
+ if (is_indirect_opcode(handler)) {
+ table = ind_table(handler);
+ handler = table[opc2(insn)];
+ if (is_indirect_opcode(handler)) {
+ table = ind_table(handler);
+ handler = table[opc3(insn)];
+ if (is_indirect_opcode(handler)) {
+ table = ind_table(handler);
+ handler = table[opc4(insn)];
+ }
+ }
+ }
+
+ /* Is opcode *REALLY* valid ? */
+ if (unlikely(handler->handler == &gen_invalid)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
+ "%02x - %02x - %02x - %02x (%08x) "
+ TARGET_FMT_lx "\n",
+ opc1(insn), opc2(insn), opc3(insn), opc4(insn),
+ insn, ctx->cia);
+ return false;
+ }
+
+ if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
+ && Rc(insn))) {
+ inval = handler->inval2;
+ } else {
+ inval = handler->inval1;
+ }
+
+ if (unlikely((insn & inval) != 0)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
+ "%02x - %02x - %02x - %02x (%08x) "
+ TARGET_FMT_lx "\n", insn & inval,
+ opc1(insn), opc2(insn), opc3(insn), opc4(insn),
+ insn, ctx->cia);
+ return false;
+ }
+
+ handler->handler(ctx);
+ return true;
+}
+
static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
@@ -9334,66 +9390,23 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = cs->env_ptr;
- opc_handler_t **table, *handler;
+ uint32_t insn;
+ bool ok;
LOG_DISAS("----------------\n");
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
ctx->cia = ctx->base.pc_next;
- ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
- need_byteswap(ctx));
-
- LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
- ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
- opc3(ctx->opcode), opc4(ctx->opcode),
- ctx->le_mode ? "little" : "big");
+ insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx));
ctx->base.pc_next += 4;
- table = cpu->opcodes;
- handler = table[opc1(ctx->opcode)];
- if (is_indirect_opcode(handler)) {
- table = ind_table(handler);
- handler = table[opc2(ctx->opcode)];
- if (is_indirect_opcode(handler)) {
- table = ind_table(handler);
- handler = table[opc3(ctx->opcode)];
- if (is_indirect_opcode(handler)) {
- table = ind_table(handler);
- handler = table[opc4(ctx->opcode)];
- }
- }
- }
- /* Is opcode *REALLY* valid ? */
- if (unlikely(handler->handler == &gen_invalid)) {
- qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
- "%02x - %02x - %02x - %02x (%08x) "
- TARGET_FMT_lx " %d\n",
- opc1(ctx->opcode), opc2(ctx->opcode),
- opc3(ctx->opcode), opc4(ctx->opcode),
- ctx->opcode, ctx->cia, (int)msr_ir);
- } else {
- uint32_t inval;
- if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
- && Rc(ctx->opcode))) {
- inval = handler->inval2;
- } else {
- inval = handler->inval1;
- }
-
- if (unlikely((ctx->opcode & inval) != 0)) {
- qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
- "%02x - %02x - %02x - %02x (%08x) "
- TARGET_FMT_lx "\n", ctx->opcode & inval,
- opc1(ctx->opcode), opc2(ctx->opcode),
- opc3(ctx->opcode), opc4(ctx->opcode),
- ctx->opcode, ctx->cia);
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- ctx->base.is_jmp = DISAS_NORETURN;
- return;
- }
+ ok = decode_legacy(cpu, ctx, insn);
+ if (!ok) {
+ gen_invalid(ctx);
+ ctx->base.is_jmp = DISAS_NORETURN;
}
- (*(handler->handler))(ctx);
+
#if defined(DO_PPC_STATISTICS)
handler->count++;
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 02/31] target/ppc: Split out decode_legacy
2021-05-12 18:54 ` [PATCH v4 02/31] target/ppc: Split out decode_legacy matheus.ferst
@ 2021-05-13 4:03 ` David Gibson
0 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:03 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 6415 bytes --]
On Wed, May 12, 2021 at 03:54:12PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1.
> ---
> target/ppc/translate.c | 115 +++++++++++++++++++++++------------------
> 1 file changed, 64 insertions(+), 51 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 9abe03222d..3ad4c7163d 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -9253,6 +9253,62 @@ void ppc_cpu_dump_statistics(CPUState *cs, int flags)
> #endif
> }
>
> +static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn)
> +{
> + opc_handler_t **table, *handler;
> + uint32_t inval;
> +
> + ctx->opcode = insn;
> +
> + LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
> + insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn),
> + ctx->le_mode ? "little" : "big");
> +
> + table = cpu->opcodes;
> + handler = table[opc1(insn)];
> + if (is_indirect_opcode(handler)) {
> + table = ind_table(handler);
> + handler = table[opc2(insn)];
> + if (is_indirect_opcode(handler)) {
> + table = ind_table(handler);
> + handler = table[opc3(insn)];
> + if (is_indirect_opcode(handler)) {
> + table = ind_table(handler);
> + handler = table[opc4(insn)];
> + }
> + }
> + }
> +
> + /* Is opcode *REALLY* valid ? */
> + if (unlikely(handler->handler == &gen_invalid)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
> + "%02x - %02x - %02x - %02x (%08x) "
> + TARGET_FMT_lx "\n",
> + opc1(insn), opc2(insn), opc3(insn), opc4(insn),
> + insn, ctx->cia);
> + return false;
> + }
> +
> + if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
> + && Rc(insn))) {
> + inval = handler->inval2;
> + } else {
> + inval = handler->inval1;
> + }
> +
> + if (unlikely((insn & inval) != 0)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
> + "%02x - %02x - %02x - %02x (%08x) "
> + TARGET_FMT_lx "\n", insn & inval,
> + opc1(insn), opc2(insn), opc3(insn), opc4(insn),
> + insn, ctx->cia);
> + return false;
> + }
> +
> + handler->handler(ctx);
> + return true;
> +}
> +
> static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> @@ -9334,66 +9390,23 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> CPUPPCState *env = cs->env_ptr;
> - opc_handler_t **table, *handler;
> + uint32_t insn;
> + bool ok;
>
> LOG_DISAS("----------------\n");
> LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
> ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
>
> ctx->cia = ctx->base.pc_next;
> - ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
> - need_byteswap(ctx));
> -
> - LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
> - ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
> - opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->le_mode ? "little" : "big");
> + insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx));
> ctx->base.pc_next += 4;
> - table = cpu->opcodes;
> - handler = table[opc1(ctx->opcode)];
> - if (is_indirect_opcode(handler)) {
> - table = ind_table(handler);
> - handler = table[opc2(ctx->opcode)];
> - if (is_indirect_opcode(handler)) {
> - table = ind_table(handler);
> - handler = table[opc3(ctx->opcode)];
> - if (is_indirect_opcode(handler)) {
> - table = ind_table(handler);
> - handler = table[opc4(ctx->opcode)];
> - }
> - }
> - }
> - /* Is opcode *REALLY* valid ? */
> - if (unlikely(handler->handler == &gen_invalid)) {
> - qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
> - "%02x - %02x - %02x - %02x (%08x) "
> - TARGET_FMT_lx " %d\n",
> - opc1(ctx->opcode), opc2(ctx->opcode),
> - opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->opcode, ctx->cia, (int)msr_ir);
> - } else {
> - uint32_t inval;
>
> - if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
> - && Rc(ctx->opcode))) {
> - inval = handler->inval2;
> - } else {
> - inval = handler->inval1;
> - }
> -
> - if (unlikely((ctx->opcode & inval) != 0)) {
> - qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
> - "%02x - %02x - %02x - %02x (%08x) "
> - TARGET_FMT_lx "\n", ctx->opcode & inval,
> - opc1(ctx->opcode), opc2(ctx->opcode),
> - opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->opcode, ctx->cia);
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> - ctx->base.is_jmp = DISAS_NORETURN;
> - return;
> - }
> + ok = decode_legacy(cpu, ctx, insn);
> + if (!ok) {
> + gen_invalid(ctx);
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
> - (*(handler->handler))(ctx);
> +
> #if defined(DO_PPC_STATISTICS)
> handler->count++;
> #endif
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception*
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-05-12 18:54 ` [PATCH v4 01/31] target/ppc: Add cia field to DisasContext matheus.ferst
2021-05-12 18:54 ` [PATCH v4 02/31] target/ppc: Split out decode_legacy matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 4:06 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL matheus.ferst
` (28 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
There are other valid settings for is_jmp besides
DISAS_NEXT and DISAS_NORETURN, so eliminating that
dichotomy from ppc_tr_translate_insn is helpful.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3ad4c7163d..616ffc1508 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -261,7 +261,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
gen_helper_raise_exception_err(cpu_env, t0, t1);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
- ctx->exception = (excp);
+ ctx->exception = excp;
+ ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_exception(DisasContext *ctx, uint32_t excp)
@@ -278,7 +279,8 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
t0 = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
- ctx->exception = (excp);
+ ctx->exception = excp;
+ ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
@@ -290,7 +292,8 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
t0 = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
- ctx->exception = (excp);
+ ctx->exception = excp;
+ ctx->base.is_jmp = DISAS_NORETURN;
}
/*
@@ -336,6 +339,7 @@ static void gen_debug_exception(DisasContext *ctx)
t0 = tcg_const_i32(EXCP_DEBUG);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
+ ctx->base.is_jmp = DISAS_NORETURN;
}
static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
@@ -9374,7 +9378,6 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
DisasContext *ctx = container_of(dcbase, DisasContext, base);
gen_debug_exception(ctx);
- dcbase->is_jmp = DISAS_NORETURN;
/*
* The address covered by the breakpoint must be included in
* [tb->pc, tb->pc + tb->size) in order to for it to be properly
@@ -9404,18 +9407,19 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
ok = decode_legacy(cpu, ctx, insn);
if (!ok) {
gen_invalid(ctx);
- ctx->base.is_jmp = DISAS_NORETURN;
}
#if defined(DO_PPC_STATISTICS)
handler->count++;
#endif
+
/* Check trace mode exceptions */
if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
(ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
ctx->exception != POWERPC_SYSCALL &&
ctx->exception != POWERPC_EXCP_TRAP &&
- ctx->exception != POWERPC_EXCP_BRANCH)) {
+ ctx->exception != POWERPC_EXCP_BRANCH &&
+ ctx->base.is_jmp != DISAS_NORETURN)) {
uint32_t excp = gen_prep_dbgex(ctx);
gen_exception_nip(ctx, excp, ctx->base.pc_next);
}
@@ -9426,14 +9430,20 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
}
- ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
- DISAS_NEXT : DISAS_NORETURN;
+ if (ctx->base.is_jmp == DISAS_NEXT
+ && ctx->exception != POWERPC_EXCP_NONE) {
+ ctx->base.is_jmp = DISAS_TOO_MANY;
+ }
}
static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ if (ctx->base.is_jmp == DISAS_NORETURN) {
+ return;
+ }
+
if (ctx->exception == POWERPC_EXCP_NONE) {
gen_goto_tb(ctx, 0, ctx->base.pc_next);
} else if (ctx->exception != POWERPC_EXCP_BRANCH) {
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception*
2021-05-12 18:54 ` [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception* matheus.ferst
@ 2021-05-13 4:06 ` David Gibson
0 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:06 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4664 bytes --]
On Wed, May 12, 2021 at 03:54:13PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> There are other valid settings for is_jmp besides
> DISAS_NEXT and DISAS_NORETURN, so eliminating that
> dichotomy from ppc_tr_translate_insn is helpful.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 26 ++++++++++++++++++--------
> 1 file changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 3ad4c7163d..616ffc1508 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -261,7 +261,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
> gen_helper_raise_exception_err(cpu_env, t0, t1);
> tcg_temp_free_i32(t0);
> tcg_temp_free_i32(t1);
> - ctx->exception = (excp);
> + ctx->exception = excp;
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> static void gen_exception(DisasContext *ctx, uint32_t excp)
> @@ -278,7 +279,8 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
> t0 = tcg_const_i32(excp);
> gen_helper_raise_exception(cpu_env, t0);
> tcg_temp_free_i32(t0);
> - ctx->exception = (excp);
> + ctx->exception = excp;
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> @@ -290,7 +292,8 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> t0 = tcg_const_i32(excp);
> gen_helper_raise_exception(cpu_env, t0);
> tcg_temp_free_i32(t0);
> - ctx->exception = (excp);
> + ctx->exception = excp;
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> /*
> @@ -336,6 +339,7 @@ static void gen_debug_exception(DisasContext *ctx)
> t0 = tcg_const_i32(EXCP_DEBUG);
> gen_helper_raise_exception(cpu_env, t0);
> tcg_temp_free_i32(t0);
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
> @@ -9374,7 +9378,6 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
>
> gen_debug_exception(ctx);
> - dcbase->is_jmp = DISAS_NORETURN;
> /*
> * The address covered by the breakpoint must be included in
> * [tb->pc, tb->pc + tb->size) in order to for it to be properly
> @@ -9404,18 +9407,19 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> ok = decode_legacy(cpu, ctx, insn);
> if (!ok) {
> gen_invalid(ctx);
> - ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> #if defined(DO_PPC_STATISTICS)
> handler->count++;
> #endif
> +
> /* Check trace mode exceptions */
> if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
> (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
> ctx->exception != POWERPC_SYSCALL &&
> ctx->exception != POWERPC_EXCP_TRAP &&
> - ctx->exception != POWERPC_EXCP_BRANCH)) {
> + ctx->exception != POWERPC_EXCP_BRANCH &&
> + ctx->base.is_jmp != DISAS_NORETURN)) {
> uint32_t excp = gen_prep_dbgex(ctx);
> gen_exception_nip(ctx, excp, ctx->base.pc_next);
> }
> @@ -9426,14 +9430,20 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
> }
>
> - ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
> - DISAS_NEXT : DISAS_NORETURN;
> + if (ctx->base.is_jmp == DISAS_NEXT
> + && ctx->exception != POWERPC_EXCP_NONE) {
> + ctx->base.is_jmp = DISAS_TOO_MANY;
> + }
> }
>
> static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
>
> + if (ctx->base.is_jmp == DISAS_NORETURN) {
> + return;
> + }
> +
> if (ctx->exception == POWERPC_EXCP_NONE) {
> gen_goto_tb(ctx, 0, ctx->base.pc_next);
> } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (2 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception* matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 4:06 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP matheus.ferst
` (27 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Since POWERPC_SYSCALL is raised by gen_exception_err,
we will have also set DISAS_NORETURN.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 616ffc1508..2303bf259a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -9416,7 +9416,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
/* Check trace mode exceptions */
if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
(ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
- ctx->exception != POWERPC_SYSCALL &&
ctx->exception != POWERPC_EXCP_TRAP &&
ctx->exception != POWERPC_EXCP_BRANCH &&
ctx->base.is_jmp != DISAS_NORETURN)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL
2021-05-12 18:54 ` [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL matheus.ferst
@ 2021-05-13 4:06 ` David Gibson
0 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:06 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 1438 bytes --]
On Wed, May 12, 2021 at 03:54:14PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Since POWERPC_SYSCALL is raised by gen_exception_err,
> we will have also set DISAS_NORETURN.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 616ffc1508..2303bf259a 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -9416,7 +9416,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> /* Check trace mode exceptions */
> if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
> (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
> - ctx->exception != POWERPC_SYSCALL &&
> ctx->exception != POWERPC_EXCP_TRAP &&
> ctx->exception != POWERPC_EXCP_BRANCH &&
> ctx->base.is_jmp != DISAS_NORETURN)) {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (3 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 4:07 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception matheus.ferst
` (26 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Since POWERPC_EXCP_TRAP is raised by gen_exception_err,
we will have also set DISAS_NORETURN.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 2303bf259a..23de04a08e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -9416,7 +9416,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
/* Check trace mode exceptions */
if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
(ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
- ctx->exception != POWERPC_EXCP_TRAP &&
ctx->exception != POWERPC_EXCP_BRANCH &&
ctx->base.is_jmp != DISAS_NORETURN)) {
uint32_t excp = gen_prep_dbgex(ctx);
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP
2021-05-12 18:54 ` [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP matheus.ferst
@ 2021-05-13 4:07 ` David Gibson
0 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:07 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 1431 bytes --]
On Wed, May 12, 2021 at 03:54:15PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Since POWERPC_EXCP_TRAP is raised by gen_exception_err,
> we will have also set DISAS_NORETURN.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 2303bf259a..23de04a08e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -9416,7 +9416,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> /* Check trace mode exceptions */
> if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
> (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
> - ctx->exception != POWERPC_EXCP_TRAP &&
> ctx->exception != POWERPC_EXCP_BRANCH &&
> ctx->base.is_jmp != DISAS_NORETURN)) {
> uint32_t excp = gen_prep_dbgex(ctx);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (4 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 4:08 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 07/31] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} matheus.ferst
` (25 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Two of the call sites that use gen_debug_exception have already
updated NIP. Only ppc_tr_breakpoint_check requires the update.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 23de04a08e..7b23f85c11 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -326,19 +326,7 @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
static void gen_debug_exception(DisasContext *ctx)
{
- TCGv_i32 t0;
-
- /*
- * These are all synchronous exceptions, we set the PC back to the
- * faulting instruction
- */
- if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
- (ctx->exception != POWERPC_EXCP_SYNC)) {
- gen_update_nip(ctx, ctx->base.pc_next);
- }
- t0 = tcg_const_i32(EXCP_DEBUG);
- gen_helper_raise_exception(cpu_env, t0);
- tcg_temp_free_i32(t0);
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -9377,6 +9365,7 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ gen_update_nip(ctx, ctx->base.pc_next);
gen_debug_exception(ctx);
/*
* The address covered by the breakpoint must be included in
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception
2021-05-12 18:54 ` [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception matheus.ferst
@ 2021-05-13 4:08 ` David Gibson
0 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:08 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 1982 bytes --]
On Wed, May 12, 2021 at 03:54:16PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Two of the call sites that use gen_debug_exception have already
> updated NIP. Only ppc_tr_breakpoint_check requires the update.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 15 ++-------------
> 1 file changed, 2 insertions(+), 13 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 23de04a08e..7b23f85c11 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -326,19 +326,7 @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
>
> static void gen_debug_exception(DisasContext *ctx)
> {
> - TCGv_i32 t0;
> -
> - /*
> - * These are all synchronous exceptions, we set the PC back to the
> - * faulting instruction
> - */
> - if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
> - (ctx->exception != POWERPC_EXCP_SYNC)) {
> - gen_update_nip(ctx, ctx->base.pc_next);
> - }
> - t0 = tcg_const_i32(EXCP_DEBUG);
> - gen_helper_raise_exception(cpu_env, t0);
> - tcg_temp_free_i32(t0);
> + gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> @@ -9377,6 +9365,7 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
>
> + gen_update_nip(ctx, ctx->base.pc_next);
> gen_debug_exception(ctx);
> /*
> * The address covered by the breakpoint must be included in
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 07/31] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE}
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (5 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 4:10 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT matheus.ferst
` (24 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Rewrite ppc_tr_tb_stop to handle these new codes.
Convert ctx->exception into these new codes at the end of
ppc_tr_translate_insn, prior to pushing the change back
throughout translate.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 75 ++++++++++++++++++++++++++++++++++++------
1 file changed, 65 insertions(+), 10 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 7b23f85c11..4bebb00bb2 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -182,6 +182,11 @@ struct DisasContext {
uint64_t insns_flags2;
};
+#define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */
+#define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */
+#define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */
+#define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */
+
/* Return true iff byteswap is needed in a scalar memop */
static inline bool need_byteswap(const DisasContext *ctx)
{
@@ -9417,28 +9422,78 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
}
- if (ctx->base.is_jmp == DISAS_NEXT
- && ctx->exception != POWERPC_EXCP_NONE) {
- ctx->base.is_jmp = DISAS_TOO_MANY;
+ if (ctx->base.is_jmp == DISAS_NEXT) {
+ switch (ctx->exception) {
+ case POWERPC_EXCP_NONE:
+ break;
+ case POWERPC_EXCP_BRANCH:
+ ctx->base.is_jmp = DISAS_NORETURN;
+ break;
+ case POWERPC_EXCP_SYNC:
+ case POWERPC_EXCP_STOP:
+ ctx->base.is_jmp = DISAS_EXIT;
+ break;
+ default:
+ /* Every other ctx->exception should have set NORETURN. */
+ g_assert_not_reached();
+ }
}
}
static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ DisasJumpType is_jmp = ctx->base.is_jmp;
+ target_ulong nip = ctx->base.pc_next;
- if (ctx->base.is_jmp == DISAS_NORETURN) {
+ if (is_jmp == DISAS_NORETURN) {
+ /* We have already exited the TB. */
return;
}
- if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
- } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
- if (unlikely(ctx->base.singlestep_enabled)) {
- gen_debug_exception(ctx);
+ /* Honor single stepping. */
+ if (unlikely(ctx->base.singlestep_enabled)) {
+ switch (is_jmp) {
+ case DISAS_TOO_MANY:
+ case DISAS_EXIT_UPDATE:
+ case DISAS_CHAIN_UPDATE:
+ gen_update_nip(ctx, nip);
+ break;
+ case DISAS_EXIT:
+ case DISAS_CHAIN:
+ break;
+ default:
+ g_assert_not_reached();
}
- /* Generate the return instruction */
+ gen_debug_exception(ctx);
+ return;
+ }
+
+ switch (is_jmp) {
+ case DISAS_TOO_MANY:
+ if (use_goto_tb(ctx, nip)) {
+ tcg_gen_goto_tb(0);
+ gen_update_nip(ctx, nip);
+ tcg_gen_exit_tb(ctx->base.tb, 0);
+ break;
+ }
+ /* fall through */
+ case DISAS_CHAIN_UPDATE:
+ gen_update_nip(ctx, nip);
+ /* fall through */
+ case DISAS_CHAIN:
+ tcg_gen_lookup_and_goto_ptr();
+ break;
+
+ case DISAS_EXIT_UPDATE:
+ gen_update_nip(ctx, nip);
+ /* fall through */
+ case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
+ break;
+
+ default:
+ g_assert_not_reached();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 07/31] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE}
2021-05-12 18:54 ` [PATCH v4 07/31] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} matheus.ferst
@ 2021-05-13 4:10 ` David Gibson
0 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:10 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4474 bytes --]
On Wed, May 12, 2021 at 03:54:17PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Rewrite ppc_tr_tb_stop to handle these new codes.
>
> Convert ctx->exception into these new codes at the end of
> ppc_tr_translate_insn, prior to pushing the change back
> throughout translate.c.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 75 ++++++++++++++++++++++++++++++++++++------
> 1 file changed, 65 insertions(+), 10 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 7b23f85c11..4bebb00bb2 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -182,6 +182,11 @@ struct DisasContext {
> uint64_t insns_flags2;
> };
>
> +#define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */
> +#define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */
> +#define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */
> +#define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */
> +
> /* Return true iff byteswap is needed in a scalar memop */
> static inline bool need_byteswap(const DisasContext *ctx)
> {
> @@ -9417,28 +9422,78 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
> }
>
> - if (ctx->base.is_jmp == DISAS_NEXT
> - && ctx->exception != POWERPC_EXCP_NONE) {
> - ctx->base.is_jmp = DISAS_TOO_MANY;
> + if (ctx->base.is_jmp == DISAS_NEXT) {
> + switch (ctx->exception) {
> + case POWERPC_EXCP_NONE:
> + break;
> + case POWERPC_EXCP_BRANCH:
> + ctx->base.is_jmp = DISAS_NORETURN;
> + break;
> + case POWERPC_EXCP_SYNC:
> + case POWERPC_EXCP_STOP:
> + ctx->base.is_jmp = DISAS_EXIT;
> + break;
> + default:
> + /* Every other ctx->exception should have set NORETURN. */
> + g_assert_not_reached();
> + }
> }
> }
>
> static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> + DisasJumpType is_jmp = ctx->base.is_jmp;
> + target_ulong nip = ctx->base.pc_next;
>
> - if (ctx->base.is_jmp == DISAS_NORETURN) {
> + if (is_jmp == DISAS_NORETURN) {
> + /* We have already exited the TB. */
> return;
> }
>
> - if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_goto_tb(ctx, 0, ctx->base.pc_next);
> - } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
> - if (unlikely(ctx->base.singlestep_enabled)) {
> - gen_debug_exception(ctx);
> + /* Honor single stepping. */
> + if (unlikely(ctx->base.singlestep_enabled)) {
> + switch (is_jmp) {
> + case DISAS_TOO_MANY:
> + case DISAS_EXIT_UPDATE:
> + case DISAS_CHAIN_UPDATE:
> + gen_update_nip(ctx, nip);
> + break;
> + case DISAS_EXIT:
> + case DISAS_CHAIN:
> + break;
> + default:
> + g_assert_not_reached();
> }
> - /* Generate the return instruction */
> + gen_debug_exception(ctx);
> + return;
> + }
> +
> + switch (is_jmp) {
> + case DISAS_TOO_MANY:
> + if (use_goto_tb(ctx, nip)) {
> + tcg_gen_goto_tb(0);
> + gen_update_nip(ctx, nip);
> + tcg_gen_exit_tb(ctx->base.tb, 0);
> + break;
> + }
> + /* fall through */
> + case DISAS_CHAIN_UPDATE:
> + gen_update_nip(ctx, nip);
> + /* fall through */
> + case DISAS_CHAIN:
> + tcg_gen_lookup_and_goto_ptr();
> + break;
> +
> + case DISAS_EXIT_UPDATE:
> + gen_update_nip(ctx, nip);
> + /* fall through */
> + case DISAS_EXIT:
> tcg_gen_exit_tb(NULL, 0);
> + break;
> +
> + default:
> + g_assert_not_reached();
> }
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (6 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 07/31] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 19:31 ` Bruno Piazera Larsen
2021-05-13 4:11 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 09/31] target/ppc: Remove unnecessary gen_io_end calls matheus.ferst
` (23 subsequent siblings)
31 siblings, 2 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Remove the synthetic "exception" after no more uses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/cpu.h | 1 -
target/ppc/translate.c | 27 +++++++++------------------
2 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 98fcf1c4d6..503de6db85 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -135,7 +135,6 @@ enum {
POWERPC_EXCP_STOP = 0x200, /* stop translation */
POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
/* QEMU exceptions: special cases we want to stop translation */
- POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
};
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4bebb00bb2..88fe24ef95 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -359,14 +359,6 @@ static inline void gen_stop_exception(DisasContext *ctx)
ctx->exception = POWERPC_EXCP_STOP;
}
-#ifndef CONFIG_USER_ONLY
-/* No need to update nip here, as execution flow will change */
-static inline void gen_sync_exception(DisasContext *ctx)
-{
- ctx->exception = POWERPC_EXCP_SYNC;
-}
-#endif
-
/*****************************************************************************/
/* SPR READ/WRITE CALLBACKS */
@@ -5035,7 +5027,7 @@ static void gen_rfi(DisasContext *ctx)
}
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfi(cpu_env);
- gen_sync_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT;
#endif
}
@@ -5052,7 +5044,7 @@ static void gen_rfid(DisasContext *ctx)
}
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfid(cpu_env);
- gen_sync_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT;
#endif
}
@@ -5069,7 +5061,7 @@ static void gen_rfscv(DisasContext *ctx)
}
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfscv(cpu_env);
- gen_sync_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT;
#endif
}
#endif
@@ -5082,7 +5074,7 @@ static void gen_hrfid(DisasContext *ctx)
/* Restore CPU state */
CHK_HV;
gen_helper_hrfid(cpu_env);
- gen_sync_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT;
#endif
}
#endif
@@ -6923,7 +6915,7 @@ static void gen_rfsvc(DisasContext *ctx)
CHK_SV;
gen_helper_rfsvc(cpu_env);
- gen_sync_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT;
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -7303,7 +7295,7 @@ static void gen_rfci_40x(DisasContext *ctx)
CHK_SV;
/* Restore CPU state */
gen_helper_40x_rfci(cpu_env);
- gen_sync_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT;
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -7315,7 +7307,7 @@ static void gen_rfci(DisasContext *ctx)
CHK_SV;
/* Restore CPU state */
gen_helper_rfci(cpu_env);
- gen_sync_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT;
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -7330,7 +7322,7 @@ static void gen_rfdi(DisasContext *ctx)
CHK_SV;
/* Restore CPU state */
gen_helper_rfdi(cpu_env);
- gen_sync_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT;
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -7343,7 +7335,7 @@ static void gen_rfmci(DisasContext *ctx)
CHK_SV;
/* Restore CPU state */
gen_helper_rfmci(cpu_env);
- gen_sync_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT;
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -9429,7 +9421,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
case POWERPC_EXCP_BRANCH:
ctx->base.is_jmp = DISAS_NORETURN;
break;
- case POWERPC_EXCP_SYNC:
case POWERPC_EXCP_STOP:
ctx->base.is_jmp = DISAS_EXIT;
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT
2021-05-12 18:54 ` [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT matheus.ferst
@ 2021-05-12 19:31 ` Bruno Piazera Larsen
2021-05-13 4:11 ` David Gibson
1 sibling, 0 replies; 56+ messages in thread
From: Bruno Piazera Larsen @ 2021-05-12 19:31 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, luis.pires, richard.henderson, f4bug, david
[-- Attachment #1: Type: text/plain, Size: 4728 bytes --]
On 12/05/2021 15:54, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Remove the synthetic "exception" after no more uses.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
> target/ppc/cpu.h | 1 -
> target/ppc/translate.c | 27 +++++++++------------------
> 2 files changed, 9 insertions(+), 19 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 98fcf1c4d6..503de6db85 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -135,7 +135,6 @@ enum {
> POWERPC_EXCP_STOP = 0x200, /* stop translation */
> POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
> /* QEMU exceptions: special cases we want to stop translation */
> - POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
> POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
> };
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 4bebb00bb2..88fe24ef95 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -359,14 +359,6 @@ static inline void gen_stop_exception(DisasContext *ctx)
> ctx->exception = POWERPC_EXCP_STOP;
> }
>
> -#ifndef CONFIG_USER_ONLY
> -/* No need to update nip here, as execution flow will change */
> -static inline void gen_sync_exception(DisasContext *ctx)
> -{
> - ctx->exception = POWERPC_EXCP_SYNC;
> -}
> -#endif
> -
> /*****************************************************************************/
> /* SPR READ/WRITE CALLBACKS */
>
> @@ -5035,7 +5027,7 @@ static void gen_rfi(DisasContext *ctx)
> }
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfi(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif
> }
>
> @@ -5052,7 +5044,7 @@ static void gen_rfid(DisasContext *ctx)
> }
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfid(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif
> }
>
> @@ -5069,7 +5061,7 @@ static void gen_rfscv(DisasContext *ctx)
> }
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfscv(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif
> }
> #endif
> @@ -5082,7 +5074,7 @@ static void gen_hrfid(DisasContext *ctx)
> /* Restore CPU state */
> CHK_HV;
> gen_helper_hrfid(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif
> }
> #endif
> @@ -6923,7 +6915,7 @@ static void gen_rfsvc(DisasContext *ctx)
> CHK_SV;
>
> gen_helper_rfsvc(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -7303,7 +7295,7 @@ static void gen_rfci_40x(DisasContext *ctx)
> CHK_SV;
> /* Restore CPU state */
> gen_helper_40x_rfci(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -7315,7 +7307,7 @@ static void gen_rfci(DisasContext *ctx)
> CHK_SV;
> /* Restore CPU state */
> gen_helper_rfci(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -7330,7 +7322,7 @@ static void gen_rfdi(DisasContext *ctx)
> CHK_SV;
> /* Restore CPU state */
> gen_helper_rfdi(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -7343,7 +7335,7 @@ static void gen_rfmci(DisasContext *ctx)
> CHK_SV;
> /* Restore CPU state */
> gen_helper_rfmci(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -9429,7 +9421,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> case POWERPC_EXCP_BRANCH:
> ctx->base.is_jmp = DISAS_NORETURN;
> break;
> - case POWERPC_EXCP_SYNC:
> case POWERPC_EXCP_STOP:
> ctx->base.is_jmp = DISAS_EXIT;
> break;
Reviewed-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
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^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT
2021-05-12 18:54 ` [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT matheus.ferst
2021-05-12 19:31 ` Bruno Piazera Larsen
@ 2021-05-13 4:11 ` David Gibson
1 sibling, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:11 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4674 bytes --]
On Wed, May 12, 2021 at 03:54:18PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Remove the synthetic "exception" after no more uses.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/cpu.h | 1 -
> target/ppc/translate.c | 27 +++++++++------------------
> 2 files changed, 9 insertions(+), 19 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 98fcf1c4d6..503de6db85 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -135,7 +135,6 @@ enum {
> POWERPC_EXCP_STOP = 0x200, /* stop translation */
> POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
> /* QEMU exceptions: special cases we want to stop translation */
> - POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
> POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
> };
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 4bebb00bb2..88fe24ef95 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -359,14 +359,6 @@ static inline void gen_stop_exception(DisasContext *ctx)
> ctx->exception = POWERPC_EXCP_STOP;
> }
>
> -#ifndef CONFIG_USER_ONLY
> -/* No need to update nip here, as execution flow will change */
> -static inline void gen_sync_exception(DisasContext *ctx)
> -{
> - ctx->exception = POWERPC_EXCP_SYNC;
> -}
> -#endif
> -
> /*****************************************************************************/
> /* SPR READ/WRITE CALLBACKS */
>
> @@ -5035,7 +5027,7 @@ static void gen_rfi(DisasContext *ctx)
> }
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfi(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif
> }
>
> @@ -5052,7 +5044,7 @@ static void gen_rfid(DisasContext *ctx)
> }
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfid(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif
> }
>
> @@ -5069,7 +5061,7 @@ static void gen_rfscv(DisasContext *ctx)
> }
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfscv(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif
> }
> #endif
> @@ -5082,7 +5074,7 @@ static void gen_hrfid(DisasContext *ctx)
> /* Restore CPU state */
> CHK_HV;
> gen_helper_hrfid(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif
> }
> #endif
> @@ -6923,7 +6915,7 @@ static void gen_rfsvc(DisasContext *ctx)
> CHK_SV;
>
> gen_helper_rfsvc(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -7303,7 +7295,7 @@ static void gen_rfci_40x(DisasContext *ctx)
> CHK_SV;
> /* Restore CPU state */
> gen_helper_40x_rfci(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -7315,7 +7307,7 @@ static void gen_rfci(DisasContext *ctx)
> CHK_SV;
> /* Restore CPU state */
> gen_helper_rfci(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -7330,7 +7322,7 @@ static void gen_rfdi(DisasContext *ctx)
> CHK_SV;
> /* Restore CPU state */
> gen_helper_rfdi(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -7343,7 +7335,7 @@ static void gen_rfmci(DisasContext *ctx)
> CHK_SV;
> /* Restore CPU state */
> gen_helper_rfmci(cpu_env);
> - gen_sync_exception(ctx);
> + ctx->base.is_jmp = DISAS_EXIT;
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> @@ -9429,7 +9421,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> case POWERPC_EXCP_BRANCH:
> ctx->base.is_jmp = DISAS_NORETURN;
> break;
> - case POWERPC_EXCP_SYNC:
> case POWERPC_EXCP_STOP:
> ctx->base.is_jmp = DISAS_EXIT;
> break;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 09/31] target/ppc: Remove unnecessary gen_io_end calls
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (7 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 08/31] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 4:12 ` David Gibson
2021-05-12 18:54 ` [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start matheus.ferst
` (22 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Since ba3e7926691ed33, we switched the implementation of icount
to always reset can_do_io at the start of the following TB.
Most of them were removed in 9e9b10c64911, but some were missed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 88fe24ef95..1c02e21a56 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -568,7 +568,6 @@ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
}
gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
gen_stop_exception(ctx);
}
}
@@ -580,7 +579,6 @@ static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
}
gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
gen_stop_exception(ctx);
}
}
@@ -605,7 +603,6 @@ static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
}
gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
gen_stop_exception(ctx);
}
}
@@ -617,7 +614,6 @@ static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
}
gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
gen_stop_exception(ctx);
}
}
@@ -666,7 +662,6 @@ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
}
gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
gen_stop_exception(ctx);
}
}
@@ -678,7 +673,6 @@ static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
}
gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
gen_stop_exception(ctx);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 09/31] target/ppc: Remove unnecessary gen_io_end calls
2021-05-12 18:54 ` [PATCH v4 09/31] target/ppc: Remove unnecessary gen_io_end calls matheus.ferst
@ 2021-05-13 4:12 ` David Gibson
0 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:12 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 2677 bytes --]
On Wed, May 12, 2021 at 03:54:19PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Since ba3e7926691ed33, we switched the implementation of icount
> to always reset can_do_io at the start of the following TB.
> Most of them were removed in 9e9b10c64911, but some were missed.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 88fe24ef95..1c02e21a56 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -568,7 +568,6 @@ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
> }
> gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> gen_stop_exception(ctx);
> }
> }
> @@ -580,7 +579,6 @@ static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
> }
> gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> gen_stop_exception(ctx);
> }
> }
> @@ -605,7 +603,6 @@ static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
> }
> gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> gen_stop_exception(ctx);
> }
> }
> @@ -617,7 +614,6 @@ static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
> }
> gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> gen_stop_exception(ctx);
> }
> }
> @@ -666,7 +662,6 @@ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
> }
> gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> gen_stop_exception(ctx);
> }
> }
> @@ -678,7 +673,6 @@ static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
> }
> gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_end();
> gen_stop_exception(ctx);
> }
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (8 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 09/31] target/ppc: Remove unnecessary gen_io_end calls matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 19:21 ` Matheus K. Ferst
2021-05-12 18:54 ` [PATCH v4 11/31] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
` (21 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Create a function to handle the details for interacting with icount.
Force the exit from the tb via DISAS_TOO_MANY, which allows chaining
to the next tb, where the code emitted for gen_tb_start() will
determine if we must exit. We can thus remove any matching
conditional call to gen_stop_exception.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 174 +++++++++--------------------------------
1 file changed, 39 insertions(+), 135 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1c02e21a56..f6410dc76c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -301,6 +301,20 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
ctx->base.is_jmp = DISAS_NORETURN;
}
+static void gen_icount_io_start(DisasContext *ctx)
+{
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ /*
+ * An I/O instruction must be last in the TB.
+ * Chain to the next TB, and let the code from gen_tb_start
+ * decide if we need to return to the main loop.
+ * Doing this first also allows this value to be overridden.
+ */
+ ctx->base.is_jmp = DISAS_TOO_MANY;
+ }
+}
+
/*
* Tells the caller what is the appropriate exception to generate and prepares
* SPR registers for this exception.
@@ -538,24 +552,14 @@ static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
#endif
@@ -563,24 +567,14 @@ static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
/* Time base */
static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
ATTRIBUTE_UNUSED
@@ -598,24 +592,14 @@ static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
#if !defined(CONFIG_USER_ONLY)
static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
ATTRIBUTE_UNUSED
@@ -634,80 +618,45 @@ static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
ATTRIBUTE_UNUSED
static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
/* HDECR */
static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
#endif
@@ -915,71 +864,41 @@ static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_store_spr(sprn, cpu_gpr[gprn]);
gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
/* We must stop translation as we may have rebooted */
gen_stop_exception(ctx);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
{
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
#endif
@@ -2863,18 +2782,13 @@ static void gen_darn(DisasContext *ctx)
if (l > 2) {
tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
} else {
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
if (l == 0) {
gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
} else {
/* Return 64-bit random for both CRN and RRN */
gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
}
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_stop_exception(ctx);
- }
}
}
#endif
@@ -5016,9 +4930,7 @@ static void gen_rfi(DisasContext *ctx)
}
/* Restore CPU state */
CHK_SV;
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfi(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5033,9 +4945,7 @@ static void gen_rfid(DisasContext *ctx)
#else
/* Restore CPU state */
CHK_SV;
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfid(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5050,9 +4960,7 @@ static void gen_rfscv(DisasContext *ctx)
#else
/* Restore CPU state */
CHK_SV;
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfscv(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5382,9 +5290,7 @@ static void gen_mtmsrd(DisasContext *ctx)
CHK_SV;
#if !defined(CONFIG_USER_ONLY)
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
if (ctx->opcode & 0x00010000) {
/* L=1 form only updates EE and RI */
TCGv t0 = tcg_temp_new();
@@ -5419,9 +5325,7 @@ static void gen_mtmsr(DisasContext *ctx)
CHK_SV;
#if !defined(CONFIG_USER_ONLY)
- if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
+ gen_icount_io_start(ctx);
if (ctx->opcode & 0x00010000) {
/* L=1 form only updates EE and RI */
TCGv t0 = tcg_temp_new();
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start
2021-05-12 18:54 ` [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start matheus.ferst
@ 2021-05-12 19:21 ` Matheus K. Ferst
2021-05-13 4:14 ` David Gibson
0 siblings, 1 reply; 56+ messages in thread
From: Matheus K. Ferst @ 2021-05-12 19:21 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen, david
On 12/05/2021 15:54, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Create a function to handle the details for interacting with icount.
>
> Force the exit from the tb via DISAS_TOO_MANY, which allows chaining
> to the next tb, where the code emitted for gen_tb_start() will
> determine if we must exit. We can thus remove any matching
> conditional call to gen_stop_exception.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
> target/ppc/translate.c | 174 +++++++++--------------------------------
> 1 file changed, 39 insertions(+), 135 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 1c02e21a56..f6410dc76c 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -301,6 +301,20 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> +static void gen_icount_io_start(DisasContext *ctx)
> +{
> + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> + gen_io_start();
> + /*
> + * An I/O instruction must be last in the TB.
> + * Chain to the next TB, and let the code from gen_tb_start
> + * decide if we need to return to the main loop.
> + * Doing this first also allows this value to be overridden.
> + */
> + ctx->base.is_jmp = DISAS_TOO_MANY;
> + }
> +}
> +
> /*
> * Tells the caller what is the appropriate exception to generate and prepares
> * SPR registers for this exception.
> @@ -538,24 +552,14 @@ static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
> #if !defined(CONFIG_USER_ONLY)
> static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
> #endif
>
> @@ -563,24 +567,14 @@ static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> /* Time base */
> static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> ATTRIBUTE_UNUSED
> @@ -598,24 +592,14 @@ static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
> #if !defined(CONFIG_USER_ONLY)
> static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> ATTRIBUTE_UNUSED
> @@ -634,80 +618,45 @@ static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
> ATTRIBUTE_UNUSED
> static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> /* HDECR */
> static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> #endif
> @@ -915,71 +864,41 @@ static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
> #if !defined(CONFIG_USER_ONLY)
> static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_store_spr(sprn, cpu_gpr[gprn]);
> gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
> /* We must stop translation as we may have rebooted */
> gen_stop_exception(ctx);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
>
> static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
> {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
> #endif
>
> @@ -2863,18 +2782,13 @@ static void gen_darn(DisasContext *ctx)
> if (l > 2) {
> tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
> } else {
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> if (l == 0) {
> gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
> } else {
> /* Return 64-bit random for both CRN and RRN */
> gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
> }
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_stop_exception(ctx);
> - }
> }
> }
> #endif
> @@ -5016,9 +4930,7 @@ static void gen_rfi(DisasContext *ctx)
> }
> /* Restore CPU state */
> CHK_SV;
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfi(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> @@ -5033,9 +4945,7 @@ static void gen_rfid(DisasContext *ctx)
> #else
> /* Restore CPU state */
> CHK_SV;
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfid(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> @@ -5050,9 +4960,7 @@ static void gen_rfscv(DisasContext *ctx)
> #else
> /* Restore CPU state */
> CHK_SV;
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfscv(cpu_env);
> ctx->base.is_jmp = DISAS_EXIT;
> @@ -5382,9 +5290,7 @@ static void gen_mtmsrd(DisasContext *ctx)
> CHK_SV;
>
> #if !defined(CONFIG_USER_ONLY)
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> if (ctx->opcode & 0x00010000) {
> /* L=1 form only updates EE and RI */
> TCGv t0 = tcg_temp_new();
> @@ -5419,9 +5325,7 @@ static void gen_mtmsr(DisasContext *ctx)
> CHK_SV;
>
> #if !defined(CONFIG_USER_ONLY)
> - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> - gen_io_start();
> - }
> + gen_icount_io_start(ctx);
> if (ctx->opcode & 0x00010000) {
> /* L=1 form only updates EE and RI */
> TCGv t0 = tcg_temp_new();
>
Sorry, I somehow changed the author by mistake, which must be
From: Richard Henderson <richard.henderson@linaro.org>
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start
2021-05-12 19:21 ` Matheus K. Ferst
@ 2021-05-13 4:14 ` David Gibson
0 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:14 UTC (permalink / raw)
To: Matheus K. Ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 13362 bytes --]
On Wed, May 12, 2021 at 04:21:13PM -0300, Matheus K. Ferst wrote:
> On 12/05/2021 15:54, matheus.ferst@eldorado.org.br wrote:
> > From: Matheus Ferst <matheus.ferst@eldorado.org.br>
> >
> > Create a function to handle the details for interacting with icount.
> >
> > Force the exit from the tb via DISAS_TOO_MANY, which allows chaining
> > to the next tb, where the code emitted for gen_tb_start() will
> > determine if we must exit. We can thus remove any matching
> > conditional call to gen_stop_exception.
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> > ---
> > target/ppc/translate.c | 174 +++++++++--------------------------------
> > 1 file changed, 39 insertions(+), 135 deletions(-)
> >
> > diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> > index 1c02e21a56..f6410dc76c 100644
> > --- a/target/ppc/translate.c
> > +++ b/target/ppc/translate.c
> > @@ -301,6 +301,20 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> > ctx->base.is_jmp = DISAS_NORETURN;
> > }
> > +static void gen_icount_io_start(DisasContext *ctx)
> > +{
> > + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > + gen_io_start();
> > + /*
> > + * An I/O instruction must be last in the TB.
> > + * Chain to the next TB, and let the code from gen_tb_start
> > + * decide if we need to return to the main loop.
> > + * Doing this first also allows this value to be overridden.
> > + */
> > + ctx->base.is_jmp = DISAS_TOO_MANY;
> > + }
> > +}
> > +
> > /*
> > * Tells the caller what is the appropriate exception to generate and prepares
> > * SPR registers for this exception.
> > @@ -538,24 +552,14 @@ static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
> > #if !defined(CONFIG_USER_ONLY)
> > static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > #endif
> > @@ -563,24 +567,14 @@ static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
> > /* Time base */
> > static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > ATTRIBUTE_UNUSED
> > @@ -598,24 +592,14 @@ static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
> > #if !defined(CONFIG_USER_ONLY)
> > static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > ATTRIBUTE_UNUSED
> > @@ -634,80 +618,45 @@ static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
> > ATTRIBUTE_UNUSED
> > static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > /* HDECR */
> > static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > #endif
> > @@ -915,71 +864,41 @@ static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
> > #if !defined(CONFIG_USER_ONLY)
> > static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_store_spr(sprn, cpu_gpr[gprn]);
> > gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
> > /* We must stop translation as we may have rebooted */
> > gen_stop_exception(ctx);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
> > {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > #endif
> > @@ -2863,18 +2782,13 @@ static void gen_darn(DisasContext *ctx)
> > if (l > 2) {
> > tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
> > } else {
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > if (l == 0) {
> > gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
> > } else {
> > /* Return 64-bit random for both CRN and RRN */
> > gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
> > }
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_stop_exception(ctx);
> > - }
> > }
> > }
> > #endif
> > @@ -5016,9 +4930,7 @@ static void gen_rfi(DisasContext *ctx)
> > }
> > /* Restore CPU state */
> > CHK_SV;
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_update_cfar(ctx, ctx->cia);
> > gen_helper_rfi(cpu_env);
> > ctx->base.is_jmp = DISAS_EXIT;
> > @@ -5033,9 +4945,7 @@ static void gen_rfid(DisasContext *ctx)
> > #else
> > /* Restore CPU state */
> > CHK_SV;
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_update_cfar(ctx, ctx->cia);
> > gen_helper_rfid(cpu_env);
> > ctx->base.is_jmp = DISAS_EXIT;
> > @@ -5050,9 +4960,7 @@ static void gen_rfscv(DisasContext *ctx)
> > #else
> > /* Restore CPU state */
> > CHK_SV;
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > gen_update_cfar(ctx, ctx->cia);
> > gen_helper_rfscv(cpu_env);
> > ctx->base.is_jmp = DISAS_EXIT;
> > @@ -5382,9 +5290,7 @@ static void gen_mtmsrd(DisasContext *ctx)
> > CHK_SV;
> > #if !defined(CONFIG_USER_ONLY)
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > if (ctx->opcode & 0x00010000) {
> > /* L=1 form only updates EE and RI */
> > TCGv t0 = tcg_temp_new();
> > @@ -5419,9 +5325,7 @@ static void gen_mtmsr(DisasContext *ctx)
> > CHK_SV;
> > #if !defined(CONFIG_USER_ONLY)
> > - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> > - gen_io_start();
> > - }
> > + gen_icount_io_start(ctx);
> > if (ctx->opcode & 0x00010000) {
> > /* L=1 form only updates EE and RI */
> > TCGv t0 = tcg_temp_new();
> >
>
> Sorry, I somehow changed the author by mistake, which must be
> From: Richard Henderson <richard.henderson@linaro.org>
It turns out this no longer applies cleanly for me on ppc-for-6.1
anyway. Please fix the attribution when you rebase for the next spin.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 11/31] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (9 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 12/31] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
` (20 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Remove the synthetic "exception" after no more uses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
linux-user/ppc/cpu_loop.c | 3 ---
target/ppc/cpu.h | 1 -
target/ppc/translate.c | 24 +++++++-----------------
3 files changed, 7 insertions(+), 21 deletions(-)
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index 4a0f6c8dc2..fe526693d2 100644
--- a/linux-user/ppc/cpu_loop.c
+++ b/linux-user/ppc/cpu_loop.c
@@ -423,9 +423,6 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(cs, "Maintenance exception while in user mode. "
"Aborting\n");
break;
- case POWERPC_EXCP_STOP: /* stop translation */
- /* We did invalidate the instruction cache. Go on */
- break;
case POWERPC_EXCP_BRANCH: /* branch instruction: */
/* We just stopped because of a branch. Go on */
break;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 503de6db85..22456f9a72 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -132,7 +132,6 @@ enum {
/* EOL */
POWERPC_EXCP_NB = 103,
/* QEMU exceptions: used internally during code translation */
- POWERPC_EXCP_STOP = 0x200, /* stop translation */
POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
/* QEMU exceptions: special cases we want to stop translation */
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f6410dc76c..db6f11d632 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -366,13 +366,6 @@ static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
}
-/* Stop translation */
-static inline void gen_stop_exception(DisasContext *ctx)
-{
- gen_update_nip(ctx, ctx->base.pc_next);
- ctx->exception = POWERPC_EXCP_STOP;
-}
-
/*****************************************************************************/
/* SPR READ/WRITE CALLBACKS */
@@ -832,7 +825,7 @@ static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
/* Must stop the translation as endianness may have changed */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
#endif
@@ -880,7 +873,7 @@ static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
gen_store_spr(sprn, cpu_gpr[gprn]);
gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
/* We must stop translation as we may have rebooted */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
@@ -4083,7 +4076,7 @@ static void gen_isync(DisasContext *ctx)
gen_check_tlb_flush(ctx, false);
}
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
@@ -5315,7 +5308,7 @@ static void gen_mtmsrd(DisasContext *ctx)
gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
}
/* Must stop the translation as machine state (may have) changed */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
#endif /* !defined(CONFIG_USER_ONLY) */
}
#endif /* defined(TARGET_PPC64) */
@@ -5358,7 +5351,7 @@ static void gen_mtmsr(DisasContext *ctx)
tcg_temp_free(msr);
}
/* Must stop the translation as machine state (may have) changed */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
#endif
}
@@ -7495,7 +7488,7 @@ static void gen_wrtee(DisasContext *ctx)
* Stop translation to have a chance to raise an exception if we
* just set msr_ee to 1
*/
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -7509,7 +7502,7 @@ static void gen_wrteei(DisasContext *ctx)
if (ctx->opcode & 0x00008000) {
tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
/* Stop translation to have a chance to raise an exception */
- gen_stop_exception(ctx);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
} else {
tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
}
@@ -9319,9 +9312,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
case POWERPC_EXCP_BRANCH:
ctx->base.is_jmp = DISAS_NORETURN;
break;
- case POWERPC_EXCP_STOP:
- ctx->base.is_jmp = DISAS_EXIT;
- break;
default:
/* Every other ctx->exception should have set NORETURN. */
g_assert_not_reached();
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 12/31] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (10 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 11/31] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 13/31] target/ppc: Remove DisasContext.exception matheus.ferst
` (19 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
The translation of branch instructions always results in exit from
the TB. Remove the synthetic "exception" after no more uses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
linux-user/ppc/cpu_loop.c | 3 ---
target/ppc/cpu.h | 2 --
target/ppc/translate.c | 8 ++------
3 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index fe526693d2..fa91ea0eed 100644
--- a/linux-user/ppc/cpu_loop.c
+++ b/linux-user/ppc/cpu_loop.c
@@ -423,9 +423,6 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(cs, "Maintenance exception while in user mode. "
"Aborting\n");
break;
- case POWERPC_EXCP_BRANCH: /* branch instruction: */
- /* We just stopped because of a branch. Go on */
- break;
case POWERPC_EXCP_SYSCALL_USER:
/* system call in user-mode emulation */
/* WARNING:
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 22456f9a72..1c3486e9d0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -131,8 +131,6 @@ enum {
POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
/* EOL */
POWERPC_EXCP_NB = 103,
- /* QEMU exceptions: used internally during code translation */
- POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
/* QEMU exceptions: special cases we want to stop translation */
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
};
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index db6f11d632..43320d2b8b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4695,7 +4695,6 @@ static void gen_b(DisasContext *ctx)
{
target_ulong li, target;
- ctx->exception = POWERPC_EXCP_BRANCH;
/* sign extend LI */
li = LI(ctx->opcode);
li = (li ^ 0x02000000) - 0x02000000;
@@ -4709,6 +4708,7 @@ static void gen_b(DisasContext *ctx)
}
gen_update_cfar(ctx, ctx->cia);
gen_goto_tb(ctx, 0, target);
+ ctx->base.is_jmp = DISAS_NORETURN;
}
#define BCOND_IM 0
@@ -4721,7 +4721,6 @@ static void gen_bcond(DisasContext *ctx, int type)
uint32_t bo = BO(ctx->opcode);
TCGLabel *l1;
TCGv target;
- ctx->exception = POWERPC_EXCP_BRANCH;
if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
target = tcg_temp_local_new();
@@ -4828,6 +4827,7 @@ static void gen_bcond(DisasContext *ctx, int type)
gen_set_label(l1);
gen_goto_tb(ctx, 1, ctx->base.pc_next);
}
+ ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_bc(DisasContext *ctx)
@@ -9293,7 +9293,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
/* Check trace mode exceptions */
if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
(ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
- ctx->exception != POWERPC_EXCP_BRANCH &&
ctx->base.is_jmp != DISAS_NORETURN)) {
uint32_t excp = gen_prep_dbgex(ctx);
gen_exception_nip(ctx, excp, ctx->base.pc_next);
@@ -9309,9 +9308,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
switch (ctx->exception) {
case POWERPC_EXCP_NONE:
break;
- case POWERPC_EXCP_BRANCH:
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
default:
/* Every other ctx->exception should have set NORETURN. */
g_assert_not_reached();
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 13/31] target/ppc: Remove DisasContext.exception
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (11 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 12/31] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 14/31] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
` (18 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Now that we have removed all of the fake exceptions, and all real
exceptions exit via DISAS_NORETURN, we can remove this field.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- Remove the field.
- Changes applied to gen_scv on rebase.
---
target/ppc/translate.c | 30 ++++--------------------------
1 file changed, 4 insertions(+), 26 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 43320d2b8b..606897fa75 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -156,7 +156,6 @@ struct DisasContext {
DisasContextBase base;
target_ulong cia; /* current instruction address */
uint32_t opcode;
- uint32_t exception;
/* Routine used to access memory */
bool pr, hv, dr, le_mode;
bool lazy_tlb_flush;
@@ -258,15 +257,12 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
* These are all synchronous exceptions, we set the PC back to the
* faulting instruction
*/
- if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_update_nip(ctx, ctx->cia);
- }
+ gen_update_nip(ctx, ctx->cia);
t0 = tcg_const_i32(excp);
t1 = tcg_const_i32(error);
gen_helper_raise_exception_err(cpu_env, t0, t1);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
- ctx->exception = excp;
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -278,13 +274,10 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
* These are all synchronous exceptions, we set the PC back to the
* faulting instruction
*/
- if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_update_nip(ctx, ctx->cia);
- }
+ gen_update_nip(ctx, ctx->cia);
t0 = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
- ctx->exception = excp;
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -297,7 +290,6 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
t0 = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
- ctx->exception = excp;
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -4996,13 +4988,10 @@ static void gen_scv(DisasContext *ctx)
uint32_t lev = (ctx->opcode >> 5) & 0x7F;
/* Set the PC back to the faulting instruction. */
- if (ctx->exception == POWERPC_EXCP_NONE) {
- gen_update_nip(ctx, ctx->cia);
- }
+ gen_update_nip(ctx, ctx->cia);
gen_helper_scv(cpu_env, tcg_constant_i32(lev));
- /* This need not be exact, just not POWERPC_EXCP_NONE */
- ctx->exception = POWERPC_SYSCALL_VECTORED;
+ ctx->base.is_jmp = DISAS_NORETURN;
}
#endif
#endif
@@ -9196,7 +9185,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
uint32_t hflags = ctx->base.tb->flags;
int bound;
- ctx->exception = POWERPC_EXCP_NONE;
ctx->spr_cb = env->spr_cb;
ctx->pr = (hflags >> HFLAGS_PR) & 1;
ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7;
@@ -9303,16 +9291,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
"temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
}
-
- if (ctx->base.is_jmp == DISAS_NEXT) {
- switch (ctx->exception) {
- case POWERPC_EXCP_NONE:
- break;
- default:
- /* Every other ctx->exception should have set NORETURN. */
- g_assert_not_reached();
- }
- }
}
static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 14/31] target/ppc: Move single-step check to ppc_tr_tb_stop
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (12 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 13/31] target/ppc: Remove DisasContext.exception matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 15/31] target/ppc: Tidy exception vs exit_tb matheus.ferst
` (17 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
When single-stepping, force max_insns to 1 in init_disas
so that we exit the translation loop immediately.
Combine the single-step checks in tb_stop, and give the
gdb exception priority over the cpu exception, just as
we already do in gen_lookup_and_goto_ptr.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 606897fa75..bfda567ac0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -9183,7 +9183,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUPPCState *env = cs->env_ptr;
uint32_t hflags = ctx->base.tb->flags;
- int bound;
ctx->spr_cb = env->spr_cb;
ctx->pr = (hflags >> HFLAGS_PR) & 1;
@@ -9223,8 +9222,12 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
}
- bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
- ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
+ if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
+ ctx->base.max_insns = 1;
+ } else {
+ int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
+ ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
+ }
}
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
@@ -9278,14 +9281,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
handler->count++;
#endif
- /* Check trace mode exceptions */
- if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
- (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
- ctx->base.is_jmp != DISAS_NORETURN)) {
- uint32_t excp = gen_prep_dbgex(ctx);
- gen_exception_nip(ctx, excp, ctx->base.pc_next);
- }
-
if (tcg_check_temp_count()) {
qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
"temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
@@ -9298,6 +9293,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
DisasJumpType is_jmp = ctx->base.is_jmp;
target_ulong nip = ctx->base.pc_next;
+ int sse;
if (is_jmp == DISAS_NORETURN) {
/* We have already exited the TB. */
@@ -9305,7 +9301,8 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
}
/* Honor single stepping. */
- if (unlikely(ctx->base.singlestep_enabled)) {
+ sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
+ if (unlikely(sse)) {
switch (is_jmp) {
case DISAS_TOO_MANY:
case DISAS_EXIT_UPDATE:
@@ -9318,8 +9315,16 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
default:
g_assert_not_reached();
}
- gen_debug_exception(ctx);
- return;
+
+ if (sse & GDBSTUB_SINGLE_STEP) {
+ gen_debug_exception(ctx);
+ return;
+ }
+ /* else CPU_SINGLE_STEP... */
+ if (nip <= 0x100 || nip > 0xf00) {
+ gen_exception(ctx, gen_prep_dbgex(ctx));
+ return;
+ }
}
switch (is_jmp) {
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 15/31] target/ppc: Tidy exception vs exit_tb
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (13 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 14/31] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 16/31] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
` (16 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
We do not need to emit an exit_tb after an exception,
as the latter will exit via longjmp.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index bfda567ac0..9912686496 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4651,8 +4651,9 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
} else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
uint32_t excp = gen_prep_dbgex(ctx);
gen_exception(ctx, excp);
+ } else {
+ tcg_gen_exit_tb(NULL, 0);
}
- tcg_gen_exit_tb(NULL, 0);
} else {
tcg_gen_lookup_and_goto_ptr();
}
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 16/31] target/ppc: Mark helper_raise_exception* as noreturn
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (14 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 15/31] target/ppc: Tidy exception vs exit_tb matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check matheus.ferst
` (15 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 513066d54d..ea9f2a236c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -1,5 +1,5 @@
-DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, void, env, i32, i32)
-DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, noreturn, env, i32, i32)
+DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
DEF_HELPER_FLAGS_4(tw, TCG_CALL_NO_WG, void, env, tl, tl, i32)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32)
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (15 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 16/31] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 19:45 ` Bruno Piazera Larsen
2021-05-12 18:54 ` [PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions matheus.ferst
` (14 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
The special logging is unnecessary. It will have been done
immediately before in the log file.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9912686496..cd4b34aa91 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -9282,11 +9282,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
handler->count++;
#endif
- if (tcg_check_temp_count()) {
- qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
- "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
- opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
- }
+ translator_loop_temp_check(&ctx->base);
}
static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check
2021-05-12 18:54 ` [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check matheus.ferst
@ 2021-05-12 19:45 ` Bruno Piazera Larsen
0 siblings, 0 replies; 56+ messages in thread
From: Bruno Piazera Larsen @ 2021-05-12 19:45 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, luis.pires, richard.henderson, f4bug, david
[-- Attachment #1: Type: text/plain, Size: 1506 bytes --]
On 12/05/2021 15:54, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> The special logging is unnecessary. It will have been done
> immediately before in the log file.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
> target/ppc/translate.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 9912686496..cd4b34aa91 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -9282,11 +9282,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
> handler->count++;
> #endif
>
> - if (tcg_check_temp_count()) {
> - qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
> - "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
> - opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
> - }
> + translator_loop_temp_check(&ctx->base);
> }
>
> static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
Reviewed-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
[-- Attachment #2: Type: text/html, Size: 2414 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (16 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 19/31] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
` (13 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
These will be used by the decodetree trans_* functions
to early-exit when the instruction set is not enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index cd4b34aa91..153c61e8ec 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7753,6 +7753,32 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
+/*
+ * Helpers for trans_* functions to check for specific insns flags.
+ * Use token pasting to ensure that we use the proper flag with the
+ * proper variable.
+ */
+#define REQUIRE_INSNS_FLAGS(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+/* Then special-case the check for 64-bit so that we elide code for ppc32. */
+#if TARGET_LONG_BITS == 32
+# define REQUIRE_64BIT(CTX) return false
+#else
+# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
+#endif
+
#include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.c.inc"
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 19/31] target/ppc: Move page crossing check to ppc_tr_translate_insn
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (17 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 20/31] target/ppc: Add infrastructure for prefixed insns matheus.ferst
` (12 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
With prefixed instructions, the number of instructions
remaining until the page crossing is no longer constant.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 153c61e8ec..dec2ff1886 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -9251,9 +9251,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
ctx->base.max_insns = 1;
- } else {
- int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
- ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
}
}
@@ -9308,6 +9305,11 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
handler->count++;
#endif
+ /* End the TB when crossing a page boundary. */
+ if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) {
+ ctx->base.is_jmp = DISAS_TOO_MANY;
+ }
+
translator_loop_temp_check(&ctx->base);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 20/31] target/ppc: Add infrastructure for prefixed insns
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (18 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 19/31] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
` (11 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/cpu.h | 1 +
target/ppc/insn32.decode | 18 ++++++++++++
target/ppc/insn64.decode | 18 ++++++++++++
target/ppc/meson.build | 9 ++++++
target/ppc/translate.c | 34 +++++++++++++++++++---
target/ppc/translate/fixedpoint-impl.c.inc | 18 ++++++++++++
6 files changed, 94 insertions(+), 4 deletions(-)
create mode 100644 target/ppc/insn32.decode
create mode 100644 target/ppc/insn64.decode
create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1c3486e9d0..55cd0d0f88 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -144,6 +144,7 @@ enum {
POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
+ POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
/* Exception subtypes for POWERPC_EXCP_PROGRAM */
/* FP exceptions */
POWERPC_EXCP_FP = 0x10,
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
new file mode 100644
index 0000000000..b175441209
--- /dev/null
+++ b/target/ppc/insn32.decode
@@ -0,0 +1,18 @@
+#
+# Power ISA decode for 32-bit insns (opcode space 0)
+#
+# Copyright (c) 2021 Luis Pires <luis.pires@eldorado.org.br>
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+#
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
new file mode 100644
index 0000000000..9fc45d0614
--- /dev/null
+++ b/target/ppc/insn64.decode
@@ -0,0 +1,18 @@
+#
+# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
+#
+# Copyright (c) 2021 Luis Pires <luis.pires@eldorado.org.br>
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+#
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index 4079d01ee3..3ad5986b33 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -16,6 +16,15 @@ ppc_ss.add(files(
ppc_ss.add(libdecnumber)
+gen = [
+ decodetree.process('insn32.decode',
+ extra_args: '--static-decode=decode_insn32'),
+ decodetree.process('insn64.decode',
+ extra_args: ['--static-decode=decode_insn64',
+ '--insnwidth=64']),
+]
+ppc_ss.add(gen)
+
ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index dec2ff1886..64a99ff2c0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7779,6 +7779,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
#endif
+#include "decode-insn32.c.inc"
+#include "decode-insn64.c.inc"
+#include "translate/fixedpoint-impl.c.inc"
+
#include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.c.inc"
@@ -9280,11 +9284,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
return true;
}
+static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ return opc1(insn) == 1;
+}
+
static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = cs->env_ptr;
+ target_ulong pc;
uint32_t insn;
bool ok;
@@ -9292,11 +9303,26 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
- ctx->cia = ctx->base.pc_next;
- insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx));
- ctx->base.pc_next += 4;
+ ctx->cia = pc = ctx->base.pc_next;
+ insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
+ ctx->base.pc_next = pc += 4;
- ok = decode_legacy(cpu, ctx, insn);
+ if (!is_prefix_insn(ctx, insn)) {
+ ok = (decode_insn32(ctx, insn) ||
+ decode_legacy(cpu, ctx, insn));
+ } else if ((pc & 63) == 0) {
+ /*
+ * Power v3.1, section 1.9 Exceptions:
+ * attempt to execute a prefixed instruction that crosses a
+ * 64-byte address boundary (system alignment error).
+ */
+ gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
+ ok = true;
+ } else {
+ uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
+ ctx->base.pc_next = pc += 4;
+ ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
+ }
if (!ok) {
gen_invalid(ctx);
}
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
new file mode 100644
index 0000000000..b740083605
--- /dev/null
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -0,0 +1,18 @@
+/*
+ * Power ISA decode for Fixed-Point Facility instructions
+ *
+ * Copyright (c) 2021 Luis Pires <luis.pires@eldorado.org.br>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (19 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 20/31] target/ppc: Add infrastructure for prefixed insns matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 22/31] target/ppc: Implement PNOP matheus.ferst
` (10 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- addi and paddi unfolded, so that addi can use @D and @PLS_D is declared only
in insn64.decode;
- Reuse trans_ADDI in trans_ADDIS.
---
target/ppc/insn32.decode | 8 ++++
target/ppc/insn64.decode | 12 ++++++
target/ppc/translate.c | 29 --------------
target/ppc/translate/fixedpoint-impl.c.inc | 44 ++++++++++++++++++++++
4 files changed, 64 insertions(+), 29 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b175441209..d93ae905a4 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -16,3 +16,11 @@
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
+
+&D rt ra si:int64_t
+@D ...... rt:5 ra:5 si:s16 &D
+
+### Fixed-Point Arithmetic Instructions
+
+ADDI 001110 ..... ..... ................ @D
+ADDIS 001111 ..... ..... ................ @D
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 9fc45d0614..5e6c96a326 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -16,3 +16,15 @@
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
+
+# Format MLS:D and 8LS:D
+&PLS_D rt ra si:int64_t r:bool
+%pls_si 32:s18 0:16
+@PLS_D ...... .. ... r:1 .. .................. \
+ ...... rt:5 ra:5 ................ \
+ &PLS_D si=%pls_si
+
+### Fixed-Point Arithmetic Instructions
+
+PADDI 000001 10 0--.-- .................. \
+ 001110 ..... ..... ................ @PLS_D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 64a99ff2c0..7f2ebcb442 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1849,19 +1849,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
/* addze addze. addzeo addzeo.*/
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
-/* addi */
-static void gen_addi(DisasContext *ctx)
-{
- target_long simm = SIMM(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- /* li case */
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
- } else {
- tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], simm);
- }
-}
/* addic addic.*/
static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
{
@@ -1881,20 +1868,6 @@ static void gen_addic_(DisasContext *ctx)
gen_op_addic(ctx, 1);
}
-/* addis */
-static void gen_addis(DisasContext *ctx)
-{
- target_long simm = SIMM(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- /* lis case */
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
- } else {
- tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], simm << 16);
- }
-}
-
/* addpcis */
static void gen_addpcis(DisasContext *ctx)
{
@@ -7906,10 +7879,8 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
-GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index b740083605..b7ee0ff034 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -16,3 +16,47 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
+/*
+ * Incorporate CIA into the constant when R=1.
+ * Validate that when R=1, RA=0.
+ */
+static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
+{
+ d->rt = a->rt;
+ d->ra = a->ra;
+ d->si = a->si;
+ if (a->r) {
+ if (unlikely(a->ra != 0)) {
+ gen_invalid(ctx);
+ return false;
+ }
+ d->si += ctx->cia;
+ }
+ return true;
+}
+
+static bool trans_ADDI(DisasContext *ctx, arg_D *a)
+{
+ if (a->ra) {
+ tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si);
+ } else {
+ tcg_gen_movi_tl(cpu_gpr[a->rt], a->si);
+ }
+ return true;
+}
+
+static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return trans_ADDI(ctx, &d);
+}
+
+static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
+{
+ a->si <<= 16;
+ return trans_ADDI(ctx, a);
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 22/31] target/ppc: Implement PNOP
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (20 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 10:37 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 23/31] TCG: add tcg_constant_tl matheus.ferst
` (9 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
The illegal suffix behavior matches what was observed in a
POWER10 DD2.0 machine.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- Detect illegal suffixes and call gen_invalid.
---
target/ppc/insn64.decode | 66 ++++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 8 +++
2 files changed, 74 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 5e6c96a326..56857b5e93 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -28,3 +28,69 @@
PADDI 000001 10 0--.-- .................. \
001110 ..... ..... ................ @PLS_D
+
+### Prefixed No-operation Instruction
+
+&PNOP invalid_suffix:bool
+@PNOP 000001 11 0000-- 000000000000000000 \
+ ................................ &PNOP
+
+{
+ ## Invalid suffixes: Branch instruction
+ # bc[l][a]
+ PNOP ................................ \
+ 010000-------------------------- @PNOP invalid_suffix=1
+ # b[l][a]
+ PNOP ................................ \
+ 010010-------------------------- @PNOP invalid_suffix=1
+ # bclr[l]
+ PNOP ................................ \
+ 010011---------------0000010000- @PNOP invalid_suffix=1
+ # bcctr[l]
+ PNOP ................................ \
+ 010011---------------1000010000- @PNOP invalid_suffix=1
+ # bctar[l]
+ PNOP ................................ \
+ 010011---------------1000110000- @PNOP invalid_suffix=1
+
+ ## Invalid suffixes: rfebb
+ PNOP ................................ \
+ 010011---------------0010010010- @PNOP invalid_suffix=1
+
+ ## Invalid suffixes: context synchronizing other than isync
+ # sc
+ PNOP ................................ \
+ 010001------------------------1- @PNOP invalid_suffix=1
+ # scv
+ PNOP ................................ \
+ 010001------------------------01 @PNOP invalid_suffix=1
+ # rfscv
+ PNOP ................................ \
+ 010011---------------0001010010- @PNOP invalid_suffix=1
+ # rfid
+ PNOP ................................ \
+ 010011---------------0000010010- @PNOP invalid_suffix=1
+ # hrfid
+ PNOP ................................ \
+ 010011---------------0100010010- @PNOP invalid_suffix=1
+ # urfid
+ PNOP ................................ \
+ 010011---------------0100110010- @PNOP invalid_suffix=1
+ # stop
+ PNOP ................................ \
+ 010011---------------0101110010- @PNOP invalid_suffix=1
+ # mtmsr w/ L=0
+ PNOP ................................ \
+ 011111---------0-----0010010010- @PNOP invalid_suffix=1
+ # mtmsrd w/ L=0
+ PNOP ................................ \
+ 011111---------0-----0010110010- @PNOP invalid_suffix=1
+
+ ## Invalid suffixes: Service Processor Attention
+ PNOP ................................ \
+ 000000----------------100000000- @PNOP invalid_suffix=1
+
+ ## Valid suffixes
+ PNOP ................................ \
+ -------------------------------- @PNOP invalid_suffix=0
+}
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index b7ee0ff034..9a8da29c64 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -60,3 +60,11 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
a->si <<= 16;
return trans_ADDI(ctx, a);
}
+
+static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
+{
+ if (a->invalid_suffix) {
+ gen_invalid(ctx);
+ }
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 22/31] target/ppc: Implement PNOP
2021-05-12 18:54 ` [PATCH v4 22/31] target/ppc: Implement PNOP matheus.ferst
@ 2021-05-13 10:37 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2021-05-13 10:37 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote:
> +### Prefixed No-operation Instruction
> +
> +&PNOP invalid_suffix:bool
> +@PNOP 000001 11 0000-- 000000000000000000 \
> + ................................ &PNOP
> +
> +{
> + ## Invalid suffixes: Branch instruction
> + # bc[l][a]
> + PNOP ................................ \
> + 010000-------------------------- @PNOP invalid_suffix=1
For other cpus it has often turned out to be helpful to have a trans_INVALID or
UNDEF or RESERVED or suchlike to use for cases like this. That way you don't
need a special argument set, nor to set a flag as you do for each of these.
Also, the invalid suffixes themselves do not overlap, so you can get a slightly
better decode via nested [], like so:
{
[
INVALID ...
INVALID ...
...
]
NOP ...
}
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 23/31] TCG: add tcg_constant_tl
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (21 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 22/31] target/ppc: Implement PNOP matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 10:42 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 24/31] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
` (8 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Used in D/DS/X-form load/store implementation.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
include/tcg/tcg-op.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 2cd1faf9c4..ef8a008ea7 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -1096,6 +1096,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
#define tcg_gen_extract2_tl tcg_gen_extract2_i64
#define tcg_const_tl tcg_const_i64
+#define tcg_constant_tl tcg_constant_i64
#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
#define tcg_gen_add2_tl tcg_gen_add2_i64
@@ -1209,6 +1210,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
#define tcg_gen_extract2_tl tcg_gen_extract2_i32
#define tcg_const_tl tcg_const_i32
+#define tcg_constant_tl tcg_constant_i32
#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
#define tcg_gen_add2_tl tcg_gen_add2_i32
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 23/31] TCG: add tcg_constant_tl
2021-05-12 18:54 ` [PATCH v4 23/31] TCG: add tcg_constant_tl matheus.ferst
@ 2021-05-13 10:42 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2021-05-13 10:42 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst<matheus.ferst@eldorado.org.br>
>
> Used in D/DS/X-form load/store implementation.
>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> include/tcg/tcg-op.h | 2 ++
> 1 file changed, 2 insertions(+)
Ah, thanks. Queuing to tcg-next.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 24/31] target/ppc: Move D/DS/X-form integer loads to decodetree
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (22 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 23/31] TCG: add tcg_constant_tl matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions matheus.ferst
` (7 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
These are all connected by macros in the legacy decoding.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- Common code of do_ldst_D and do_ldst_X moved to do_ldst;
- @D{,S} instead of @PLS_D{,S} for non-prefixed loads;
- do_ldst_PLS_D moved to the next patch.
---
target/ppc/insn32.decode | 37 ++++++
target/ppc/translate.c | 147 ++++-----------------
target/ppc/translate/fixedpoint-impl.c.inc | 89 +++++++++++++
3 files changed, 150 insertions(+), 123 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d93ae905a4..860b96d866 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -20,6 +20,43 @@
&D rt ra si:int64_t
@D ...... rt:5 ra:5 si:s16 &D
+%ds_si 2:s14 !function=times_4
+@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+
+&X rt ra rb
+@X ...... rt:5 ra:5 rb:5 .......... . &X
+
+### Fixed-Point Load Instructions
+
+LBZ 100010 ..... ..... ................ @D
+LBZU 100011 ..... ..... ................ @D
+LBZX 011111 ..... ..... ..... 0001010111 - @X
+LBZUX 011111 ..... ..... ..... 0001110111 - @X
+
+LHZ 101000 ..... ..... ................ @D
+LHZU 101001 ..... ..... ................ @D
+LHZX 011111 ..... ..... ..... 0100010111 - @X
+LHZUX 011111 ..... ..... ..... 0100110111 - @X
+
+LHA 101010 ..... ..... ................ @D
+LHAU 101011 ..... ..... ................ @D
+LHAX 011111 ..... ..... ..... 0101010111 - @X
+LHAXU 011111 ..... ..... ..... 0101110111 - @X
+
+LWZ 100000 ..... ..... ................ @D
+LWZU 100001 ..... ..... ................ @D
+LWZX 011111 ..... ..... ..... 0000010111 - @X
+LWZUX 011111 ..... ..... ..... 0000110111 - @X
+
+LWA 111010 ..... ..... ..............10 @DS
+LWAX 011111 ..... ..... ..... 0101010101 - @X
+LWAUX 011111 ..... ..... ..... 0101110101 - @X
+
+LD 111010 ..... ..... ..............00 @DS
+LDU 111010 ..... ..... ..............01 @DS
+LDX 011111 ..... ..... ..... 0000010101 - @X
+LDUX 011111 ..... ..... ..... 0000110101 - @X
+
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 7f2ebcb442..32d217071b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3412,54 +3412,6 @@ GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
#endif
-#define GEN_LD(name, ldop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_LDU(name, ldop, opc, type) \
-static void glue(gen_, name##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0 || \
- rA(ctx->opcode) == rD(ctx->opcode))) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (type == PPC_64B) \
- gen_addr_imm_index(ctx, EA, 0x03); \
- else \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_LDUX(name, ldop, opc2, opc3, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0 || \
- rA(ctx->opcode) == rD(ctx->opcode))) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
@@ -3478,21 +3430,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
#define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
-#define GEN_LDS(name, ldop, op, type) \
-GEN_LD(name, ldop, op | 0x20, type); \
-GEN_LDU(name, ldop, op | 0x21, type); \
-GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
-GEN_LDX(name, ldop, 0x17, op | 0x00, type)
-
-/* lbz lbzu lbzux lbzx */
-GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
-/* lha lhau lhaux lhax */
-GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
-/* lhz lhzu lhzux lhzx */
-GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
-/* lwz lwzu lwzux lwzx */
-GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
-
#define GEN_LDEPX(name, ldop, opc2, opc3) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
@@ -3513,47 +3450,12 @@ GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
#endif
#if defined(TARGET_PPC64)
-/* lwaux */
-GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
-/* lwax */
-GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
-/* ldux */
-GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
-/* ldx */
-GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
-
/* CI load/store variants */
GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
-static void gen_ld(DisasContext *ctx)
-{
- TCGv EA;
- if (Rc(ctx->opcode)) {
- if (unlikely(rA(ctx->opcode) == 0 ||
- rA(ctx->opcode) == rD(ctx->opcode))) {
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- return;
- }
- }
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0x03);
- if (ctx->opcode & 0x02) {
- /* lwa (lwau is undefined) */
- gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
- } else {
- /* ld - ldu */
- gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
- }
- if (Rc(ctx->opcode)) {
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
- }
- tcg_temp_free(EA);
-}
-
/* lq */
static void gen_lq(DisasContext *ctx)
{
@@ -7726,6 +7628,14 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
+/*
+ * Helpers for decodetree used by !function for decoding arguments.
+ */
+static int times_4(DisasContext *ctx, int x)
+{
+ return x * 4;
+}
+
/*
* Helpers for trans_* functions to check for specific insns flags.
* Use token pasting to ensure that we use the proper flag with the
@@ -7752,6 +7662,21 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
#endif
+/*
+ * Helpers for implementing sets of trans_* functions.
+ * Defer the implementation of NAME to FUNC, with optional extra arguments.
+ */
+#define TRANS(NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { return FUNC(ctx, a, __VA_ARGS__); }
+
+#define TRANS64(NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
+
+/* TODO: More TRANS* helpers for extra insn_flags checks. */
+
+
#include "decode-insn32.c.inc"
#include "decode-insn64.c.inc"
#include "translate/fixedpoint-impl.c.inc"
@@ -7936,7 +7861,6 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
PPC_NONE, PPC2_ISA300),
#endif
#if defined(TARGET_PPC64)
-GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
#endif
@@ -8302,34 +8226,11 @@ GEN_PPC64_R2(rldcr, 0x1E, 0x09),
GEN_PPC64_R4(rldimi, 0x1E, 0x06),
#endif
-#undef GEN_LD
-#undef GEN_LDU
-#undef GEN_LDUX
#undef GEN_LDX_E
-#undef GEN_LDS
-#define GEN_LD(name, ldop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDU(name, ldop, opc, type) \
-GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_LDUX(name, ldop, opc2, opc3, type) \
-GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
-#define GEN_LDS(name, ldop, op, type) \
-GEN_LD(name, ldop, op | 0x20, type) \
-GEN_LDU(name, ldop, op | 0x21, type) \
-GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
-GEN_LDX(name, ldop, 0x17, op | 0x00, type)
-
-GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
-GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
-GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
-GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
+
#if defined(TARGET_PPC64)
-GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
-GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
-GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
-GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
/* HV/P7 and later only */
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 9a8da29c64..4c3eff6979 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -36,6 +36,95 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
return true;
}
+/*
+ * Fixed-Point Load/Store Instructions
+ */
+
+static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update,
+ bool store, MemOp mop)
+{
+ TCGv ea;
+
+ if (update && (ra == 0 || (!store && ra == rt))) {
+ gen_invalid(ctx);
+ return true;
+ }
+ gen_set_access_type(ctx, ACCESS_INT);
+
+ ea = tcg_temp_new();
+ if (ra) {
+ tcg_gen_add_tl(ea, cpu_gpr[ra], displ);
+ } else {
+ tcg_gen_mov_tl(ea, displ);
+ }
+ if (NARROW_MODE(ctx)) {
+ tcg_gen_ext32u_tl(ea, ea);
+ }
+ mop ^= ctx->default_tcg_memop_mask;
+ if (store) {
+ tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+ }
+ if (update) {
+ tcg_gen_mov_tl(cpu_gpr[ra], ea);
+ }
+ tcg_temp_free(ea);
+
+ return true;
+}
+
+static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
+ MemOp mop)
+{
+ return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
+}
+
+static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
+ bool store, MemOp mop)
+{
+ return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
+}
+
+/* Load Byte and Zero */
+TRANS(LBZ, do_ldst_D, false, false, MO_UB)
+TRANS(LBZX, do_ldst_X, false, false, MO_UB)
+TRANS(LBZU, do_ldst_D, true, false, MO_UB)
+TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
+
+/* Load Halfword and Zero */
+TRANS(LHZ, do_ldst_D, false, false, MO_UW)
+TRANS(LHZX, do_ldst_X, false, false, MO_UW)
+TRANS(LHZU, do_ldst_D, true, false, MO_UW)
+TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
+
+/* Load Halfword Algebraic */
+TRANS(LHA, do_ldst_D, false, false, MO_SW)
+TRANS(LHAX, do_ldst_X, false, false, MO_SW)
+TRANS(LHAU, do_ldst_D, true, false, MO_SW)
+TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
+
+/* Load Word and Zero */
+TRANS(LWZ, do_ldst_D, false, false, MO_UL)
+TRANS(LWZX, do_ldst_X, false, false, MO_UL)
+TRANS(LWZU, do_ldst_D, true, false, MO_UL)
+TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
+
+/* Load Word Algebraic */
+TRANS64(LWA, do_ldst_D, false, false, MO_SL)
+TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
+TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
+
+/* Load Doubleword */
+TRANS64(LD, do_ldst_D, false, false, MO_Q)
+TRANS64(LDX, do_ldst_X, false, false, MO_Q)
+TRANS64(LDU, do_ldst_D, true, false, MO_Q)
+TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
+
+/*
+ * Fixed-Point Arithmetic Instructions
+ */
+
static bool trans_ADDI(DisasContext *ctx, arg_D *a)
{
if (a->ra) {
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (23 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 24/31] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 10:50 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 26/31] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
` (6 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- prefixed and non-prefixed loads unfolded.
---
target/ppc/insn64.decode | 15 +++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 16 ++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 56857b5e93..0c8264a194 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -24,6 +24,21 @@
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
+### Fixed-Point Load Instructions
+
+PLBZ 000001 10 0--.-- .................. \
+ 100010 ..... ..... ................ @PLS_D
+PLHZ 000001 10 0--.-- .................. \
+ 101000 ..... ..... ................ @PLS_D
+PLHA 000001 10 0--.-- .................. \
+ 101010 ..... ..... ................ @PLS_D
+PLWZ 000001 10 0--.-- .................. \
+ 100000 ..... ..... ................ @PLS_D
+PLWA 000001 00 0--.-- .................. \
+ 101001 ..... ..... ................ @PLS_D
+PLD 000001 00 0--.-- .................. \
+ 111001 ..... ..... ................ @PLS_D
+
### Fixed-Point Arithmetic Instructions
PADDI 000001 10 0--.-- .................. \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 4c3eff6979..67291e0b75 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -80,6 +80,16 @@ static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
}
+static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update,
+ bool store, MemOp mop)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return do_ldst_D(ctx, &d, update, store, mop);
+}
+
static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update,
bool store, MemOp mop)
{
@@ -91,35 +101,41 @@ TRANS(LBZ, do_ldst_D, false, false, MO_UB)
TRANS(LBZX, do_ldst_X, false, false, MO_UB)
TRANS(LBZU, do_ldst_D, true, false, MO_UB)
TRANS(LBZUX, do_ldst_X, true, false, MO_UB)
+TRANS(PLBZ, do_ldst_PLS_D, false, false, MO_UB)
/* Load Halfword and Zero */
TRANS(LHZ, do_ldst_D, false, false, MO_UW)
TRANS(LHZX, do_ldst_X, false, false, MO_UW)
TRANS(LHZU, do_ldst_D, true, false, MO_UW)
TRANS(LHZUX, do_ldst_X, true, false, MO_UW)
+TRANS(PLHZ, do_ldst_PLS_D, false, false, MO_UW)
/* Load Halfword Algebraic */
TRANS(LHA, do_ldst_D, false, false, MO_SW)
TRANS(LHAX, do_ldst_X, false, false, MO_SW)
TRANS(LHAU, do_ldst_D, true, false, MO_SW)
TRANS(LHAXU, do_ldst_X, true, false, MO_SW)
+TRANS(PLHA, do_ldst_PLS_D, false, false, MO_SW)
/* Load Word and Zero */
TRANS(LWZ, do_ldst_D, false, false, MO_UL)
TRANS(LWZX, do_ldst_X, false, false, MO_UL)
TRANS(LWZU, do_ldst_D, true, false, MO_UL)
TRANS(LWZUX, do_ldst_X, true, false, MO_UL)
+TRANS(PLWZ, do_ldst_PLS_D, false, false, MO_UL)
/* Load Word Algebraic */
TRANS64(LWA, do_ldst_D, false, false, MO_SL)
TRANS64(LWAX, do_ldst_X, false, false, MO_SL)
TRANS64(LWAUX, do_ldst_X, true, false, MO_SL)
+TRANS64(PLWA, do_ldst_PLS_D, false, false, MO_SL)
/* Load Doubleword */
TRANS64(LD, do_ldst_D, false, false, MO_Q)
TRANS64(LDX, do_ldst_X, false, false, MO_Q)
TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
+TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
/*
* Fixed-Point Arithmetic Instructions
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 26/31] target/ppc: Move D/DS/X-form integer stores to decodetree
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (24 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 27/31] target/ppc: Implement prefixed integer store instructions matheus.ferst
` (5 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
These are all connected by macros in the legacy decoding.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- @D{,S} instead of @PLS_D{,S} for non-prefixed stores;
---
target/ppc/insn32.decode | 22 ++++++
target/ppc/translate.c | 85 +---------------------
target/ppc/translate/fixedpoint-impl.c.inc | 24 ++++++
3 files changed, 49 insertions(+), 82 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 860b96d866..8460100177 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -57,6 +57,28 @@ LDU 111010 ..... ..... ..............01 @DS
LDX 011111 ..... ..... ..... 0000010101 - @X
LDUX 011111 ..... ..... ..... 0000110101 - @X
+### Fixed-Point Store Instructions
+
+STB 100110 ..... ..... ................ @D
+STBU 100111 ..... ..... ................ @D
+STBX 011111 ..... ..... ..... 0011010111 - @X
+STBUX 011111 ..... ..... ..... 0011110111 - @X
+
+STH 101100 ..... ..... ................ @D
+STHU 101101 ..... ..... ................ @D
+STHX 011111 ..... ..... ..... 0110010111 - @X
+STHUX 011111 ..... ..... ..... 0110110111 - @X
+
+STW 100100 ..... ..... ................ @D
+STWU 100101 ..... ..... ................ @D
+STWX 011111 ..... ..... ..... 0010010111 - @X
+STWUX 011111 ..... ..... ..... 0010110111 - @X
+
+STD 111110 ..... ..... ..............00 @DS
+STDU 111110 ..... ..... ..............01 @DS
+STDX 011111 ..... ..... ..... 0010010101 - @X
+STDUX 011111 ..... ..... ..... 0010110101 - @X
+
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 32d217071b..477e3deede 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3388,7 +3388,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, \
tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
}
+#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
+#endif
GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
@@ -3521,52 +3523,6 @@ static void gen_lq(DisasContext *ctx)
#endif
/*** Integer store ***/
-#define GEN_ST(name, stop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_STU(name, stop, opc, type) \
-static void glue(gen_, stop##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (type == PPC_64B) \
- gen_addr_imm_index(ctx, EA, 0x03); \
- else \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_STUX(name, stop, opc2, opc3, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
@@ -3584,19 +3540,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
#define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
-#define GEN_STS(name, stop, op, type) \
-GEN_ST(name, stop, op | 0x20, type); \
-GEN_STU(name, stop, op | 0x21, type); \
-GEN_STUX(name, stop, 0x17, op | 0x01, type); \
-GEN_STX(name, stop, 0x17, op | 0x00, type)
-
-/* stb stbu stbux stbx */
-GEN_STS(stb, st8, 0x06, PPC_INTEGER);
-/* sth sthu sthux sthx */
-GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
-/* stw stwu stwux stwx */
-GEN_STS(stw, st32, 0x04, PPC_INTEGER);
-
#define GEN_STEPX(name, stop, opc2, opc3) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
@@ -3618,8 +3561,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
#endif
#if defined(TARGET_PPC64)
-GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
-GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
@@ -8255,31 +8196,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
#endif
-#undef GEN_ST
-#undef GEN_STU
-#undef GEN_STUX
#undef GEN_STX_E
-#undef GEN_STS
-#define GEN_ST(name, stop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STU(name, stop, opc, type) \
-GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUX(name, stop, opc2, opc3, type) \
-GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
-#define GEN_STS(name, stop, op, type) \
-GEN_ST(name, stop, op | 0x20, type) \
-GEN_STU(name, stop, op | 0x21, type) \
-GEN_STUX(name, stop, 0x17, op | 0x01, type) \
-GEN_STX(name, stop, 0x17, op | 0x00, type)
-
-GEN_STS(stb, st8, 0x06, PPC_INTEGER)
-GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
-GEN_STS(stw, st32, 0x04, PPC_INTEGER)
+
#if defined(TARGET_PPC64)
-GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
-GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 67291e0b75..7fec0a8595 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -137,6 +137,30 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
+/* Store Byte */
+TRANS(STB, do_ldst_D, false, true, MO_UB)
+TRANS(STBX, do_ldst_X, false, true, MO_UB)
+TRANS(STBU, do_ldst_D, true, true, MO_UB)
+TRANS(STBUX, do_ldst_X, true, true, MO_UB)
+
+/* Store Halfword */
+TRANS(STH, do_ldst_D, false, true, MO_UW)
+TRANS(STHX, do_ldst_X, false, true, MO_UW)
+TRANS(STHU, do_ldst_D, true, true, MO_UW)
+TRANS(STHUX, do_ldst_X, true, true, MO_UW)
+
+/* Store Word */
+TRANS(STW, do_ldst_D, false, true, MO_UL)
+TRANS(STWX, do_ldst_X, false, true, MO_UL)
+TRANS(STWU, do_ldst_D, true, true, MO_UL)
+TRANS(STWUX, do_ldst_X, true, true, MO_UL)
+
+/* Store Doubleword */
+TRANS64(STD, do_ldst_D, false, true, MO_Q)
+TRANS64(STDX, do_ldst_X, false, true, MO_Q)
+TRANS64(STDU, do_ldst_D, true, true, MO_Q)
+TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
+
/*
* Fixed-Point Arithmetic Instructions
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 27/31] target/ppc: Implement prefixed integer store instructions
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (25 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 26/31] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-12 18:54 ` [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
` (4 subsequent siblings)
31 siblings, 0 replies; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- prefixed and non-prefixed stores unfolded.
---
target/ppc/insn64.decode | 12 ++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 4 ++++
2 files changed, 16 insertions(+)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 0c8264a194..b68b0074f4 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -39,6 +39,18 @@ PLWA 000001 00 0--.-- .................. \
PLD 000001 00 0--.-- .................. \
111001 ..... ..... ................ @PLS_D
+### Fixed-Point Store Instructions
+
+PSTW 000001 10 0--.-- .................. \
+ 100100 ..... ..... ................ @PLS_D
+PSTB 000001 10 0--.-- .................. \
+ 100110 ..... ..... ................ @PLS_D
+PSTH 000001 10 0--.-- .................. \
+ 101100 ..... ..... ................ @PLS_D
+
+PSTD 000001 00 0--.-- .................. \
+ 111101 ..... ..... ................ @PLS_D
+
### Fixed-Point Arithmetic Instructions
PADDI 000001 10 0--.-- .................. \
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 7fec0a8595..04a974214f 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -142,24 +142,28 @@ TRANS(STB, do_ldst_D, false, true, MO_UB)
TRANS(STBX, do_ldst_X, false, true, MO_UB)
TRANS(STBU, do_ldst_D, true, true, MO_UB)
TRANS(STBUX, do_ldst_X, true, true, MO_UB)
+TRANS(PSTB, do_ldst_PLS_D, false, true, MO_UB)
/* Store Halfword */
TRANS(STH, do_ldst_D, false, true, MO_UW)
TRANS(STHX, do_ldst_X, false, true, MO_UW)
TRANS(STHU, do_ldst_D, true, true, MO_UW)
TRANS(STHUX, do_ldst_X, true, true, MO_UW)
+TRANS(PSTH, do_ldst_PLS_D, false, true, MO_UW)
/* Store Word */
TRANS(STW, do_ldst_D, false, true, MO_UL)
TRANS(STWX, do_ldst_X, false, true, MO_UL)
TRANS(STWU, do_ldst_D, true, true, MO_UL)
TRANS(STWUX, do_ldst_X, true, true, MO_UL)
+TRANS(PSTW, do_ldst_PLS_D, false, true, MO_UL)
/* Store Doubleword */
TRANS64(STD, do_ldst_D, false, true, MO_Q)
TRANS64(STDX, do_ldst_X, false, true, MO_Q)
TRANS64(STDU, do_ldst_D, true, true, MO_Q)
TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
+TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
/*
* Fixed-Point Arithmetic Instructions
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (26 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 27/31] target/ppc: Implement prefixed integer store instructions matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 11:01 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 29/31] target/ppc: Implement cfuged instruction matheus.ferst
` (3 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
setbc: Set Boolean Condition
setbcr: Set Boolean Condition Reverse
setnbc: Set Negative Boolean Condition
setnbcr: Set Negative Boolean Condition Reverse
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 10 ++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 21 +++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 8460100177..d69c0bc14c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -26,6 +26,9 @@
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
+&X_bi rt bi
+@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -83,3 +86,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+
+### Move To/From System Register Instructions
+
+SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
+SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
+SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
+SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 04a974214f..37dd25148c 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -201,3 +201,24 @@ static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
}
return true;
}
+
+static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ uint32_t mask = 0x08 >> (a->bi & 0x03);
+ TCGv temp = tcg_temp_new();
+
+ tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
+ tcg_gen_andi_tl(temp, temp, mask);
+ tcg_gen_movcond_tl(a->r?TCG_COND_EQ:TCG_COND_NE, cpu_gpr[a->rt], temp,
+ tcg_constant_tl(0), tcg_constant_tl(a->n?-1:1),
+ tcg_constant_tl(0));
+ tcg_temp_free(temp);
+
+ return true;
+}
+
+TRANS(SETBC, do_set_bool_cond, false, false)
+TRANS(SETBCR, do_set_bool_cond, false, true)
+TRANS(SETNBC, do_set_bool_cond, true, false)
+TRANS(SETNBCR, do_set_bool_cond, true, true)
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
2021-05-12 18:54 ` [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
@ 2021-05-13 11:01 ` Richard Henderson
2021-05-13 11:43 ` Matheus K. Ferst
0 siblings, 1 reply; 56+ messages in thread
From: Richard Henderson @ 2021-05-13 11:01 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote:
> +static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev)
> +{
> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> + uint32_t mask = 0x08 >> (a->bi & 0x03);
> + TCGv temp = tcg_temp_new();
> +
> + tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
> + tcg_gen_andi_tl(temp, temp, mask);
> + tcg_gen_movcond_tl(a->r?TCG_COND_EQ:TCG_COND_NE, cpu_gpr[a->rt], temp,
> + tcg_constant_tl(0), tcg_constant_tl(a->n?-1:1),
> + tcg_constant_tl(0));
Mind the spacing around ?:.
Did you forget to update a->r and a->n to "neg" and "rev"?
It sure looks like this doesn't compile...
I guess this is fine with movcond, but perhaps slightly better with
tcg_gen_setcondi_tl(cond, rt, temp, 0);
if (neg) {
tcg_gen_neg_tl(rt, rt);
}
TCG isn't the most optimizing of compilers...
r~
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
2021-05-13 11:01 ` Richard Henderson
@ 2021-05-13 11:43 ` Matheus K. Ferst
0 siblings, 0 replies; 56+ messages in thread
From: Matheus K. Ferst @ 2021-05-13 11:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 13/05/2021 08:01, Richard Henderson wrote:
> On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote:
>> +static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool
>> neg, bool rev)
>> +{
>> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
>> + uint32_t mask = 0x08 >> (a->bi & 0x03);
>> + TCGv temp = tcg_temp_new();
>> +
>> + tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
>> + tcg_gen_andi_tl(temp, temp, mask);
>> + tcg_gen_movcond_tl(a->r?TCG_COND_EQ:TCG_COND_NE, cpu_gpr[a->rt],
>> temp,
>> + tcg_constant_tl(0), tcg_constant_tl(a->n?-1:1),
>> + tcg_constant_tl(0));
>
> Mind the spacing around ?:.
>
Fixed.
> Did you forget to update a->r and a->n to "neg" and "rev"?
> It sure looks like this doesn't compile...
>
I messed up when rebasing, the change is in the next patch. I'll fix
that too.
> I guess this is fine with movcond, but perhaps slightly better with
>
> tcg_gen_setcondi_tl(cond, rt, temp, 0);
> if (neg) {
> tcg_gen_neg_tl(rt, rt);
> }
>
> TCG isn't the most optimizing of compilers...
>
>
> r~
And also looks cleaner, I'll apply that too.
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 29/31] target/ppc: Implement cfuged instruction
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (27 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 11:31 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 30/31] target/ppc: Implement vcfuged instruction matheus.ferst
` (2 subsequent siblings)
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 +++
target/ppc/int_helper.c | 39 ++++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 16 +++++++--
4 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ea9f2a236c..c517b9f025 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -46,6 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
+DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d69c0bc14c..64788e2a4b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -87,6 +87,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+## Fixed-Point Logical Instructions
+
+CFUGED 011111 ..... ..... ..... 0011011100 - @X
+
### Move To/From System Register Instructions
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index a44c2d90ea..d1cfb915ae 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -320,6 +320,45 @@ target_ulong helper_popcntb(target_ulong val)
}
#endif
+uint64_t helper_cfuged(uint64_t src, uint64_t mask)
+{
+ target_ulong m, left = 0, right = 0;
+ unsigned int n, i = 64;
+ bool bit = 0;
+
+ if (mask == 0 || mask == -1) {
+ return src;
+ }
+
+ while (i) {
+ n = ctz64(mask);
+ if (n > i) {
+ n = i;
+ }
+
+ m = (1ll << n) - 1;
+ if (bit) {
+ right = ror64(right | (src & m), n);
+ } else {
+ left = ror64(left | (src & m), n);
+ }
+
+ src >>= n;
+ mask >>= n;
+ i -= n;
+ bit = !bit;
+ mask = ~mask;
+ }
+
+ if (bit) {
+ n = ctpop64(mask);
+ } else {
+ n = 64 - ctpop64(mask);
+ }
+
+ return left | (right >> n);
+}
+
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 37dd25148c..4617f7356b 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -210,8 +210,8 @@ static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev)
tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
tcg_gen_andi_tl(temp, temp, mask);
- tcg_gen_movcond_tl(a->r?TCG_COND_EQ:TCG_COND_NE, cpu_gpr[a->rt], temp,
- tcg_constant_tl(0), tcg_constant_tl(a->n?-1:1),
+ tcg_gen_movcond_tl(rev?TCG_COND_EQ:TCG_COND_NE, cpu_gpr[a->rt], temp,
+ tcg_constant_tl(0), tcg_constant_tl(neg?-1:1),
tcg_constant_tl(0));
tcg_temp_free(temp);
@@ -222,3 +222,15 @@ TRANS(SETBC, do_set_bool_cond, false, false)
TRANS(SETBCR, do_set_bool_cond, false, true)
TRANS(SETNBC, do_set_bool_cond, true, false)
TRANS(SETNBCR, do_set_bool_cond, true, true)
+
+static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ gen_invalid(ctx);
+#endif
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 29/31] target/ppc: Implement cfuged instruction
2021-05-12 18:54 ` [PATCH v4 29/31] target/ppc: Implement cfuged instruction matheus.ferst
@ 2021-05-13 11:31 ` Richard Henderson
2021-05-13 12:24 ` Matheus K. Ferst
0 siblings, 1 reply; 56+ messages in thread
From: Richard Henderson @ 2021-05-13 11:31 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote:
> + while (i) {
> + n = ctz64(mask);
> + if (n > i) {
> + n = i;
> + }
> +
> + m = (1ll << n) - 1;
> + if (bit) {
> + right = ror64(right | (src & m), n);
> + } else {
> + left = ror64(left | (src & m), n);
> + }
> +
> + src >>= n;
> + mask >>= n;
> + i -= n;
> + bit = !bit;
> + mask = ~mask;
> + }
> +
> + if (bit) {
> + n = ctpop64(mask);
> + } else {
> + n = 64 - ctpop64(mask);
> + }
> +
> + return left | (right >> n);
> +}
This doesn't correspond to the algorithm presented in the manual. Thus this
requires lots of extra commentary.
I guess I see how you're trying to process blocks at a time, instead of single
bits at a time. But I don't think the merging of data into "right" and "left"
looks right. I would have expected
right = (right << n) | (src & m);
and similarly for left.
It doesn't look like that the ctpop at the end is correct, given how mask has
been modified. I would have thought that
n = ctpop64(orig_mask);
return (left << n) | right;
would be the correct answer.
I could be wrong about the above, but that's what the missing commentary should
have helped me understand.
> +static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> +#if defined(TARGET_PPC64)
> + gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
> +#else
> + gen_invalid(ctx);
> +#endif
> + return true;
> +}
Given that this helper will also be used by vcfuged, there's no point in hiding
it in a TARGET_PPC64 block, and thus you can drop the ifdefs.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v4 29/31] target/ppc: Implement cfuged instruction
2021-05-13 11:31 ` Richard Henderson
@ 2021-05-13 12:24 ` Matheus K. Ferst
2021-05-14 0:01 ` Richard Henderson
0 siblings, 1 reply; 56+ messages in thread
From: Matheus K. Ferst @ 2021-05-13 12:24 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 13/05/2021 08:31, Richard Henderson wrote:
> On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote:
>> + while (i) {
>> + n = ctz64(mask);
>> + if (n > i) {
>> + n = i;
>> + }
>> +
>> + m = (1ll << n) - 1;
>> + if (bit) {
>> + right = ror64(right | (src & m), n);
>> + } else {
>> + left = ror64(left | (src & m), n);
>> + }
>> +
>> + src >>= n;
>> + mask >>= n;
>> + i -= n;
>> + bit = !bit;
>> + mask = ~mask;
>> + }
>> +
>> + if (bit) {
>> + n = ctpop64(mask);
>> + } else {
>> + n = 64 - ctpop64(mask);
>> + }
>> +
>> + return left | (right >> n);
>> +}
>
> This doesn't correspond to the algorithm presented in the manual. Thus
> this requires lots of extra commentary.
>
> I guess I see how you're trying to process blocks at a time, instead of
> single bits at a time. But I don't think the merging of data into
> "right" and "left" looks right. I would have expected
>
> right = (right << n) | (src & m);
>
> and similarly for left.
>
> It doesn't look like that the ctpop at the end is correct, given how
> mask has been modified. I would have thought that
>
> n = ctpop64(orig_mask);
> return (left << n) | right;
>
> would be the correct answer.
>
> I could be wrong about the above, but that's what the missing commentary
> should have helped me understand.
>
It sure worth more comments. Yes, the idea is to process in blocks, and
we negate the mask to avoid deciding between ctz and cto inside the
loop. We use rotate instead of shift so it don't change the number of
zeros and ones, and then we don't need orig_mask.
You'll find my test cases for cfuged and vcfuged on
https://github.com/PPC64/qemu/blob/ferst-tcg-cfuged/tests/tcg/ppc64le/ .
I got the same results by running them with this implementation and with
the Power10 Functional Simulator.
>> +static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
>> +{
>> + REQUIRE_64BIT(ctx);
>> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
>> +#if defined(TARGET_PPC64)
>> + gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
>> +#else
>> + gen_invalid(ctx);
>> +#endif
>> + return true;
>> +}
>
> Given that this helper will also be used by vcfuged, there's no point in
> hiding it in a TARGET_PPC64 block, and thus you can drop the ifdefs.
>
>
> r~
>
If I remove it, the build for ppc will fail, because cpu_gpr is declared
as TCGv, and the helper uses i64 to match {get,set}_cpu_vsr{l,h}.
REQUIRE_64BIT makes the helper call unreachable for ppc, but it's a
runtime check. At build time, the compiler will check the types anyway,
and give us an error.
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v4 29/31] target/ppc: Implement cfuged instruction
2021-05-13 12:24 ` Matheus K. Ferst
@ 2021-05-14 0:01 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2021-05-14 0:01 UTC (permalink / raw)
To: Matheus K. Ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/13/21 7:24 AM, Matheus K. Ferst wrote:
>>> +static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
>>> +{
>>> + REQUIRE_64BIT(ctx);
>>> + REQUIRE_INSNS_FLAGS2(ctx, ISA310);
>>> +#if defined(TARGET_PPC64)
>>> + gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
>>> +#else
>>> + gen_invalid(ctx);
>>> +#endif
>>> + return true;
>>> +}
>>
>> Given that this helper will also be used by vcfuged, there's no point in
>> hiding it in a TARGET_PPC64 block, and thus you can drop the ifdefs.
>>
>>
>> r~
>>
>
> If I remove it, the build for ppc will fail, because cpu_gpr is declared as
> TCGv, and the helper uses i64 to match {get,set}_cpu_vsr{l,h}. REQUIRE_64BIT
> makes the helper call unreachable for ppc, but it's a runtime check. At build
> time, the compiler will check the types anyway, and give us an error.
Hmm, yes. Just change the gen_invalid above to qemu_build_not_reached().
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 30/31] target/ppc: Implement vcfuged instruction
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (28 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 29/31] target/ppc: Implement cfuged instruction matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 11:36 ` Richard Henderson
2021-05-12 18:54 ` [PATCH v4 31/31] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-13 4:22 ` [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions David Gibson
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 7 ++++
target/ppc/translate.c | 1 +
target/ppc/translate/vector-impl.c.inc | 50 ++++++++++++++++++++++++++
3 files changed, 58 insertions(+)
create mode 100644 target/ppc/translate/vector-impl.c.inc
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 64788e2a4b..73b5ea0422 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -23,6 +23,9 @@
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+&VX vrt vra vrb
+@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
@@ -97,3 +100,7 @@ SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
+
+## Vector Bit Manipulation Instruction
+
+VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 477e3deede..847de8e012 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7627,6 +7627,7 @@ static int times_4(DisasContext *ctx, int x)
#include "translate/vmx-impl.c.inc"
#include "translate/vsx-impl.c.inc"
+#include "translate/vector-impl.c.inc"
#include "translate/dfp-impl.c.inc"
diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
new file mode 100644
index 0000000000..4e07de5671
--- /dev/null
+++ b/target/ppc/translate/vector-impl.c.inc
@@ -0,0 +1,50 @@
+/*
+ * Power ISA decode for Vector Facility instructions
+ *
+ * Copyright (c) 2021 Matheus Ferst <matheus.ferst@eldorado.org.br>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 tgt, src, mask;
+
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return true;
+ }
+
+ tgt = tcg_temp_new_i64();
+ src = tcg_temp_new_i64();
+ mask = tcg_temp_new_i64();
+
+ // centrifuge lower double word
+ get_cpu_vsrl(src, a->vra+32);
+ get_cpu_vsrl(mask, a->vrb+32);
+ gen_helper_cfuged(tgt, src, mask);
+ set_cpu_vsrl(a->vrt+32, tgt);
+
+ // centrifuge higher double word
+ get_cpu_vsrh(src, a->vra+32);
+ get_cpu_vsrh(mask, a->vrb+32);
+ gen_helper_cfuged(tgt, src, mask);
+ set_cpu_vsrh(a->vrt+32, tgt);
+
+ tcg_temp_free_i64(tgt);
+ tcg_temp_free_i64(src);
+ tcg_temp_free_i64(mask);
+
+ return true;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 30/31] target/ppc: Implement vcfuged instruction
2021-05-12 18:54 ` [PATCH v4 30/31] target/ppc: Implement vcfuged instruction matheus.ferst
@ 2021-05-13 11:36 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2021-05-13 11:36 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
> target/ppc/insn32.decode | 7 ++++
> target/ppc/translate.c | 1 +
> target/ppc/translate/vector-impl.c.inc | 50 ++++++++++++++++++++++++++
> 3 files changed, 58 insertions(+)
> create mode 100644 target/ppc/translate/vector-impl.c.inc
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 64788e2a4b..73b5ea0422 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -23,6 +23,9 @@
> %ds_si 2:s14 !function=times_4
> @DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
>
> +&VX vrt vra vrb
> +@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
> +
> &X rt ra rb
> @X ...... rt:5 ra:5 rb:5 .......... . &X
>
> @@ -97,3 +100,7 @@ SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
> SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
> SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
> SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
> +
> +## Vector Bit Manipulation Instruction
> +
> +VCFUGED 000100 ..... ..... ..... 10101001101 @VX
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 477e3deede..847de8e012 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7627,6 +7627,7 @@ static int times_4(DisasContext *ctx, int x)
> #include "translate/vmx-impl.c.inc"
>
> #include "translate/vsx-impl.c.inc"
> +#include "translate/vector-impl.c.inc"
>
> #include "translate/dfp-impl.c.inc"
>
> diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc
> new file mode 100644
> index 0000000000..4e07de5671
> --- /dev/null
> +++ b/target/ppc/translate/vector-impl.c.inc
> @@ -0,0 +1,50 @@
> +/*
> + * Power ISA decode for Vector Facility instructions
> + *
> + * Copyright (c) 2021 Matheus Ferst <matheus.ferst@eldorado.org.br>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
> +{
> + TCGv_i64 tgt, src, mask;
> +
> + if (unlikely(!ctx->altivec_enabled)) {
> + gen_exception(ctx, POWERPC_EXCP_VPU);
> + return true;
> + }
You have to REQUIRE_INSN_FLAGS(something) before checking for altivec_enabled.
You're going to want to create some boilerplate for this, because it's going to
get repeated a *lot*.
> + // centrifuge lower double word
> + get_cpu_vsrl(src, a->vra+32);
> + get_cpu_vsrl(mask, a->vrb+32);
> + gen_helper_cfuged(tgt, src, mask);
> + set_cpu_vsrl(a->vrt+32, tgt);
> +
> + // centrifuge higher double word
> + get_cpu_vsrh(src, a->vra+32);
> + get_cpu_vsrh(mask, a->vrb+32);
> + gen_helper_cfuged(tgt, src, mask);
> + set_cpu_vsrh(a->vrt+32, tgt);
This has multiple checkpatch errors.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v4 31/31] target/ppc: Move addpcis to decodetree
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (29 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 30/31] target/ppc: Implement vcfuged instruction matheus.ferst
@ 2021-05-12 18:54 ` matheus.ferst
2021-05-13 11:40 ` Richard Henderson
2021-05-13 4:22 ` [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions David Gibson
31 siblings, 1 reply; 56+ messages in thread
From: matheus.ferst @ 2021-05-12 18:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: richard.henderson, f4bug, luis.pires, lagarcia, bruno.larsen,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 6 ++++++
target/ppc/translate.c | 9 ---------
target/ppc/translate/fixedpoint-impl.c.inc | 7 +++++++
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 73b5ea0422..a827d0bdee 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -23,6 +23,10 @@
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+&DX rt d
+%dx_d 6:s10 16:5 0:1
+@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
@@ -90,6 +94,8 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+ADDPCIS 010011 ..... ..... .......... 00010 . @DX
+
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 847de8e012..26368cf402 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1868,14 +1868,6 @@ static void gen_addic_(DisasContext *ctx)
gen_op_addic(ctx, 1);
}
-/* addpcis */
-static void gen_addpcis(DisasContext *ctx)
-{
- target_long d = DX(ctx->opcode);
-
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
-}
-
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
{
@@ -7748,7 +7740,6 @@ GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 4617f7356b..5e13a67af3 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -194,6 +194,13 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
return trans_ADDI(ctx, a);
}
+static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d<<16));
+ return true;
+}
+
static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
{
if (a->invalid_suffix) {
--
2.25.1
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v4 31/31] target/ppc: Move addpcis to decodetree
2021-05-12 18:54 ` [PATCH v4 31/31] target/ppc: Move addpcis to decodetree matheus.ferst
@ 2021-05-13 11:40 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2021-05-13 11:40 UTC (permalink / raw)
To: matheus.ferst, qemu-devel, qemu-ppc
Cc: lagarcia, bruno.larsen, luis.pires, f4bug, david
On 5/12/21 1:54 PM, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst<matheus.ferst@eldorado.org.br>
>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> target/ppc/insn32.decode | 6 ++++++
> target/ppc/translate.c | 9 ---------
> target/ppc/translate/fixedpoint-impl.c.inc | 7 +++++++
> 3 files changed, 13 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions
2021-05-12 18:54 [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions matheus.ferst
` (30 preceding siblings ...)
2021-05-12 18:54 ` [PATCH v4 31/31] target/ppc: Move addpcis to decodetree matheus.ferst
@ 2021-05-13 4:22 ` David Gibson
31 siblings, 0 replies; 56+ messages in thread
From: David Gibson @ 2021-05-13 4:22 UTC (permalink / raw)
To: matheus.ferst
Cc: richard.henderson, qemu-devel, f4bug, luis.pires, qemu-ppc,
lagarcia, bruno.larsen
[-- Attachment #1: Type: text/plain, Size: 4500 bytes --]
On Wed, May 12, 2021 at 03:54:10PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> This series provides the basic infrastructure for adding the new 32/64-bit
> instructions in Power ISA 3.1 to target/ppc.
I've applied the first chunk of these. After that I get conflicts
with my current ppc-for-6.1 tree. I suspect those are conflicts with
the !TCG changes I recently applied as well.
In any case, please rebase the remainder and resend.
>
> v4:
> - Rebase on ppc-for-6.1;
> - Fold do_ldst_D and do_ldst_X;
> - Add tcg_const_tl, used to share do_ldst_D and do_ldst_X code;
> - Unfold prefixed and non-prefixed loads/stores/addi to let non-prefixed insns use the non-prefixed formats;
> - PNOP invalid suffixes;
> - setbc/setbcr/stnbc/setnbcr implemented;
> - cfuged/vcfuged implemented;
> - addpcis moved to decodetree.
>
> v3:
> - More changes for decodetree.
> - Cleanup exception/is_jmp logic to the point exception is removed.
> - Fold in Luis' isa check for prefixed insn support.
> - Share trans_* between prefixed and non-prefixed instructions.
> - Use macros to minimize the trans_* boilerplate.
> - Fix decode mistake for STHX/STHXU.
>
> v2:
> - Store current pc in ctx instead of insn_size
> - Use separate decode files for 32- and 64-bit instructions
> - Improvements to the exception/is_jmp logic
> - Use translator_loop_temp_check()
> - Moved logic to prevent translation from crossing page boundaries
> - Additional instructions using decodetree: addis, pnop, loads/stores
> - Added check for prefixed insn support in cpu flags
>
> Matheus Ferst (6):
> target/ppc: Introduce gen_icount_io_start
> TCG: add tcg_constant_tl
> target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
> target/ppc: Implement cfuged instruction
> target/ppc: Implement vcfuged instruction
> target/ppc: Move addpcis to decodetree
>
> Richard Henderson (25):
> target/ppc: Add cia field to DisasContext
> target/ppc: Split out decode_legacy
> target/ppc: Move DISAS_NORETURN setting into gen_exception*
> target/ppc: Remove special case for POWERPC_SYSCALL
> target/ppc: Remove special case for POWERPC_EXCP_TRAP
> target/ppc: Simplify gen_debug_exception
> target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE}
> target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT
> target/ppc: Remove unnecessary gen_io_end calls
> target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE
> target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN
> target/ppc: Remove DisasContext.exception
> target/ppc: Move single-step check to ppc_tr_tb_stop
> target/ppc: Tidy exception vs exit_tb
> target/ppc: Mark helper_raise_exception* as noreturn
> target/ppc: Use translator_loop_temp_check
> target/ppc: Introduce macros to check isa extensions
> target/ppc: Move page crossing check to ppc_tr_translate_insn
> target/ppc: Add infrastructure for prefixed insns
> target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
> target/ppc: Implement PNOP
> target/ppc: Move D/DS/X-form integer loads to decodetree
> target/ppc: Implement prefixed integer load instructions
> target/ppc: Move D/DS/X-form integer stores to decodetree
> target/ppc: Implement prefixed integer store instructions
>
> include/tcg/tcg-op.h | 2 +
> linux-user/ppc/cpu_loop.c | 6 -
> target/ppc/cpu.h | 5 +-
> target/ppc/helper.h | 5 +-
> target/ppc/insn32.decode | 112 +++
> target/ppc/insn64.decode | 123 +++
> target/ppc/int_helper.c | 39 +
> target/ppc/meson.build | 9 +
> target/ppc/translate.c | 829 ++++++++-------------
> target/ppc/translate/fixedpoint-impl.c.inc | 243 ++++++
> target/ppc/translate/vector-impl.c.inc | 50 ++
> 11 files changed, 877 insertions(+), 546 deletions(-)
> create mode 100644 target/ppc/insn32.decode
> create mode 100644 target/ppc/insn64.decode
> create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
> create mode 100644 target/ppc/translate/vector-impl.c.inc
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 56+ messages in thread