From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 8/9] target/arm: Enable FPSCR.QC bit for MVE
Date: Thu, 20 May 2021 16:28:39 +0100 [thread overview]
Message-ID: <20210520152840.24453-9-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210520152840.24453-1-peter.maydell@linaro.org>
MVE has an FPSCR.QC bit similar to the A-profile Neon one;
when MVE is implemented make the bit writeable.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/vfp_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index e0886ab5a56..11e1e087e81 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -220,7 +220,8 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
FPCR_LTPSIZE_LENGTH);
}
- if (arm_feature(env, ARM_FEATURE_NEON)) {
+ if (arm_feature(env, ARM_FEATURE_NEON) ||
+ cpu_isar_feature(aa32_mve, cpu)) {
/*
* The bit we set within fpscr_q is arbitrary; the register as a
* whole being zero/non-zero is what counts.
--
2.20.1
next prev parent reply other threads:[~2021-05-20 15:40 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 15:28 [PATCH 0/9] target/arm: MVE preliminaries Peter Maydell
2021-05-20 15:28 ` [PATCH 1/9] target/arm: Add isar feature check functions for MVE Peter Maydell
2021-05-24 15:21 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 2/9] target/arm: Update feature checks for insns which are "MVE or FP" Peter Maydell
2021-05-24 15:32 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 3/9] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp Peter Maydell
2021-05-24 16:24 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 4/9] target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp Peter Maydell
2021-05-24 16:31 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 5/9] target/arm: Fix return values in fp_sysreg_checks() Peter Maydell
2021-05-24 16:36 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 6/9] target/arm: Implement M-profile VPR register Peter Maydell
2021-05-24 16:51 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 7/9] target/arm: Make FPSCR.LTPSIZE writable for MVE Peter Maydell
2021-05-24 16:56 ` Richard Henderson
2021-05-20 15:28 ` Peter Maydell [this message]
2021-05-24 16:59 ` [PATCH 8/9] target/arm: Enable FPSCR.QC bit " Richard Henderson
2021-05-24 17:08 ` Peter Maydell
2021-05-20 15:28 ` [PATCH 9/9] target/arm: Allow board models to specify initial NS VTOR Peter Maydell
2021-05-24 17:05 ` Richard Henderson
2021-05-20 15:45 ` [PATCH 0/9] target/arm: MVE preliminaries no-reply
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