From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org, groug@kaod.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
David Gibson <david@gibson.dropbear.id.au>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
Matheus Ferst <matheus.ferst@eldorado.org.br>
Subject: [PULL 35/42] target/ppc: Move D/DS/X-form integer stores to decodetree
Date: Thu, 3 Jun 2021 18:22:24 +1000 [thread overview]
Message-ID: <20210603082231.601214-36-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20210603082231.601214-1-david@gibson.dropbear.id.au>
From: Richard Henderson <richard.henderson@linaro.org>
These are all connected by macros in the legacy decoding.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210601193528.2533031-9-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/insn32.decode | 22 ++++++
target/ppc/translate.c | 85 +---------------------
target/ppc/translate/fixedpoint-impl.c.inc | 24 ++++++
3 files changed, 49 insertions(+), 82 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 70f64c235b..00ec0f4328 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -57,6 +57,28 @@ LDU 111010 ..... ..... ..............01 @DS
LDX 011111 ..... ..... ..... 0000010101 - @X
LDUX 011111 ..... ..... ..... 0000110101 - @X
+### Fixed-Point Store Instructions
+
+STB 100110 ..... ..... ................ @D
+STBU 100111 ..... ..... ................ @D
+STBX 011111 ..... ..... ..... 0011010111 - @X
+STBUX 011111 ..... ..... ..... 0011110111 - @X
+
+STH 101100 ..... ..... ................ @D
+STHU 101101 ..... ..... ................ @D
+STHX 011111 ..... ..... ..... 0110010111 - @X
+STHUX 011111 ..... ..... ..... 0110110111 - @X
+
+STW 100100 ..... ..... ................ @D
+STWU 100101 ..... ..... ................ @D
+STWX 011111 ..... ..... ..... 0010010111 - @X
+STWUX 011111 ..... ..... ..... 0010110111 - @X
+
+STD 111110 ..... ..... ..............00 @DS
+STDU 111110 ..... ..... ..............01 @DS
+STDX 011111 ..... ..... ..... 0010010101 - @X
+STDUX 011111 ..... ..... ..... 0010110101 - @X
+
### Fixed-Point Arithmetic Instructions
ADDI 001110 ..... ..... ................ @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d9238d1d10..3c3cb1b664 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3299,7 +3299,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, \
tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
}
+#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
+#endif
GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
@@ -3432,52 +3434,6 @@ static void gen_lq(DisasContext *ctx)
#endif
/*** Integer store ***/
-#define GEN_ST(name, stop, opc, type) \
-static void glue(gen_, name)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_STU(name, stop, opc, type) \
-static void glue(gen_, stop##u)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- if (type == PPC_64B) \
- gen_addr_imm_index(ctx, EA, 0x03); \
- else \
- gen_addr_imm_index(ctx, EA, 0); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
-#define GEN_STUX(name, stop, opc2, opc3, type) \
-static void glue(gen_, name##ux)(DisasContext *ctx) \
-{ \
- TCGv EA; \
- if (unlikely(rA(ctx->opcode) == 0)) { \
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
- return; \
- } \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_reg_index(ctx, EA); \
- gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
- tcg_temp_free(EA); \
-}
-
#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
@@ -3495,19 +3451,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
#define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
-#define GEN_STS(name, stop, op, type) \
-GEN_ST(name, stop, op | 0x20, type); \
-GEN_STU(name, stop, op | 0x21, type); \
-GEN_STUX(name, stop, 0x17, op | 0x01, type); \
-GEN_STX(name, stop, 0x17, op | 0x00, type)
-
-/* stb stbu stbux stbx */
-GEN_STS(stb, st8, 0x06, PPC_INTEGER);
-/* sth sthu sthux sthx */
-GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
-/* stw stwu stwux stwx */
-GEN_STS(stw, st32, 0x04, PPC_INTEGER);
-
#define GEN_STEPX(name, stop, opc2, opc3) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
@@ -3529,8 +3472,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
#endif
#if defined(TARGET_PPC64)
-GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
-GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
@@ -8166,31 +8107,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
#endif
-#undef GEN_ST
-#undef GEN_STU
-#undef GEN_STUX
#undef GEN_STX_E
-#undef GEN_STS
-#define GEN_ST(name, stop, opc, type) \
-GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STU(name, stop, opc, type) \
-GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
-#define GEN_STUX(name, stop, opc2, opc3, type) \
-GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
-#define GEN_STS(name, stop, op, type) \
-GEN_ST(name, stop, op | 0x20, type) \
-GEN_STU(name, stop, op | 0x21, type) \
-GEN_STUX(name, stop, 0x17, op | 0x01, type) \
-GEN_STX(name, stop, 0x17, op | 0x00, type)
-
-GEN_STS(stb, st8, 0x06, PPC_INTEGER)
-GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
-GEN_STS(stw, st32, 0x04, PPC_INTEGER)
+
#if defined(TARGET_PPC64)
-GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
-GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 7687f31d6f..adeee33289 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -137,6 +137,30 @@ TRANS64(LDU, do_ldst_D, true, false, MO_Q)
TRANS64(LDUX, do_ldst_X, true, false, MO_Q)
TRANS64(PLD, do_ldst_PLS_D, false, false, MO_Q)
+/* Store Byte */
+TRANS(STB, do_ldst_D, false, true, MO_UB)
+TRANS(STBX, do_ldst_X, false, true, MO_UB)
+TRANS(STBU, do_ldst_D, true, true, MO_UB)
+TRANS(STBUX, do_ldst_X, true, true, MO_UB)
+
+/* Store Halfword */
+TRANS(STH, do_ldst_D, false, true, MO_UW)
+TRANS(STHX, do_ldst_X, false, true, MO_UW)
+TRANS(STHU, do_ldst_D, true, true, MO_UW)
+TRANS(STHUX, do_ldst_X, true, true, MO_UW)
+
+/* Store Word */
+TRANS(STW, do_ldst_D, false, true, MO_UL)
+TRANS(STWX, do_ldst_X, false, true, MO_UL)
+TRANS(STWU, do_ldst_D, true, true, MO_UL)
+TRANS(STWUX, do_ldst_X, true, true, MO_UL)
+
+/* Store Doubleword */
+TRANS64(STD, do_ldst_D, false, true, MO_Q)
+TRANS64(STDX, do_ldst_X, false, true, MO_Q)
+TRANS64(STDU, do_ldst_D, true, true, MO_Q)
+TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
+
/*
* Fixed-Point Arithmetic Instructions
*/
--
2.31.1
next prev parent reply other threads:[~2021-06-03 8:41 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-03 8:21 [PULL 00/42] ppc-for-6.1 queue 20210603 David Gibson
2021-06-03 8:21 ` [PULL 01/42] target/ppc: cleaned error_report from ppc_store_sdr1 David Gibson
2021-06-03 8:21 ` [PULL 02/42] target/ppc: moved ppc_store_lpcr and ppc_store_msr to cpu.c David Gibson
2021-06-03 8:21 ` [PULL 03/42] target/ppc: reduce usage of fpscr_set_rounding_mode David Gibson
2021-06-03 8:21 ` [PULL 04/42] target/ppc: removed unnecessary inclusion of helper-proto.h David Gibson
2021-06-03 8:21 ` [PULL 05/42] spapr: Don't hijack current_machine->boot_order David Gibson
2021-06-03 8:21 ` [PULL 06/42] spapr: Fix EEH capability issue on KVM guest for PCI passthru David Gibson
2021-06-03 8:21 ` [PULL 07/42] spapr: nvdimm: Forward declare and move the definitions David Gibson
2021-06-03 8:21 ` [PULL 08/42] spapr: nvdimm: Fix the persistent-memory root node name in device tree David Gibson
2021-06-03 8:21 ` [PULL 09/42] target/ppc: fold ppc_store_ptcr into it's only caller David Gibson
2021-06-03 8:21 ` [PULL 10/42] spapr: Remove stale comment about power-saving LPCR bits David Gibson
2021-06-03 8:22 ` [PULL 11/42] spapr: Set LPCR to current AIL mode when starting a new CPU David Gibson
2021-06-03 8:22 ` [PULL 12/42] target/ppc: used ternary operator when registering MAS David Gibson
2021-06-03 8:22 ` [PULL 13/42] target/ppc: added ifdefs around TCG-only code David Gibson
2021-06-03 8:22 ` [PULL 14/42] target/ppc: created tcg-stub.c file David Gibson
2021-06-03 8:22 ` [PULL 15/42] target/ppc: updated meson.build to support disable-tcg David Gibson
2021-06-03 8:22 ` [PULL 16/42] target/ppc: remove ppc_cpu_dump_statistics David Gibson
2021-06-03 8:22 ` [PULL 17/42] target/ppc: removed mentions to DO_PPC_STATISTICS David Gibson
2021-06-03 8:22 ` [PULL 18/42] monitor: removed cpustats command David Gibson
2021-06-03 8:22 ` [PULL 19/42] ppc/pef.c: initialize cgs->ready in kvmppc_svm_init() David Gibson
2021-06-03 8:22 ` [PULL 20/42] hw/core/cpu: removed cpu_dump_statistics function David Gibson
2021-06-03 8:22 ` [PULL 21/42] HMP: added info cpustats to removed_features.rst David Gibson
2021-06-03 8:22 ` [PULL 22/42] target/ppc: removed GEN_OPCODE decision tree David Gibson
2021-06-03 8:22 ` [PULL 23/42] target/ppc: removed all mentions to PPC_DUMP_CPU David Gibson
2021-06-03 8:22 ` [PULL 24/42] target/ppc: overhauled and moved logic of storing fpscr David Gibson
2021-06-03 8:22 ` [PULL 25/42] target/ppc: powerpc_excp: Move lpes code to where it is used David Gibson
2021-06-03 8:22 ` [PULL 26/42] target/ppc: powerpc_excp: Remove dump_syscall_vectored David Gibson
2021-06-03 8:22 ` [PULL 27/42] target/ppc: powerpc_excp: Consolidade TLB miss code David Gibson
2021-06-03 8:22 ` [PULL 28/42] target/ppc: Introduce macros to check isa extensions David Gibson
2021-06-03 8:22 ` [PULL 29/42] target/ppc: Move page crossing check to ppc_tr_translate_insn David Gibson
2021-06-03 8:22 ` [PULL 30/42] target/ppc: Add infrastructure for prefixed insns David Gibson
2021-06-03 8:22 ` [PULL 31/42] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI David Gibson
2021-06-03 8:22 ` [PULL 32/42] target/ppc: Implement PNOP David Gibson
2021-06-03 8:22 ` [PULL 33/42] target/ppc: Move D/DS/X-form integer loads to decodetree David Gibson
2021-06-03 8:22 ` [PULL 34/42] target/ppc: Implement prefixed integer load instructions David Gibson
2021-06-03 8:22 ` David Gibson [this message]
2021-06-03 8:22 ` [PULL 36/42] target/ppc: Implement prefixed integer store instructions David Gibson
2021-06-03 8:22 ` [PULL 37/42] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions David Gibson
2021-06-03 8:22 ` [PULL 38/42] target/ppc: Implement cfuged instruction David Gibson
2021-06-03 8:22 ` [PULL 39/42] target/ppc: Implement vcfuged instruction David Gibson
2021-06-03 8:22 ` [PULL 40/42] target/ppc: Move addpcis to decodetree David Gibson
2021-06-03 8:22 ` [PULL 41/42] target/ppc: Move cmp/cmpi/cmpl/cmpli " David Gibson
2021-06-03 8:22 ` [PULL 42/42] target/ppc: fix single-step exception regression David Gibson
2021-06-03 9:01 ` [PULL 00/42] ppc-for-6.1 queue 20210603 no-reply
2021-06-03 10:36 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210603082231.601214-36-david@gibson.dropbear.id.au \
--to=david@gibson.dropbear.id.au \
--cc=groug@kaod.org \
--cc=matheus.ferst@eldorado.org.br \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).