From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, richard.henderson@linaro.org,
bin.meng@windriver.com,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions
Date: Thu, 10 Jun 2021 15:58:42 +0800 [thread overview]
Message-ID: <20210610075908.3305506-12-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com>
There are 11 instructions, including signed or unsigned
minimum, maximum, clip value, absolute value, and leading
zero, leading one count instructions.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode | 11 ++
target/riscv/insn_trans/trans_rvp.c.inc | 41 ++++++
target/riscv/packed_helper.c | 158 ++++++++++++++++++++++++
4 files changed, 221 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 4d0918b9a9..88035aafad 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1232,3 +1232,14 @@ DEF_HELPER_3(umul8, i64, env, tl, tl)
DEF_HELPER_3(umulx8, i64, env, tl, tl)
DEF_HELPER_3(khm8, tl, env, tl, tl)
DEF_HELPER_3(khmx8, tl, env, tl, tl)
+
+DEF_HELPER_3(smin16, tl, env, tl, tl)
+DEF_HELPER_3(umin16, tl, env, tl, tl)
+DEF_HELPER_3(smax16, tl, env, tl, tl)
+DEF_HELPER_3(umax16, tl, env, tl, tl)
+DEF_HELPER_3(sclip16, tl, env, tl, tl)
+DEF_HELPER_3(uclip16, tl, env, tl, tl)
+DEF_HELPER_2(kabs16, tl, env, tl)
+DEF_HELPER_2(clrs16, tl, env, tl)
+DEF_HELPER_2(clz16, tl, env, tl)
+DEF_HELPER_2(clo16, tl, env, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 05c3e67477..847c796874 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -835,3 +835,14 @@ umul8 1011100 ..... ..... 000 ..... 1110111 @r
umulx8 1011101 ..... ..... 000 ..... 1110111 @r
khm8 1000111 ..... ..... 000 ..... 1110111 @r
khmx8 1001111 ..... ..... 000 ..... 1110111 @r
+
+smin16 1000000 ..... ..... 000 ..... 1110111 @r
+umin16 1001000 ..... ..... 000 ..... 1110111 @r
+smax16 1000001 ..... ..... 000 ..... 1110111 @r
+umax16 1001001 ..... ..... 000 ..... 1110111 @r
+sclip16 1000010 0.... ..... 000 ..... 1110111 @sh4
+uclip16 1000010 1.... ..... 000 ..... 1110111 @sh4
+kabs16 1010110 10001 ..... 000 ..... 1110111 @r2
+clrs16 1010111 01000 ..... 000 ..... 1110111 @r2
+clz16 1010111 01001 ..... 000 ..... 1110111 @r2
+clo16 1010111 01011 ..... 000 ..... 1110111 @r2
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index 2188de8505..3e6307cdc3 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -294,3 +294,44 @@ GEN_RVP_R_D64_OOL(umul8);
GEN_RVP_R_D64_OOL(umulx8);
GEN_RVP_R_OOL(khm8);
GEN_RVP_R_OOL(khmx8);
+
+/* SIMD 16-bit Miscellaneous Instructions */
+GEN_RVP_R_OOL(smin16);
+GEN_RVP_R_OOL(umin16);
+GEN_RVP_R_OOL(smax16);
+GEN_RVP_R_OOL(umax16);
+GEN_RVP_SHIFTI(sclip16, NULL, gen_helper_sclip16);
+GEN_RVP_SHIFTI(uclip16, NULL, gen_helper_uclip16);
+
+/* Out of line helpers for R2 format */
+static bool
+r2_ool(DisasContext *ctx, arg_r2 *a,
+ void (* fn)(TCGv, TCGv_ptr, TCGv))
+{
+ TCGv src1, dst;
+ if (!has_ext(ctx, RVP)) {
+ return false;
+ }
+
+ src1 = tcg_temp_new();
+ dst = tcg_temp_new();
+
+ gen_get_gpr(src1, a->rs1);
+ fn(dst, cpu_env, src1);
+ gen_set_gpr(a->rd, dst);
+
+ tcg_temp_free(src1);
+ tcg_temp_free(dst);
+ return true;
+}
+
+#define GEN_RVP_R2_OOL(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_r2 *a) \
+{ \
+ return r2_ool(s, a, gen_helper_##NAME); \
+}
+
+GEN_RVP_R2_OOL(kabs16);
+GEN_RVP_R2_OOL(clrs16);
+GEN_RVP_R2_OOL(clz16);
+GEN_RVP_R2_OOL(clo16);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 56baefeb8e..e4a9463135 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -920,3 +920,161 @@ static inline void do_khmx8(CPURISCVState *env, void *vd, void *va,
}
RVPR(khmx8, 2, 1);
+
+/* SIMD 16-bit Miscellaneous Instructions */
+static inline void do_smin16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int16_t *d = vd, *a = va, *b = vb;
+
+ d[i] = (a[i] < b[i]) ? a[i] : b[i];
+}
+
+RVPR(smin16, 1, 2);
+
+static inline void do_umin16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint16_t *d = vd, *a = va, *b = vb;
+
+ d[i] = (a[i] < b[i]) ? a[i] : b[i];
+}
+
+RVPR(umin16, 1, 2);
+
+static inline void do_smax16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int16_t *d = vd, *a = va, *b = vb;
+
+ d[i] = (a[i] > b[i]) ? a[i] : b[i];
+}
+
+RVPR(smax16, 1, 2);
+
+static inline void do_umax16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint16_t *d = vd, *a = va, *b = vb;
+
+ d[i] = (a[i] > b[i]) ? a[i] : b[i];
+}
+
+RVPR(umax16, 1, 2);
+
+static int64_t sat64(CPURISCVState *env, int64_t a, uint8_t shift)
+{
+ int64_t max = shift >= 64 ? INT64_MAX : (1ull << shift) - 1;
+ int64_t min = shift >= 64 ? INT64_MIN : -(1ull << shift);
+ int64_t result;
+
+ if (a > max) {
+ result = max;
+ env->vxsat = 0x1;
+ } else if (a < min) {
+ result = min;
+ env->vxsat = 0x1;
+ } else {
+ result = a;
+ }
+ return result;
+}
+
+static inline void do_sclip16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int16_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0xf;
+
+ d[i] = sat64(env, a[i], shift);
+}
+
+RVPR(sclip16, 1, 2);
+
+static uint64_t satu64(CPURISCVState *env, uint64_t a, uint8_t shift)
+{
+ uint64_t max = shift >= 64 ? UINT64_MAX : (1ull << shift) - 1;
+ uint64_t result;
+
+ if (a > max) {
+ result = max;
+ env->vxsat = 0x1;
+ } else {
+ result = a;
+ }
+ return result;
+}
+
+static inline void do_uclip16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int16_t *d = vd, *a = va;
+ uint8_t shift = *(uint8_t *)vb & 0xf;
+
+ if (a[i] < 0) {
+ d[i] = 0;
+ env->vxsat = 0x1;
+ } else {
+ d[i] = satu64(env, a[i], shift);
+ }
+}
+
+RVPR(uclip16, 1, 2);
+
+typedef void PackedFn2i(CPURISCVState *, void *, void *, uint8_t);
+
+static inline target_ulong rvpr2(CPURISCVState *env, target_ulong a,
+ uint8_t step, uint8_t size, PackedFn2i *fn)
+{
+ int i, passes = sizeof(target_ulong) / size;
+ target_ulong result;
+
+ for (i = 0; i < passes; i += step) {
+ fn(env, &result, &a, i);
+ }
+ return result;
+}
+
+#define RVPR2(NAME, STEP, SIZE) \
+target_ulong HELPER(NAME)(CPURISCVState *env, target_ulong a) \
+{ \
+ return rvpr2(env, a, STEP, SIZE, (PackedFn2i *)do_##NAME); \
+}
+
+static inline void do_kabs16(CPURISCVState *env, void *vd, void *va, uint8_t i)
+{
+ int16_t *d = vd, *a = va;
+
+ if (a[i] == INT16_MIN) {
+ d[i] = INT16_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[i] = abs(a[i]);
+ }
+}
+
+RVPR2(kabs16, 1, 2);
+
+static inline void do_clrs16(CPURISCVState *env, void *vd, void *va, uint8_t i)
+{
+ int16_t *d = vd, *a = va;
+ d[i] = clrsb32(a[i]) - 16;
+}
+
+RVPR2(clrs16, 1, 2);
+
+static inline void do_clz16(CPURISCVState *env, void *vd, void *va, uint8_t i)
+{
+ int16_t *d = vd, *a = va;
+ d[i] = (a[i] < 0) ? 0 : (clz32(a[i]) - 16);
+}
+
+RVPR2(clz16, 1, 2);
+
+static inline void do_clo16(CPURISCVState *env, void *vd, void *va, uint8_t i)
+{
+ int16_t *d = vd, *a = va;
+ d[i] = (a[i] >= 0) ? 0 : (clo32(a[i]) - 16);
+}
+
+RVPR2(clo16, 1, 2);
--
2.25.1
next prev parent reply other threads:[~2021-06-10 8:14 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-10 7:58 [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-06-10 18:00 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-06-10 19:39 ` Richard Henderson
2021-06-11 4:36 ` LIU Zhiwei
2021-06-24 6:05 ` LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-06-10 19:44 ` Richard Henderson
2021-06-10 7:58 ` [PATCH v2 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-10 7:58 ` LIU Zhiwei [this message]
2021-06-10 7:58 ` [PATCH v2 12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:58 ` [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-06-10 7:59 ` [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-06-14 22:55 ` [PATCH v2 00/37] target/riscv: support packed extension v0.9.4 no-reply
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