From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 22/28] target/arm: Implement MVE WLSTP insn
Date: Tue, 15 Jun 2021 16:43:59 +0100 [thread overview]
Message-ID: <20210615154405.21399-23-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org>
Implement the MVE WLSTP insn; this is like the existing WLS insn,
except that it specifies a size value which is used to set
FPSCR.LTPSIZE.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-8-peter.maydell@linaro.org
---
target/arm/t32.decode | 8 ++++++--
target/arm/translate.c | 37 ++++++++++++++++++++++++++++++++++++-
2 files changed, 42 insertions(+), 3 deletions(-)
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 087e514e0ac..6906829265f 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -672,8 +672,12 @@ BL 1111 0. .......... 11.1 ............ @branch24
%lob_imm 1:10 11:1 !function=times_2
DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001
- WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=%lob_imm
- LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=%lob_imm
+ WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=%lob_imm size=4
+ {
+ LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=%lob_imm
+ # This is WLSTP
+ WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=%lob_imm
+ }
LCTP 1111 0 0000 000 1111 1110 0000 0000 0001
]
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c49561590c9..78878e9b194 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8134,7 +8134,11 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
return false;
}
if (a->rn == 13 || a->rn == 15) {
- /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
+ /*
+ * For WLSTP rn == 15 is a related encoding (LE); the
+ * other cases caught by this condition are all
+ * CONSTRAINED UNPREDICTABLE: we choose to UNDEF
+ */
return false;
}
if (s->condexec_mask) {
@@ -8147,10 +8151,41 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
*/
return false;
}
+ if (a->size != 4) {
+ /* WLSTP */
+ if (!dc_isar_feature(aa32_mve, s)) {
+ return false;
+ }
+ /*
+ * We need to check that the FPU is enabled here, but mustn't
+ * call vfp_access_check() to do that because we don't want to
+ * do the lazy state preservation in the "loop count is zero" case.
+ * Do the check-and-raise-exception by hand.
+ */
+ if (s->fp_excp_el) {
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(), s->fp_excp_el);
+ return true;
+ }
+ }
+
nextlabel = gen_new_label();
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_R[a->rn], 0, nextlabel);
tmp = load_reg(s, a->rn);
store_reg(s, 14, tmp);
+ if (a->size != 4) {
+ /*
+ * WLSTP: set FPSCR.LTPSIZE. This requires that we do the
+ * lazy state preservation, new FP context creation, etc,
+ * that vfp_access_check() does. We know that the actual
+ * access check will succeed (ie it won't generate code that
+ * throws an exception) because we did that check by hand earlier.
+ */
+ bool ok = vfp_access_check(s);
+ assert(ok);
+ tmp = tcg_const_i32(a->size);
+ store_cpu_field(tmp, v7m.ltpsize);
+ }
gen_jmp_tb(s, s->base.pc_next, 1);
gen_set_label(nextlabel);
--
2.20.1
next prev parent reply other threads:[~2021-06-15 15:56 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-15 15:43 [PULL 00/28] target-arm queue Peter Maydell
2021-06-15 15:43 ` [PULL 01/28] hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes Peter Maydell
2021-06-15 15:43 ` [PULL 02/28] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 Peter Maydell
2021-06-15 15:43 ` [PULL 03/28] target/arm: Remove fprintf from disas_simd_mod_imm Peter Maydell
2021-06-15 15:43 ` [PULL 04/28] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 Peter Maydell
2021-06-15 15:43 ` [PULL 05/28] hw: virt: consider hw_compat_6_0 Peter Maydell
2021-06-15 15:43 ` [PULL 06/28] hw/arm: add quanta-gbs-bmc machine Peter Maydell
2021-06-15 15:43 ` [PULL 07/28] hw/arm: quanta-gbs-bmc add i2c comments Peter Maydell
2021-06-15 15:43 ` [PULL 08/28] hw/intc/armv7m_nvic: Remove stale comment Peter Maydell
2021-06-15 15:43 ` [PULL 09/28] hw/acpi: Provide stub version of acpi_ghes_record_errors() Peter Maydell
2021-06-15 15:43 ` [PULL 10/28] hw/acpi: Provide function acpi_ghes_present() Peter Maydell
2021-06-15 15:43 ` [PULL 11/28] target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors Peter Maydell
2021-06-15 15:43 ` [PULL 12/28] target/arm: Fix mte page crossing test Peter Maydell
2021-06-15 15:43 ` [PULL 13/28] hw/arm: gsj add i2c comments Peter Maydell
2021-06-15 15:43 ` [PULL 14/28] hw/arm: gsj add pca9548 Peter Maydell
2021-06-15 15:43 ` [PULL 15/28] hw/arm: quanta-q71l add pca954x muxes Peter Maydell
2021-06-15 15:43 ` [PULL 16/28] target/arm: Provide and use H8 and H1_8 macros Peter Maydell
2021-06-15 15:43 ` [PULL 17/28] target/arm: Enable FPSCR.QC bit for MVE Peter Maydell
2021-06-15 15:43 ` [PULL 18/28] target/arm: Handle VPR semantics in existing code Peter Maydell
2021-06-15 15:43 ` [PULL 19/28] target/arm: Add handling for PSR.ECI/ICI Peter Maydell
2021-06-15 15:43 ` [PULL 20/28] target/arm: Let vfp_access_check() handle late NOCP checks Peter Maydell
2021-06-15 15:43 ` [PULL 21/28] target/arm: Implement MVE LCTP Peter Maydell
2021-06-15 15:43 ` Peter Maydell [this message]
2021-06-15 15:44 ` [PULL 23/28] target/arm: Implement MVE DLSTP Peter Maydell
2021-06-15 15:44 ` [PULL 24/28] target/arm: Implement MVE LETP insn Peter Maydell
2021-06-15 15:44 ` [PULL 25/28] target/arm: Add framework for MVE decode Peter Maydell
2021-06-15 15:44 ` [PULL 26/28] target/arm: Move expand_pred_b() data to vec_helper.c Peter Maydell
2021-06-15 15:44 ` [PULL 27/28] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations Peter Maydell
2021-06-15 15:44 ` [PULL 28/28] include/qemu/int128.h: Add function to create Int128 from int64_t Peter Maydell
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