From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/57] target/arm: Implement MVE VMVN (register)
Date: Mon, 21 Jun 2021 17:27:53 +0100 [thread overview]
Message-ID: <20210621162833.32535-18-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210621162833.32535-1-peter.maydell@linaro.org>
Implement the MVE VMVN(register) operation. Note that for
predication this operation is byte-by-byte.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-7-peter.maydell@linaro.org
---
target/arm/helper-mve.h | 2 ++
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c | 4 ++++
target/arm/translate-mve.c | 5 +++++
4 files changed, 14 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 4c89387587d..f1dc52f7a50 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -47,3 +47,5 @@ DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
+DEF_HELPER_FLAGS_3(mve_vmvn, TCG_CALL_NO_WG, void, env, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 16ee511a5cb..ff8afb682fb 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -30,6 +30,7 @@
@vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr
@1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm
+@1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0
# Vector loads and stores
@@ -74,3 +75,5 @@ VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op
VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op
VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op
VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op
+
+VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 8b565b50a9a..fa0a32d284b 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -277,3 +277,7 @@ DO_1OP(vrev32h, 4, uint32_t, hswap32)
DO_1OP(vrev64b, 8, uint64_t, bswap64)
DO_1OP(vrev64h, 8, uint64_t, hswap64)
DO_1OP(vrev64w, 8, uint64_t, wswap64)
+
+#define DO_NOT(N) (~(N))
+
+DO_1OP(vmvn, 8, uint64_t, DO_NOT)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 32a8324c5e6..bd908abcff7 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -232,3 +232,8 @@ static bool trans_VREV64(DisasContext *s, arg_1op *a)
};
return do_1op(s, a, fns[a->size]);
}
+
+static bool trans_VMVN(DisasContext *s, arg_1op *a)
+{
+ return do_1op(s, a, gen_helper_mve_vmvn);
+}
--
2.20.1
next prev parent reply other threads:[~2021-06-21 16:35 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-21 16:27 [PULL 00/57] target-arm queue Peter Maydell
2021-06-21 16:27 ` [PULL 01/57] hw/acpi: Provide stub version of acpi_ghes_record_errors() Peter Maydell
2021-06-21 16:27 ` [PULL 02/57] hw/acpi: Provide function acpi_ghes_present() Peter Maydell
2021-06-21 16:27 ` [PULL 03/57] target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors Peter Maydell
2021-06-21 16:27 ` [PULL 04/57] docs/system/arm: Document which architecture extensions we emulate Peter Maydell
2021-06-21 16:27 ` [PULL 05/57] target/arm/translate-vfp.c: Whitespace fixes Peter Maydell
2021-06-21 16:27 ` [PULL 06/57] target/arm: Handle FPU being disabled in FPCXT_NS accesses Peter Maydell
2021-06-21 16:27 ` [PULL 07/57] target/arm: Don't NOCP fault for " Peter Maydell
2021-06-21 16:27 ` [PULL 08/57] target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access Peter Maydell
2021-06-21 16:27 ` [PULL 09/57] target/arm: Factor FP context update code out into helper function Peter Maydell
2021-06-21 16:27 ` [PULL 10/57] target/arm: Split vfp_access_check() into A and M versions Peter Maydell
2021-06-21 16:27 ` [PULL 11/57] target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m() Peter Maydell
2021-06-21 16:27 ` [PULL 12/57] target/arm: Implement MVE VLDR/VSTR (non-widening forms) Peter Maydell
2021-06-21 16:27 ` [PULL 13/57] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns Peter Maydell
2021-06-21 16:27 ` [PULL 14/57] target/arm: Implement MVE VCLZ Peter Maydell
2021-06-21 16:27 ` [PULL 15/57] target/arm: Implement MVE VCLS Peter Maydell
2021-06-21 16:27 ` [PULL 16/57] target/arm: Implement MVE VREV16, VREV32, VREV64 Peter Maydell
2021-06-21 16:27 ` Peter Maydell [this message]
2021-06-21 16:27 ` [PULL 18/57] target/arm: Implement MVE VABS Peter Maydell
2021-06-21 16:27 ` [PULL 19/57] target/arm: Implement MVE VNEG Peter Maydell
2021-06-21 16:27 ` [PULL 20/57] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64 Peter Maydell
2021-06-21 16:27 ` [PULL 21/57] target/arm: Implement MVE VDUP Peter Maydell
2021-06-21 16:27 ` [PULL 22/57] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR Peter Maydell
2021-06-21 16:27 ` [PULL 23/57] target/arm: Implement MVE VADD, VSUB, VMUL Peter Maydell
2021-06-21 16:28 ` [PULL 24/57] target/arm: Implement MVE VMULH Peter Maydell
2021-06-21 16:28 ` [PULL 25/57] target/arm: Implement MVE VRMULH Peter Maydell
2021-06-21 16:28 ` [PULL 26/57] target/arm: Implement MVE VMAX, VMIN Peter Maydell
2021-06-21 16:28 ` [PULL 27/57] target/arm: Implement MVE VABD Peter Maydell
2021-06-21 16:28 ` [PULL 28/57] target/arm: Implement MVE VHADD, VHSUB Peter Maydell
2021-06-21 16:28 ` [PULL 29/57] target/arm: Implement MVE VMULL Peter Maydell
2021-06-21 16:28 ` [PULL 30/57] target/arm: Implement MVE VMLALDAV Peter Maydell
2021-06-21 16:28 ` [PULL 31/57] target/arm: Implement MVE VMLSLDAV Peter Maydell
2021-06-21 16:28 ` [PULL 32/57] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH Peter Maydell
2021-06-21 16:28 ` [PULL 33/57] target/arm: Implement MVE VADD (scalar) Peter Maydell
2021-06-21 16:28 ` [PULL 34/57] target/arm: Implement MVE VSUB, VMUL (scalar) Peter Maydell
2021-06-21 16:28 ` [PULL 35/57] target/arm: Implement MVE VHADD, VHSUB (scalar) Peter Maydell
2021-06-21 16:28 ` [PULL 36/57] target/arm: Implement MVE VBRSR Peter Maydell
2021-06-21 16:28 ` [PULL 37/57] target/arm: Implement MVE VPST Peter Maydell
2021-06-21 16:28 ` [PULL 38/57] target/arm: Implement MVE VQADD and VQSUB Peter Maydell
2021-06-21 16:28 ` [PULL 39/57] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) Peter Maydell
2021-06-21 16:28 ` [PULL 40/57] target/arm: Implement MVE VQDMULL scalar Peter Maydell
2021-06-21 16:28 ` [PULL 41/57] target/arm: Implement MVE VQDMULH, VQRDMULH (vector) Peter Maydell
2021-06-21 16:28 ` [PULL 42/57] target/arm: Implement MVE VQADD, VQSUB (vector) Peter Maydell
2021-06-21 16:28 ` [PULL 43/57] target/arm: Implement MVE VQSHL (vector) Peter Maydell
2021-06-21 16:28 ` [PULL 44/57] target/arm: Implement MVE VQRSHL Peter Maydell
2021-06-21 16:28 ` [PULL 45/57] target/arm: Implement MVE VSHL insn Peter Maydell
2021-06-21 16:28 ` [PULL 46/57] target/arm: Implement MVE VRSHL Peter Maydell
2021-06-21 16:28 ` [PULL 47/57] target/arm: Implement MVE VQDMLADH and VQRDMLADH Peter Maydell
2021-06-21 16:28 ` [PULL 48/57] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH Peter Maydell
2021-06-21 16:28 ` [PULL 49/57] target/arm: Implement MVE VQDMULL (vector) Peter Maydell
2021-06-21 16:28 ` [PULL 50/57] target/arm: Implement MVE VRHADD Peter Maydell
2021-06-21 16:28 ` [PULL 51/57] target/arm: Implement MVE VADC, VSBC Peter Maydell
2021-06-21 16:28 ` [PULL 52/57] target/arm: Implement MVE VCADD Peter Maydell
2021-06-21 16:28 ` [PULL 53/57] target/arm: Implement MVE VHCADD Peter Maydell
2021-06-21 16:28 ` [PULL 54/57] target/arm: Implement MVE VADDV Peter Maydell
2021-06-21 16:28 ` [PULL 55/57] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE Peter Maydell
2021-06-21 16:28 ` [PULL 56/57] target/arm: Implement MTE3 Peter Maydell
2021-06-21 16:28 ` [PULL 57/57] docs/system: arm: Add nRF boards description Peter Maydell
2021-06-21 17:25 ` [PULL 00/57] target-arm queue no-reply
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