From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDC88C48BDF for ; Thu, 24 Jun 2021 11:16:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 718DE611CE for ; Thu, 24 Jun 2021 11:16:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 718DE611CE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:54278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwNLp-00053A-HV for qemu-devel@archiver.kernel.org; Thu, 24 Jun 2021 07:16:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42608) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwN58-00069W-Dq; Thu, 24 Jun 2021 06:59:38 -0400 Received: from out28-49.mail.aliyun.com ([115.124.28.49]:48875) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwN55-0006Hi-Ru; Thu, 24 Jun 2021 06:59:38 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.074364|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.622771-0.00721081-0.370018; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047199; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.KXJqQRB_1624532370; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KXJqQRB_1624532370) by smtp.aliyun-inc.com(10.147.41.121); Thu, 24 Jun 2021 18:59:30 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 06/37] target/riscv: SIMD 8-bit Shift Instructions Date: Thu, 24 Jun 2021 18:54:50 +0800 Message-Id: <20210624105521.3964-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> References: <20210624105521.3964-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.49; envelope-from=zhiwei_liu@c-sky.com; helo=out28-49.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Instructions include right arithmetic shift, right logic shift, and left shift. The shift can be an immediate or a register scalar. The right shift has rounding operation. And the left shift has saturation operation. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 17 ++++ target/riscv/insn_trans/trans_rvp.c.inc | 16 ++++ target/riscv/packed_helper.c | 102 ++++++++++++++++++++++++ 4 files changed, 144 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index de7b4fc17d..1b365135ff 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1197,3 +1197,12 @@ DEF_HELPER_3(sll16, tl, env, tl, tl) DEF_HELPER_3(ksll16, tl, env, tl, tl) DEF_HELPER_3(kslra16, tl, env, tl, tl) DEF_HELPER_3(kslra16_u, tl, env, tl, tl) + +DEF_HELPER_3(sra8, tl, env, tl, tl) +DEF_HELPER_3(sra8_u, tl, env, tl, tl) +DEF_HELPER_3(srl8, tl, env, tl, tl) +DEF_HELPER_3(srl8_u, tl, env, tl, tl) +DEF_HELPER_3(sll8, tl, env, tl, tl) +DEF_HELPER_3(ksll8, tl, env, tl, tl) +DEF_HELPER_3(kslra8, tl, env, tl, tl) +DEF_HELPER_3(kslra8_u, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 44c497f28a..8b78fb24bc 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -25,6 +25,7 @@ %sh7 20:7 %sh4 20:4 +%sh3 20:3 %csr 20:12 %rm 12:3 %nf 29:3 !function=ex_plus_1 @@ -63,6 +64,7 @@ @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd @sh4 ...... ...... ..... ... ..... ....... &shift shamt=%sh4 %rs1 %rd +@sh3 ...... ...... ..... ... ..... ....... &shift shamt=%sh3 %rs1 %rd @csr ............ ..... ... ..... ....... %csr %rs1 %rd @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd @@ -792,3 +794,18 @@ ksll16 0110010 ..... ..... 000 ..... 1110111 @r kslli16 0111010 1.... ..... 000 ..... 1110111 @sh4 kslra16 0101011 ..... ..... 000 ..... 1110111 @r kslra16_u 0110011 ..... ..... 000 ..... 1110111 @r + +sra8 0101100 ..... ..... 000 ..... 1110111 @r +sra8_u 0110100 ..... ..... 000 ..... 1110111 @r +srai8 0111100 00... ..... 000 ..... 1110111 @sh3 +srai8_u 0111100 01... ..... 000 ..... 1110111 @sh3 +srl8 0101101 ..... ..... 000 ..... 1110111 @r +srl8_u 0110101 ..... ..... 000 ..... 1110111 @r +srli8 0111101 00... ..... 000 ..... 1110111 @sh3 +srli8_u 0111101 01... ..... 000 ..... 1110111 @sh3 +sll8 0101110 ..... ..... 000 ..... 1110111 @r +slli8 0111110 00... ..... 000 ..... 1110111 @sh3 +ksll8 0110110 ..... ..... 000 ..... 1110111 @r +kslli8 0111110 01... ..... 000 ..... 1110111 @sh3 +kslra8 0101111 ..... ..... 000 ..... 1110111 @r +kslra8_u 0110111 ..... ..... 000 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index afafa49824..e6c5f2ddf5 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -187,3 +187,19 @@ GEN_RVP_SHIFTI(slli16, tcg_gen_vec_shl16i_tl, gen_helper_sll16); GEN_RVP_SHIFTI(srai16_u, NULL, gen_helper_sra16_u); GEN_RVP_SHIFTI(srli16_u, NULL, gen_helper_srl16_u); GEN_RVP_SHIFTI(kslli16, NULL, gen_helper_ksll16); + +/* SIMD 8-bit Shift Instructions */ +GEN_RVP_R_OOL(sra8); +GEN_RVP_R_OOL(srl8); +GEN_RVP_R_OOL(sll8); +GEN_RVP_R_OOL(sra8_u); +GEN_RVP_R_OOL(srl8_u); +GEN_RVP_R_OOL(ksll8); +GEN_RVP_R_OOL(kslra8); +GEN_RVP_R_OOL(kslra8_u); +GEN_RVP_SHIFTI(srai8, tcg_gen_vec_sar8i_tl, gen_helper_sra8); +GEN_RVP_SHIFTI(srli8, tcg_gen_vec_shr8i_tl, gen_helper_srl8); +GEN_RVP_SHIFTI(slli8, tcg_gen_vec_shl8i_tl, gen_helper_sll8); +GEN_RVP_SHIFTI(srai8_u, NULL, gen_helper_sra8_u); +GEN_RVP_SHIFTI(srli8_u, NULL, gen_helper_srl8_u); +GEN_RVP_SHIFTI(kslli8, NULL, gen_helper_ksll8); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 7e31c2fe46..ab9ebc472b 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -529,3 +529,105 @@ static inline void do_kslra16_u(CPURISCVState *env, void *vd, void *va, } RVPR(kslra16_u, 1, 2); + +/* SIMD 8-bit Shift Instructions */ +static inline void do_sra8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x7; + d[i] = a[i] >> shift; +} + +RVPR(sra8, 1, 1); + +static inline void do_srl8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint8_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x7; + d[i] = a[i] >> shift; +} + +RVPR(srl8, 1, 1); + +static inline void do_sll8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint8_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x7; + d[i] = a[i] << shift; +} + +RVPR(sll8, 1, 1); + +static inline void do_sra8_u(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x7; + d[i] = vssra8(env, 0, a[i], shift); +} + +RVPR(sra8_u, 1, 1); + +static inline void do_srl8_u(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint8_t *d = vd, *a = va; + uint8_t shift = *(uint8_t *)vb & 0x7; + d[i] = vssrl8(env, 0, a[i], shift); +} + +RVPR(srl8_u, 1, 1); + +static inline void do_ksll8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va, result; + uint8_t shift = *(uint8_t *)vb & 0x7; + + result = a[i] << shift; + if (shift > (clrsb32(a[i]) - 24)) { + env->vxsat = 0x1; + d[i] = (a[i] & INT8_MIN) ? INT8_MIN : INT8_MAX; + } else { + d[i] = result; + } +} + +RVPR(ksll8, 1, 1); + +static inline void do_kslra8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va; + int32_t shift = sextract32((*(uint32_t *)vb), 0, 4); + + if (shift >= 0) { + do_ksll8(env, vd, va, vb, i); + } else { + shift = -shift; + shift = (shift == 8) ? 7 : shift; + d[i] = a[i] >> shift; + } +} + +RVPR(kslra8, 1, 1); + +static inline void do_kslra8_u(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va; + int32_t shift = sextract32((*(uint32_t *)vb), 0, 4); + + if (shift >= 0) { + do_ksll8(env, vd, va, vb, i); + } else { + shift = -shift; + shift = (shift == 8) ? 7 : shift; + d[i] = vssra8(env, 0, a[i], shift); + } +} + +RVPR(kslra8_u, 1, 1); -- 2.17.1