From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 1/7] target/riscv: Use target_ulong for the DisasContext misa
Date: Thu, 24 Jun 2021 05:02:05 -0700 [thread overview]
Message-ID: <20210624120211.85499-2-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com>
The is_32bit() check in translate.c expects a 64-bit guest to have a
64-bit misa value otherwise the macro check won't work. This patches
fixes that and fixes a Coverity issue at the same time.
Fixes: CID 1453107
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: c00176c7518c2a7b4de3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com
---
target/riscv/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c6e8739614..62a7d7e4c7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -47,7 +47,7 @@ typedef struct DisasContext {
bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs;
- uint32_t misa;
+ target_ulong misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
--
2.31.1
next prev parent reply other threads:[~2021-06-24 12:06 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 12:02 [PULL 0/7] riscv-to-apply queue Alistair Francis
2021-06-24 12:02 ` Alistair Francis [this message]
2021-06-24 12:02 ` [PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation Alistair Francis
2021-06-24 12:02 ` [PULL 3/7] hw/char: Consistent function names for sifive_uart Alistair Francis
2021-06-24 12:02 ` [PULL 4/7] hw/char: QOMify sifive_uart Alistair Francis
2021-06-24 12:02 ` [PULL 5/7] hw/char/ibex_uart: Make the register layout private Alistair Francis
2021-06-24 12:02 ` [PULL 6/7] hw/timer: Initial commit of Ibex Timer Alistair Francis
2021-06-24 12:02 ` [PULL 7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Alistair Francis
2021-06-25 17:55 ` [PULL 0/7] riscv-to-apply queue Peter Maydell
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