* [PATCH v3 00/29] tcg: bswap improvements
@ 2021-06-26 6:36 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 01/29] tcg: Add flags argument to bswap opcodes Richard Henderson
` (29 more replies)
0 siblings, 30 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel
Changes for v3:
* Comment improvments for mips (phil).
* Patch 3 is new, rearranging some tcg/aarch64 helpers.
Changes for v2:
* Merge tcg_out_rev{16,32,64}, which perhaps solves the issue of
mnemonics vs actual opcodes, and also preps for Phil suggestion
of adding additional tcg opcodes for hswap and wswap operations.
* Improve comments for ppc bswap.
* Improve README entries.
Patches lacking review:
03-tcg-aarch64-Merge-tcg_out_rev-16-32-64.patch
11-tcg-ppc-Support-bswap-flags.patch
12-tcg-ppc-Use-power10-byte-reverse-instructions.patch
13-tcg-s390-Support-bswap-flags.patch
r~
Richard Henderson (29):
tcg: Add flags argument to bswap opcodes
tcg/i386: Support bswap flags
tcg/aarch64: Merge tcg_out_rev{16,32,64}
tcg/aarch64: Support bswap flags
tcg/arm: Support bswap flags
tcg/ppc: Split out tcg_out_ext{8,16,32}s
tcg/ppc: Split out tcg_out_sari{32,64}
tcg/ppc: Split out tcg_out_bswap16
tcg/ppc: Split out tcg_out_bswap32
tcg/ppc: Split out tcg_out_bswap64
tcg/ppc: Support bswap flags
tcg/ppc: Use power10 byte-reverse instructions
tcg/s390: Support bswap flags
tcg/mips: Support bswap flags in tcg_out_bswap16
tcg/mips: Support bswap flags in tcg_out_bswap32
tcg/tci: Support bswap flags
tcg: Handle new bswap flags during optimize
tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64
tcg: Make use of bswap flags in tcg_gen_qemu_ld_*
tcg: Make use of bswap flags in tcg_gen_qemu_st_*
target/arm: Improve REV32
target/arm: Improve vector REV
target/arm: Improve REVSH
target/i386: Improve bswap translation
target/sh4: Improve swap.b translation
target/mips: Fix gen_mxu_s32ldd_s32lddr
tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP
tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAP
tcg/riscv: Remove MO_BSWAP handling
include/tcg/tcg-op.h | 8 +-
include/tcg/tcg-opc.h | 10 +-
include/tcg/tcg.h | 12 ++
tcg/aarch64/tcg-target.h | 2 +-
tcg/arm/tcg-target.h | 2 +-
target/arm/translate-a64.c | 21 +--
target/arm/translate.c | 4 +-
target/i386/tcg/translate.c | 14 +-
target/mips/tcg/mxu_translate.c | 6 +-
target/s390x/translate.c | 4 +-
target/sh4/translate.c | 3 +-
tcg/optimize.c | 56 +++++-
tcg/tcg-op.c | 143 ++++++++++------
tcg/tcg.c | 28 +++
tcg/tci.c | 3 +-
tcg/aarch64/tcg-target.c.inc | 125 ++++++--------
tcg/arm/tcg-target.c.inc | 295 ++++++++++++++------------------
tcg/i386/tcg-target.c.inc | 20 ++-
tcg/mips/tcg-target.c.inc | 102 +++++------
tcg/ppc/tcg-target.c.inc | 230 +++++++++++++++++--------
tcg/riscv/tcg-target.c.inc | 64 +++----
tcg/s390/tcg-target.c.inc | 34 +++-
tcg/tci/tcg-target.c.inc | 23 ++-
tcg/README | 22 ++-
24 files changed, 704 insertions(+), 527 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v3 01/29] tcg: Add flags argument to bswap opcodes
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 02/29] tcg/i386: Support bswap flags Richard Henderson
` (28 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
This will eventually simplify front-end usage, and will allow
backends to unset TCG_TARGET_HAS_MEMORY_BSWAP without loss of
optimization.
The argument is added during expansion, not currently exposed to the
front end translators. The backends currently only support a flags
value of either TCG_BSWAP_IZ, or (TCG_BSWAP_IZ | TCG_BSWAP_OZ),
since they all require zero top bytes and leave them that way.
At the existing call sites we pass in (TCG_BSWAP_IZ | TCG_BSWAP_OZ),
except for the flags-ignored cases of a 32-bit swap of a 32-bit
value and or a 64-bit swap of a 64-bit value, where we pass 0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-opc.h | 10 +++++-----
include/tcg/tcg.h | 12 ++++++++++++
tcg/tcg-op.c | 13 ++++++++-----
tcg/tcg.c | 28 ++++++++++++++++++++++++++++
tcg/README | 22 ++++++++++++++--------
5 files changed, 67 insertions(+), 18 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 5bbec858aa..993992373e 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -96,8 +96,8 @@ DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
-DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
-DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
+DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap16_i32))
+DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap32_i32))
DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
@@ -165,9 +165,9 @@ DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
-DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
-DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
-DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
+DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
+DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
+DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 2dad364240..899493701c 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -408,6 +408,18 @@ typedef TCGv_ptr TCGv_env;
/* Used to align parameters. See the comment before tcgv_i32_temp. */
#define TCG_CALL_DUMMY_ARG ((TCGArg)0)
+/*
+ * Flags for the bswap opcodes.
+ * If IZ, the input is zero-extended, otherwise unknown.
+ * If OZ or OS, the output is zero- or sign-extended respectively,
+ * otherwise the high bits are undefined.
+ */
+enum {
+ TCG_BSWAP_IZ = 1,
+ TCG_BSWAP_OZ = 2,
+ TCG_BSWAP_OS = 4,
+};
+
typedef enum TCGTempVal {
TEMP_VAL_DEAD,
TEMP_VAL_REG,
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index dcc2ed0bbc..dc65577e2f 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1005,7 +1005,8 @@ void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
{
if (TCG_TARGET_HAS_bswap16_i32) {
- tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
+ tcg_gen_op3i_i32(INDEX_op_bswap16_i32, ret, arg,
+ TCG_BSWAP_IZ | TCG_BSWAP_OZ);
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
@@ -1020,7 +1021,7 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
{
if (TCG_TARGET_HAS_bswap32_i32) {
- tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
+ tcg_gen_op3i_i32(INDEX_op_bswap32_i32, ret, arg, 0);
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -1661,7 +1662,8 @@ void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
} else if (TCG_TARGET_HAS_bswap16_i64) {
- tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
+ tcg_gen_op3i_i64(INDEX_op_bswap16_i64, ret, arg,
+ TCG_BSWAP_IZ | TCG_BSWAP_OZ);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
@@ -1680,7 +1682,8 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
} else if (TCG_TARGET_HAS_bswap32_i64) {
- tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
+ tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg,
+ TCG_BSWAP_IZ | TCG_BSWAP_OZ);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
@@ -1717,7 +1720,7 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
} else if (TCG_TARGET_HAS_bswap64_i64) {
- tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
+ tcg_gen_op3i_i64(INDEX_op_bswap64_i64, ret, arg, 0);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5e53c3348f..5150ed700e 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1778,6 +1778,14 @@ static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = {
[MO_ALIGN_64 >> MO_ASHIFT] = "al64+",
};
+static const char bswap_flag_name[][6] = {
+ [TCG_BSWAP_IZ] = "iz",
+ [TCG_BSWAP_OZ] = "oz",
+ [TCG_BSWAP_OS] = "os",
+ [TCG_BSWAP_IZ | TCG_BSWAP_OZ] = "iz,oz",
+ [TCG_BSWAP_IZ | TCG_BSWAP_OS] = "iz,os",
+};
+
static inline bool tcg_regset_single(TCGRegSet d)
{
return (d & (d - 1)) == 0;
@@ -1921,6 +1929,26 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
i = 1;
}
break;
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ {
+ TCGArg flags = op->args[k];
+ const char *name = NULL;
+
+ if (flags < ARRAY_SIZE(bswap_flag_name)) {
+ name = bswap_flag_name[flags];
+ }
+ if (name) {
+ col += qemu_log(",%s", name);
+ } else {
+ col += qemu_log(",$0x%" TCG_PRIlx, flags);
+ }
+ i = k = 1;
+ }
+ break;
default:
i = 0;
break;
diff --git a/tcg/README b/tcg/README
index 8510d823e3..c2e7762a37 100644
--- a/tcg/README
+++ b/tcg/README
@@ -295,19 +295,25 @@ ext32u_i64 t0, t1
8, 16 or 32 bit sign/zero extension (both operands must have the same type)
-* bswap16_i32/i64 t0, t1
+* bswap16_i32/i64 t0, t1, flags
-16 bit byte swap on a 32/64 bit value. It assumes that the two/six high order
-bytes are set to zero.
+16 bit byte swap on the low bits of a 32/64 bit input.
+If flags & TCG_BSWAP_IZ, then t1 is known to be zero-extended from bit 15.
+If flags & TCG_BSWAP_OZ, then t0 will be zero-extended from bit 15.
+If flags & TCG_BSWAP_OS, then t0 will be sign-extended from bit 15.
+If neither TCG_BSWAP_OZ nor TCG_BSWAP_OS are set, then the bits of
+t0 above bit 15 may contain any value.
-* bswap32_i32/i64 t0, t1
+* bswap32_i64 t0, t1, flags
-32 bit byte swap on a 32/64 bit value. With a 64 bit value, it assumes that
-the four high order bytes are set to zero.
+32 bit byte swap on a 64-bit value. The flags are the same as for bswap16,
+except they apply from bit 31 instead of bit 15.
-* bswap64_i64 t0, t1
+* bswap32_i32 t0, t1, flags
+* bswap64_i64 t0, t1, flags
-64 bit byte swap
+32/64 bit byte swap. The flags are ignored, but still present
+for consistency with the other bswap opcodes.
* discard_i32/i64 t0
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 02/29] tcg/i386: Support bswap flags
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
2021-06-26 6:36 ` [PATCH v3 01/29] tcg: Add flags argument to bswap opcodes Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 03/29] tcg/aarch64: Merge tcg_out_rev{16,32,64} Richard Henderson
` (27 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Retain the current rorw bswap16 expansion for the zero-in/zero-out case.
Otherwise, perform a wider bswap plus a right-shift or extend.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 34113388ef..98d924b91a 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2421,10 +2421,28 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
OP_32_64(bswap16):
- tcg_out_rolw_8(s, a0);
+ if (a2 & TCG_BSWAP_OS) {
+ /* Output must be sign-extended. */
+ if (rexw) {
+ tcg_out_bswap64(s, a0);
+ tcg_out_shifti(s, SHIFT_SAR + rexw, a0, 48);
+ } else {
+ tcg_out_bswap32(s, a0);
+ tcg_out_shifti(s, SHIFT_SAR, a0, 16);
+ }
+ } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ /* Output must be zero-extended, but input isn't. */
+ tcg_out_bswap32(s, a0);
+ tcg_out_shifti(s, SHIFT_SHR, a0, 16);
+ } else {
+ tcg_out_rolw_8(s, a0);
+ }
break;
OP_32_64(bswap32):
tcg_out_bswap32(s, a0);
+ if (rexw && (a2 & TCG_BSWAP_OS)) {
+ tcg_out_ext32s(s, a0, a0);
+ }
break;
OP_32_64(neg):
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 03/29] tcg/aarch64: Merge tcg_out_rev{16,32,64}
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
2021-06-26 6:36 ` [PATCH v3 01/29] tcg: Add flags argument to bswap opcodes Richard Henderson
2021-06-26 6:36 ` [PATCH v3 02/29] tcg/i386: Support bswap flags Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-28 14:16 ` Peter Maydell
2021-06-26 6:36 ` [PATCH v3 04/29] tcg/aarch64: Support bswap flags Richard Henderson
` (26 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Pass in the input and output size. We currently use 3 of the 5
possible combinations; the others may be used by new tcg opcodes.
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 42 ++++++++++++++----------------------
1 file changed, 16 insertions(+), 26 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 27cde314a9..8619e54fca 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -475,9 +475,7 @@ typedef enum {
/* Data-processing (1 source) instructions. */
I3507_CLZ = 0x5ac01000,
I3507_RBIT = 0x5ac00000,
- I3507_REV16 = 0x5ac00400,
- I3507_REV32 = 0x5ac00800,
- I3507_REV64 = 0x5ac00c00,
+ I3507_REV = 0x5ac00000, /* + size << 10 */
/* Data-processing (2 source) instructions. */
I3508_LSLV = 0x1ac02000,
@@ -1417,19 +1415,11 @@ static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a,
}
}
-static inline void tcg_out_rev64(TCGContext *s, TCGReg rd, TCGReg rn)
+static inline void tcg_out_rev(TCGContext *s, int ext, MemOp s_bits,
+ TCGReg rd, TCGReg rn)
{
- tcg_out_insn(s, 3507, REV64, TCG_TYPE_I64, rd, rn);
-}
-
-static inline void tcg_out_rev32(TCGContext *s, TCGReg rd, TCGReg rn)
-{
- tcg_out_insn(s, 3507, REV32, TCG_TYPE_I32, rd, rn);
-}
-
-static inline void tcg_out_rev16(TCGContext *s, TCGReg rd, TCGReg rn)
-{
- tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn);
+ /* REV, REV16, REV32 */
+ tcg_out_insn_3507(s, I3507_REV | (s_bits << 10), ext, rd, rn);
}
static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits,
@@ -1737,13 +1727,13 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
case MO_UW:
tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
if (bswap) {
- tcg_out_rev16(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_16, data_r, data_r);
}
break;
case MO_SW:
if (bswap) {
tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
- tcg_out_rev16(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_16, data_r, data_r);
tcg_out_sxt(s, ext, MO_16, data_r, data_r);
} else {
tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
@@ -1753,13 +1743,13 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
case MO_UL:
tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
if (bswap) {
- tcg_out_rev32(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_32, data_r, data_r);
}
break;
case MO_SL:
if (bswap) {
tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
- tcg_out_rev32(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_32, data_r, data_r);
tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r);
} else {
tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
@@ -1768,7 +1758,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
case MO_Q:
tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
if (bswap) {
- tcg_out_rev64(s, data_r, data_r);
+ tcg_out_rev(s, TCG_TYPE_I64, MO_64, data_r, data_r);
}
break;
default:
@@ -1788,21 +1778,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
break;
case MO_16:
if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev16(s, TCG_REG_TMP, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_16, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
break;
case MO_32:
if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev32(s, TCG_REG_TMP, data_r);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_32, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
break;
case MO_64:
if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev64(s, TCG_REG_TMP, data_r);
+ tcg_out_rev(s, TCG_TYPE_I64, MO_64, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
@@ -2184,15 +2174,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_bswap64_i64:
- tcg_out_rev64(s, a0, a1);
+ tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
break;
case INDEX_op_bswap32_i64:
case INDEX_op_bswap32_i32:
- tcg_out_rev32(s, a0, a1);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1);
break;
case INDEX_op_bswap16_i64:
case INDEX_op_bswap16_i32:
- tcg_out_rev16(s, a0, a1);
+ tcg_out_rev(s, TCG_TYPE_I32, MO_16, a0, a1);
break;
case INDEX_op_ext8s_i64:
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 04/29] tcg/aarch64: Support bswap flags
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (2 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 03/29] tcg/aarch64: Merge tcg_out_rev{16,32,64} Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 9:38 ` Philippe Mathieu-Daudé
2021-06-26 6:36 ` [PATCH v3 05/29] tcg/arm: " Richard Henderson
` (25 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 8619e54fca..72aa7e0e74 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2177,12 +2177,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
break;
case INDEX_op_bswap32_i64:
+ tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a0);
+ }
+ break;
case INDEX_op_bswap32_i32:
tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1);
break;
case INDEX_op_bswap16_i64:
case INDEX_op_bswap16_i32:
tcg_out_rev(s, TCG_TYPE_I32, MO_16, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ /* Output must be sign-extended. */
+ tcg_out_sxt(s, ext, MO_16, a0, a0);
+ } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ /* Output must be zero-extended, but input isn't. */
+ tcg_out_uxt(s, MO_16, a0, a0);
+ }
break;
case INDEX_op_ext8s_i64:
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 05/29] tcg/arm: Support bswap flags
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (3 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 04/29] tcg/aarch64: Support bswap flags Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 06/29] tcg/ppc: Split out tcg_out_ext{8,16,32}s Richard Henderson
` (24 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Combine the three bswap16 routines, and differentiate via the flags.
Use the correct flags combination from the load/store routines, and
pass along the constant parameter from tcg_out_op.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 101 ++++++++++++++++++++++++---------------
1 file changed, 63 insertions(+), 38 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 5157143246..73e0455511 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1013,50 +1013,71 @@ static inline void tcg_out_ext16u(TCGContext *s, int cond,
}
}
-static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
+static void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn, int flags)
{
if (use_armv6_instructions) {
- /* revsh */
- tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
- } else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24));
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_ASR(16));
- tcg_out_dat_reg(s, cond, ARITH_ORR,
- rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8));
- }
-}
+ if (flags & TCG_BSWAP_OS) {
+ /* revsh */
+ tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
+ return;
+ }
-static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
-{
- if (use_armv6_instructions) {
/* rev16 */
tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
- } else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, rn, SHIFT_IMM_LSL(24));
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_LSR(16));
- tcg_out_dat_reg(s, cond, ARITH_ORR,
- rd, TCG_REG_TMP, rn, SHIFT_IMM_LSR(8));
+ if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ /* uxth */
+ tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rd);
+ }
+ return;
}
-}
-/* swap the two low bytes assuming that the two high input bytes and the
- two high output bit can hold any value. */
-static inline void tcg_out_bswap16st(TCGContext *s, int cond, int rd, int rn)
-{
- if (use_armv6_instructions) {
- /* rev16 */
- tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
- } else {
+ if (flags == 0) {
+ /*
+ * For stores, no input or output extension:
+ * rn = xxAB
+ * lsr tmp, rn, #8 tmp = 0xxA
+ * and tmp, tmp, #0xff tmp = 000A
+ * orr rd, tmp, rn, lsl #8 rd = xABA
+ */
tcg_out_dat_reg(s, cond, ARITH_MOV,
TCG_REG_TMP, 0, rn, SHIFT_IMM_LSR(8));
tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_TMP, TCG_REG_TMP, 0xff);
tcg_out_dat_reg(s, cond, ARITH_ORR,
rd, TCG_REG_TMP, rn, SHIFT_IMM_LSL(8));
+ return;
}
+
+ /*
+ * Byte swap, leaving the result at the top of the register.
+ * We will then shift down, zero or sign-extending.
+ */
+ if (flags & TCG_BSWAP_IZ) {
+ /*
+ * rn = 00AB
+ * ror tmp, rn, #8 tmp = B00A
+ * orr tmp, tmp, tmp, lsl #16 tmp = BA00
+ */
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ TCG_REG_TMP, 0, rn, SHIFT_IMM_ROR(8));
+ tcg_out_dat_reg(s, cond, ARITH_ORR,
+ TCG_REG_TMP, TCG_REG_TMP, TCG_REG_TMP,
+ SHIFT_IMM_LSL(16));
+ } else {
+ /*
+ * rn = xxAB
+ * and tmp, rn, #0xff00 tmp = 00A0
+ * lsl tmp, tmp, #8 tmp = 0A00
+ * orr tmp, tmp, rn, lsl #24 tmp = BA00
+ */
+ tcg_out_dat_rI(s, cond, ARITH_AND, TCG_REG_TMP, rn, 0xff00, 1);
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ TCG_REG_TMP, 0, TCG_REG_TMP, SHIFT_IMM_LSL(8));
+ tcg_out_dat_reg(s, cond, ARITH_ORR,
+ TCG_REG_TMP, TCG_REG_TMP, rn, SHIFT_IMM_LSL(24));
+ }
+ tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, TCG_REG_TMP,
+ (flags & TCG_BSWAP_OS
+ ? SHIFT_IMM_ASR(8) : SHIFT_IMM_LSR(8)));
}
static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
@@ -1705,13 +1726,15 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
case MO_UW:
tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
if (bswap) {
- tcg_out_bswap16(s, COND_AL, datalo, datalo);
+ tcg_out_bswap16(s, COND_AL, datalo, datalo,
+ TCG_BSWAP_IZ | TCG_BSWAP_OZ);
}
break;
case MO_SW:
if (bswap) {
tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
- tcg_out_bswap16s(s, COND_AL, datalo, datalo);
+ tcg_out_bswap16(s, COND_AL, datalo, datalo,
+ TCG_BSWAP_IZ | TCG_BSWAP_OS);
} else {
tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
}
@@ -1766,13 +1789,15 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,
case MO_UW:
tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
if (bswap) {
- tcg_out_bswap16(s, COND_AL, datalo, datalo);
+ tcg_out_bswap16(s, COND_AL, datalo, datalo,
+ TCG_BSWAP_IZ | TCG_BSWAP_OZ);
}
break;
case MO_SW:
if (bswap) {
tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
- tcg_out_bswap16s(s, COND_AL, datalo, datalo);
+ tcg_out_bswap16(s, COND_AL, datalo, datalo,
+ TCG_BSWAP_IZ | TCG_BSWAP_OS);
} else {
tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
}
@@ -1862,7 +1887,7 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc,
break;
case MO_16:
if (bswap) {
- tcg_out_bswap16st(s, cond, TCG_REG_R0, datalo);
+ tcg_out_bswap16(s, cond, TCG_REG_R0, datalo, 0);
tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend);
} else {
tcg_out_st16_r(s, cond, datalo, addrlo, addend);
@@ -1907,7 +1932,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc,
break;
case MO_16:
if (bswap) {
- tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, datalo);
+ tcg_out_bswap16(s, COND_AL, TCG_REG_R0, datalo, 0);
tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0);
} else {
tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
@@ -2245,7 +2270,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_bswap16_i32:
- tcg_out_bswap16(s, COND_AL, args[0], args[1]);
+ tcg_out_bswap16(s, COND_AL, args[0], args[1], args[2]);
break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, COND_AL, args[0], args[1]);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 06/29] tcg/ppc: Split out tcg_out_ext{8,16,32}s
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (4 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 05/29] tcg/arm: " Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 07/29] tcg/ppc: Split out tcg_out_sari{32,64} Richard Henderson
` (23 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-ppc, Philippe Mathieu-Daudé
We will shortly require these in other context;
make the expansion as clear as possible.
Cc: qemu-ppc@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 31 +++++++++++++++++++++----------
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 795701442b..aa35ff8250 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -738,6 +738,21 @@ static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
}
+static inline void tcg_out_ext8s(TCGContext *s, TCGReg dst, TCGReg src)
+{
+ tcg_out32(s, EXTSB | RA(dst) | RS(src));
+}
+
+static inline void tcg_out_ext16s(TCGContext *s, TCGReg dst, TCGReg src)
+{
+ tcg_out32(s, EXTSH | RA(dst) | RS(src));
+}
+
+static inline void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src)
+{
+ tcg_out32(s, EXTSW | RA(dst) | RS(src));
+}
+
static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
{
tcg_out_rld(s, RLDICL, dst, src, 0, 32);
@@ -2322,7 +2337,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0, a1, a2;
- int c;
switch (opc) {
case INDEX_op_exit_tb:
@@ -2390,7 +2404,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ld8s_i32:
case INDEX_op_ld8s_i64:
tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
- tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
+ tcg_out_ext8s(s, args[0], args[0]);
break;
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
@@ -2728,18 +2742,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
- c = EXTSB;
- goto gen_ext;
+ tcg_out_ext8s(s, args[0], args[1]);
+ break;
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
- c = EXTSH;
- goto gen_ext;
+ tcg_out_ext16s(s, args[0], args[1]);
+ break;
case INDEX_op_ext_i32_i64:
case INDEX_op_ext32s_i64:
- c = EXTSW;
- goto gen_ext;
- gen_ext:
- tcg_out32(s, c | RS(args[1]) | RA(args[0]));
+ tcg_out_ext32s(s, args[0], args[1]);
break;
case INDEX_op_extu_i32_i64:
tcg_out_ext32u(s, args[0], args[1]);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 07/29] tcg/ppc: Split out tcg_out_sari{32,64}
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (5 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 06/29] tcg/ppc: Split out tcg_out_ext{8,16,32}s Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 08/29] tcg/ppc: Split out tcg_out_bswap16 Richard Henderson
` (22 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-ppc
We will shortly require sari in other context;
split out both for cleanliness sake.
Cc: qemu-ppc@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index aa35ff8250..50347182d7 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -768,6 +768,12 @@ static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
}
+static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c)
+{
+ /* Limit immediate shift count lest we create an illegal insn. */
+ tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31));
+}
+
static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
{
tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
@@ -778,6 +784,11 @@ static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
}
+static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c)
+{
+ tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2));
+}
+
/* Emit a move into ret of arg, if it can be done in one insn. */
static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
{
@@ -2601,8 +2612,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_sar_i32:
if (const_args[2]) {
- /* Limit immediate shift count lest we create an illegal insn. */
- tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2] & 31));
+ tcg_out_sari32(s, args[0], args[1], args[2]);
} else {
tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
}
@@ -2690,8 +2700,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_sar_i64:
if (const_args[2]) {
- int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
- tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
+ tcg_out_sari64(s, args[0], args[1], args[2]);
} else {
tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 08/29] tcg/ppc: Split out tcg_out_bswap16
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (6 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 07/29] tcg/ppc: Split out tcg_out_sari{32,64} Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 09/29] tcg/ppc: Split out tcg_out_bswap32 Richard Henderson
` (21 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-ppc
With the use of a suitable temporary, we can use the same
algorithm when src overlaps dst. The result is the same
number of instructions either way.
Cc: qemu-ppc@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 34 +++++++++++++++++++---------------
1 file changed, 19 insertions(+), 15 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 50347182d7..ad46ce32ca 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -789,6 +789,24 @@ static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c)
tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2));
}
+static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src)
+{
+ TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
+
+ /*
+ * In the following,
+ * dep(a, b, m) -> (a & ~m) | (b & m)
+ *
+ * Begin with: src = xxxxabcd
+ */
+ /* tmp = rol32(src, 24) & 0x000000ff = 0000000c */
+ tcg_out_rlw(s, RLWINM, tmp, src, 24, 24, 31);
+ /* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */
+ tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23);
+
+ tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
+}
+
/* Emit a move into ret of arg, if it can be done in one insn. */
static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
{
@@ -2779,21 +2797,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
- a0 = args[0], a1 = args[1];
- /* a1 = abcd */
- if (a0 != a1) {
- /* a0 = (a1 r<< 24) & 0xff # 000c */
- tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
- /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
- tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
- } else {
- /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
- /* a0 = (a1 r<< 24) & 0xff # 000c */
- tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
- /* a0 = a0 | r0 # 00dc */
- tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
- }
+ tcg_out_bswap16(s, args[0], args[1]);
break;
case INDEX_op_bswap32_i32:
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 09/29] tcg/ppc: Split out tcg_out_bswap32
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (7 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 08/29] tcg/ppc: Split out tcg_out_bswap16 Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 10/29] tcg/ppc: Split out tcg_out_bswap64 Richard Henderson
` (20 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-ppc
Cc: qemu-ppc@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 38 ++++++++++++++++++++++----------------
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index ad46ce32ca..28b8671cba 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -807,6 +807,27 @@ static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src)
tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
}
+static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src)
+{
+ TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
+
+ /*
+ * Stolen from gcc's builtin_bswap32.
+ * In the following,
+ * dep(a, b, m) -> (a & ~m) | (b & m)
+ *
+ * Begin with: src = xxxxabcd
+ */
+ /* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */
+ tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31);
+ /* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */
+ tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7);
+ /* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */
+ tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23);
+
+ tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
+}
+
/* Emit a move into ret of arg, if it can be done in one insn. */
static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
{
@@ -2799,24 +2820,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_bswap16_i64:
tcg_out_bswap16(s, args[0], args[1]);
break;
-
case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64:
- /* Stolen from gcc's builtin_bswap32 */
- a1 = args[1];
- a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
-
- /* a1 = args[1] # abcd */
- /* a0 = rotate_left (a1, 8) # bcda */
- tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
- /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
- tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
- /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
- tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
-
- if (a0 == TCG_REG_R0) {
- tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
- }
+ tcg_out_bswap32(s, args[0], args[1]);
break;
case INDEX_op_bswap64_i64:
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 10/29] tcg/ppc: Split out tcg_out_bswap64
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (8 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 09/29] tcg/ppc: Split out tcg_out_bswap32 Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 11/29] tcg/ppc: Support bswap flags Richard Henderson
` (19 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-ppc
Cc: qemu-ppc@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 64 +++++++++++++++++++++-------------------
1 file changed, 34 insertions(+), 30 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 28b8671cba..da6d10722e 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -828,6 +828,39 @@ static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src)
tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
}
+static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src)
+{
+ TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
+ TCGReg t1 = dst == src ? dst : TCG_REG_R0;
+
+ /*
+ * In the following,
+ * dep(a, b, m) -> (a & ~m) | (b & m)
+ *
+ * Begin with: src = abcdefgh
+ */
+ /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */
+ tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31);
+ /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */
+ tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7);
+ /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */
+ tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23);
+
+ /* t0 = rol64(t0, 32) = hgfe0000 */
+ tcg_out_rld(s, RLDICL, t0, t0, 32, 0);
+ /* t1 = rol64(src, 32) = efghabcd */
+ tcg_out_rld(s, RLDICL, t1, src, 32, 0);
+
+ /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */
+ tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31);
+ /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */
+ tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7);
+ /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */
+ tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23);
+
+ tcg_out_mov(s, TCG_TYPE_REG, dst, t0);
+}
+
/* Emit a move into ret of arg, if it can be done in one insn. */
static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
{
@@ -2824,37 +2857,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_bswap32_i64:
tcg_out_bswap32(s, args[0], args[1]);
break;
-
case INDEX_op_bswap64_i64:
- a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
- if (a0 == a1) {
- a0 = TCG_REG_R0;
- a2 = a1;
- }
-
- /* a1 = # abcd efgh */
- /* a0 = rl32(a1, 8) # 0000 fghe */
- tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
- /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
- tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
- /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
- tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
-
- /* a0 = rl64(a0, 32) # hgfe 0000 */
- /* a2 = rl64(a1, 32) # efgh abcd */
- tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
- tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
-
- /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
- tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
- /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
- tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
- /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
- tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
-
- if (a0 == 0) {
- tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
- }
+ tcg_out_bswap64(s, args[0], args[1]);
break;
case INDEX_op_deposit_i32:
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 11/29] tcg/ppc: Support bswap flags
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (9 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 10/29] tcg/ppc: Split out tcg_out_bswap64 Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 9:32 ` Philippe Mathieu-Daudé
2021-06-26 6:36 ` [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions Richard Henderson
` (18 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc
For INDEX_op_bswap32_i32, pass 0 for flags: input not zero-extended,
output does not need extension within the host 64-bit register.
Cc: qemu-ppc@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index da6d10722e..33f0139519 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -789,7 +789,7 @@ static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c)
tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2));
}
-static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src)
+static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags)
{
TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
@@ -804,10 +804,14 @@ static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src)
/* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */
tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23);
- tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
+ if (flags & TCG_BSWAP_OS) {
+ tcg_out_ext16s(s, dst, tmp);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
+ }
}
-static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src)
+static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags)
{
TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
@@ -825,7 +829,11 @@ static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src)
/* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */
tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23);
- tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
+ if (flags & TCG_BSWAP_OS) {
+ tcg_out_ext32s(s, dst, tmp);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_REG, dst, tmp);
+ }
}
static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src)
@@ -2851,11 +2859,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
- tcg_out_bswap16(s, args[0], args[1]);
+ tcg_out_bswap16(s, args[0], args[1], args[2]);
break;
case INDEX_op_bswap32_i32:
+ tcg_out_bswap32(s, args[0], args[1], 0);
+ break;
case INDEX_op_bswap32_i64:
- tcg_out_bswap32(s, args[0], args[1]);
+ tcg_out_bswap32(s, args[0], args[1], args[2]);
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, args[0], args[1]);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (10 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 11/29] tcg/ppc: Support bswap flags Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-28 14:33 ` Peter Maydell
2021-06-26 6:36 ` [PATCH v3 13/29] tcg/s390: Support bswap flags Richard Henderson
` (17 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc
Cc: qemu-ppc@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 33f0139519..e0f4665213 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -413,6 +413,10 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define SRAD XO31(794)
#define SRADI XO31(413<<1)
+#define BRH XO31(219)
+#define BRW XO31(155)
+#define BRD XO31(187)
+
#define TW XO31( 4)
#define TRAP (TW | TO(31))
@@ -748,6 +752,11 @@ static inline void tcg_out_ext16s(TCGContext *s, TCGReg dst, TCGReg src)
tcg_out32(s, EXTSH | RA(dst) | RS(src));
}
+static inline void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src)
+{
+ tcg_out32(s, ANDI | SAI(src, dst, 0xffff));
+}
+
static inline void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src)
{
tcg_out32(s, EXTSW | RA(dst) | RS(src));
@@ -793,6 +802,16 @@ static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags)
{
TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
+ if (have_isa_3_10) {
+ tcg_out32(s, BRH | RA(dst) | RS(src));
+ if (flags & TCG_BSWAP_OS) {
+ tcg_out_ext16s(s, dst, dst);
+ } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ tcg_out_ext16u(s, dst, dst);
+ }
+ return;
+ }
+
/*
* In the following,
* dep(a, b, m) -> (a & ~m) | (b & m)
@@ -815,6 +834,16 @@ static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags)
{
TCGReg tmp = dst == src ? TCG_REG_R0 : dst;
+ if (have_isa_3_10) {
+ tcg_out32(s, BRW | RA(dst) | RS(src));
+ if (flags & TCG_BSWAP_OS) {
+ tcg_out_ext32s(s, dst, dst);
+ } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ tcg_out_ext32u(s, dst, dst);
+ }
+ return;
+ }
+
/*
* Stolen from gcc's builtin_bswap32.
* In the following,
@@ -841,6 +870,11 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src)
TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
TCGReg t1 = dst == src ? dst : TCG_REG_R0;
+ if (have_isa_3_10) {
+ tcg_out32(s, BRD | RA(dst) | RS(src));
+ return;
+ }
+
/*
* In the following,
* dep(a, b, m) -> (a & ~m) | (b & m)
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 13/29] tcg/s390: Support bswap flags
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (11 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-28 14:43 ` Peter Maydell
2021-06-26 6:36 ` [PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16 Richard Henderson
` (16 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
For INDEX_op_bswap16_i64, use 64-bit instructions so that we can
easily provide the extension to 64-bits. Drop the special case,
previously used, where the input is already zero-extended -- the
minor code size savings is not worth the complication.
Cc: qemu-s390x@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++------
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 5fe073f09a..b82cf19f09 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -1951,15 +1951,37 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
break;
- OP_32_64(bswap16):
- /* The TCG bswap definition requires bits 0-47 already be zero.
- Thus we don't need the G-type insns to implement bswap16_i64. */
- tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
- tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16);
+ case INDEX_op_bswap16_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ tcg_out_insn(s, RRE, LRVR, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16);
+ } else {
+ tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16);
+ }
break;
- OP_32_64(bswap32):
+ case INDEX_op_bswap16_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ tcg_out_insn(s, RRE, LRVGR, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48);
+ } else {
+ tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48);
+ }
+ break;
+
+ case INDEX_op_bswap32_i32:
tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
break;
+ case INDEX_op_bswap32_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ tcg_out_insn(s, RRE, LRVR, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tgen_ext32s(s, a0, a0);
+ } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ tgen_ext32u(s, a0, a0);
+ }
+ break;
case INDEX_op_add2_i32:
if (const_args[4]) {
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (12 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 13/29] tcg/s390: Support bswap flags Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 9:30 ` Philippe Mathieu-Daudé
2021-06-26 6:36 ` [PATCH v3 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32 Richard Henderson
` (15 subsequent siblings)
29 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Merge tcg_out_bswap16 and tcg_out_bswap16s. Use the flags
in the internal uses for loads and stores.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 63 +++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 33 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 5944448b2a..a9f9f527f6 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -540,39 +540,37 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
}
}
-static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
+static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
{
+ /* ret and arg can't be register tmp0 */
+ tcg_debug_assert(ret != TCG_TMP0);
+ tcg_debug_assert(arg != TCG_TMP0);
+
+ /* With arg = abcd: */
if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
- } else {
- /* ret and arg can't be register at */
- if (ret == TCG_TMP0 || arg == TCG_TMP0) {
- tcg_abort();
+ tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
+ if (flags & TCG_BSWAP_OS) {
+ tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
+ } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
}
-
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
- tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
+ return;
}
-}
-static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
- tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
+ if (!(flags & TCG_BSWAP_IZ)) {
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
+ }
+ if (flags & TCG_BSWAP_OS) {
+ tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
+ tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
} else {
- /* ret and arg can't be register at */
- if (ret == TCG_TMP0 || arg == TCG_TMP0) {
- tcg_abort();
+ tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
+ if (flags & TCG_BSWAP_OZ) {
+ tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
}
-
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
- tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
}
+ tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
}
static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
@@ -1367,14 +1365,14 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
break;
case MO_UW | MO_BSWAP:
tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
- tcg_out_bswap16(s, lo, TCG_TMP1);
+ tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_UW:
tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
break;
case MO_SW | MO_BSWAP:
tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
- tcg_out_bswap16s(s, lo, TCG_TMP1);
+ tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS);
break;
case MO_SW:
tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
@@ -1514,8 +1512,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
break;
case MO_16 | MO_BSWAP:
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
- tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
+ tcg_out_bswap16(s, TCG_TMP1, lo, 0);
lo = TCG_TMP1;
/* FALLTHRU */
case MO_16:
@@ -1933,10 +1930,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_not_i64:
i1 = OPC_NOR;
goto do_unary;
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap16_i64:
- i1 = OPC_WSBH;
- goto do_unary;
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
i1 = OPC_SEB;
@@ -1948,6 +1941,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
break;
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ tcg_out_bswap16(s, a0, a1, a2);
+ break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, a0, a1);
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (13 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16 Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 16/29] tcg/tci: Support bswap flags Richard Henderson
` (14 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Merge tcg_out_bswap32 and tcg_out_bswap32s.
Use the flags in the internal uses for loads and stores.
For mips32r2 bswap32 with zero-extension, standardize on
WSBH+ROTR+DEXT. This is the same number of insns as the
previous DSBH+DSHD+DSRL but fits in better with the flags check.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 39 ++++++++++++++++-----------------------
1 file changed, 16 insertions(+), 23 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index a9f9f527f6..bf0eb84e2d 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -579,27 +579,20 @@ static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
tcg_debug_assert(ok);
}
-static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
+static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
{
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
+ if (flags & TCG_BSWAP_OZ) {
+ tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
+ }
} else {
- tcg_out_bswap_subr(s, bswap32_addr);
- /* delay slot -- never omit the insn, like tcg_out_mov might. */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
- tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
- }
-}
-
-static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
- tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
- tcg_out_dsrl(s, ret, ret, 32);
- } else {
- tcg_out_bswap_subr(s, bswap32u_addr);
+ if (flags & TCG_BSWAP_OZ) {
+ tcg_out_bswap_subr(s, bswap32u_addr);
+ } else {
+ tcg_out_bswap_subr(s, bswap32_addr);
+ }
/* delay slot -- never omit the insn, like tcg_out_mov might. */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
@@ -1381,7 +1374,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
if (TCG_TARGET_REG_BITS == 64 && is_64) {
if (use_mips32r2_instructions) {
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
- tcg_out_bswap32u(s, lo, lo);
+ tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
} else {
tcg_out_bswap_subr(s, bswap32u_addr);
/* delay slot */
@@ -1394,7 +1387,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
case MO_SL | MO_BSWAP:
if (use_mips32r2_instructions) {
tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
- tcg_out_bswap32(s, lo, lo);
+ tcg_out_bswap32(s, lo, lo, 0);
} else {
tcg_out_bswap_subr(s, bswap32_addr);
/* delay slot */
@@ -1520,7 +1513,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
break;
case MO_32 | MO_BSWAP:
- tcg_out_bswap32(s, TCG_TMP3, lo);
+ tcg_out_bswap32(s, TCG_TMP3, lo, 0);
lo = TCG_TMP3;
/* FALLTHRU */
case MO_32:
@@ -1539,9 +1532,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
} else {
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
+ tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
+ tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
}
break;
@@ -1946,10 +1939,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_bswap16(s, a0, a1, a2);
break;
case INDEX_op_bswap32_i32:
- tcg_out_bswap32(s, a0, a1);
+ tcg_out_bswap32(s, a0, a1, 0);
break;
case INDEX_op_bswap32_i64:
- tcg_out_bswap32u(s, a0, a1);
+ tcg_out_bswap32(s, a0, a1, a2);
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, a0, a1);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 16/29] tcg/tci: Support bswap flags
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (14 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32 Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 17/29] tcg: Handle new bswap flags during optimize Richard Henderson
` (13 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
The existing interpreter zero-extends, ignoring high bits.
Simply add a separate sign-extension opcode if required.
Ensure that the interpreter supports ext16s when bswap16 is enabled.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 3 ++-
tcg/tci/tcg-target.c.inc | 23 ++++++++++++++++++++---
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 71689d4a40..b672c7cae5 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -808,7 +808,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
regs[r0] = (int8_t)regs[r1];
break;
#endif
-#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
+#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 || \
+ TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
CASE_32_64(ext16s)
tci_args_rr(insn, &r0, &r1);
regs[r0] = (int16_t)regs[r1];
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 9651e7a8f1..0cb16aaa81 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -597,6 +597,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
+ TCGOpcode exts;
+
switch (opc) {
case INDEX_op_exit_tb:
tcg_out_op_p(s, opc, (void *)args[0]);
@@ -710,13 +712,28 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */
CASE_64(ext_i32)
CASE_64(extu_i32)
- CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */
- CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */
- CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */
CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */
+ case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
+ case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
tcg_out_op_rr(s, opc, args[0], args[1]);
break;
+ case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
+ exts = INDEX_op_ext16s_i32;
+ goto do_bswap;
+ case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
+ exts = INDEX_op_ext16s_i64;
+ goto do_bswap;
+ case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
+ exts = INDEX_op_ext32s_i64;
+ do_bswap:
+ /* The base tci bswaps zero-extend, and ignore high bits. */
+ tcg_out_op_rr(s, opc, args[0], args[1]);
+ if (args[2] & TCG_BSWAP_OS) {
+ tcg_out_op_rr(s, exts, args[0], args[0]);
+ }
+ break;
+
CASE_32_64(add2)
CASE_32_64(sub2)
tcg_out_op_rrrrrr(s, opc, args[0], args[1], args[2],
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 17/29] tcg: Handle new bswap flags during optimize
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (15 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 16/29] tcg/tci: Support bswap flags Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 18/29] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 Richard Henderson
` (12 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Notice when the input is known to be zero-extended and force
the TCG_BSWAP_IZ flag on. Honor the TCG_BSWAP_OS bit during
constant folding. Propagate the input to the output mask.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 51 insertions(+), 5 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 211a4209a0..9876ac52a8 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -355,10 +355,12 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
return (uint16_t)x;
CASE_OP_32_64(bswap16):
- return bswap16(x);
+ x = bswap16(x);
+ return y & TCG_BSWAP_OS ? (int16_t)x : x;
CASE_OP_32_64(bswap32):
- return bswap32(x);
+ x = bswap32(x);
+ return y & TCG_BSWAP_OS ? (int32_t)x : x;
case INDEX_op_bswap64_i64:
return bswap64(x);
@@ -1029,6 +1031,42 @@ void tcg_optimize(TCGContext *s)
}
break;
+ CASE_OP_32_64(bswap16):
+ mask = arg_info(op->args[1])->mask;
+ if (mask <= 0xffff) {
+ op->args[2] |= TCG_BSWAP_IZ;
+ }
+ mask = bswap16(mask);
+ switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
+ case TCG_BSWAP_OZ:
+ break;
+ case TCG_BSWAP_OS:
+ mask = (int16_t)mask;
+ break;
+ default: /* undefined high bits */
+ mask |= MAKE_64BIT_MASK(16, 48);
+ break;
+ }
+ break;
+
+ case INDEX_op_bswap32_i64:
+ mask = arg_info(op->args[1])->mask;
+ if (mask <= 0xffffffffu) {
+ op->args[2] |= TCG_BSWAP_IZ;
+ }
+ mask = bswap32(mask);
+ switch (op->args[2] & (TCG_BSWAP_OZ | TCG_BSWAP_OS)) {
+ case TCG_BSWAP_OZ:
+ break;
+ case TCG_BSWAP_OS:
+ mask = (int32_t)mask;
+ break;
+ default: /* undefined high bits */
+ mask |= MAKE_64BIT_MASK(32, 32);
+ break;
+ }
+ break;
+
default:
break;
}
@@ -1135,9 +1173,6 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(ext16s):
CASE_OP_32_64(ext16u):
CASE_OP_32_64(ctpop):
- CASE_OP_32_64(bswap16):
- CASE_OP_32_64(bswap32):
- case INDEX_op_bswap64_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
case INDEX_op_ext_i32_i64:
@@ -1151,6 +1186,17 @@ void tcg_optimize(TCGContext *s)
}
goto do_default;
+ CASE_OP_32_64(bswap16):
+ CASE_OP_32_64(bswap32):
+ case INDEX_op_bswap64_i64:
+ if (arg_is_const(op->args[1])) {
+ tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
+ op->args[2]);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
+ break;
+ }
+ goto do_default;
+
CASE_OP_32_64(add):
CASE_OP_32_64(sub):
CASE_OP_32_64(mul):
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 18/29] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (16 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 17/29] tcg: Handle new bswap flags during optimize Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 19/29] tcg: Make use of bswap flags in tcg_gen_qemu_ld_* Richard Henderson
` (11 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé
Implement the new semantics in the fallback expansion.
Change all callers to supply the flags that keep the
semantics unchanged locally.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op.h | 8 +--
target/arm/translate-a64.c | 12 ++--
target/arm/translate.c | 2 +-
target/i386/tcg/translate.c | 2 +-
target/mips/tcg/mxu_translate.c | 2 +-
target/s390x/translate.c | 4 +-
target/sh4/translate.c | 2 +-
tcg/tcg-op.c | 121 ++++++++++++++++++++++----------
8 files changed, 99 insertions(+), 54 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 1a2ae93758..2a654f350c 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -330,7 +330,7 @@ void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
-void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
+void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags);
void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
@@ -528,8 +528,8 @@ void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
+void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
+void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
@@ -1192,7 +1192,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
-#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
+#define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S)
#define tcg_gen_bswap_tl tcg_gen_bswap32_i32
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7f74d0e81a..f2641a37ba 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5437,15 +5437,15 @@ static void handle_rev32(DisasContext *s, unsigned int sf,
/* bswap32_i64 requires zero high word */
tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
- tcg_gen_bswap32_i64(tcg_rd, tcg_tmp);
+ tcg_gen_bswap32_i64(tcg_rd, tcg_tmp, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
- tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
+ tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);
tcg_temp_free_i64(tcg_tmp);
} else {
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
- tcg_gen_bswap32_i64(tcg_rd, tcg_rd);
+ tcg_gen_bswap32_i64(tcg_rd, tcg_rd, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
}
}
@@ -12453,10 +12453,12 @@ static void handle_rev(DisasContext *s, int opcode, bool u,
read_vec_element(s, tcg_tmp, rn, i, grp_size);
switch (grp_size) {
case MO_16:
- tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
+ tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp,
+ TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_32:
- tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
+ tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp,
+ TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_64:
tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9e2cca7707..669b0be578 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -355,7 +355,7 @@ void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
{
tcg_gen_ext16u_i32(var, var);
- tcg_gen_bswap16_i32(var, var);
+ tcg_gen_bswap16_i32(var, var, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_ext16s_i32(dest, var);
}
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index a7f5c0c8f2..e8a9dcd21a 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -7203,7 +7203,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
{
gen_op_mov_v_reg(s, MO_32, s->T0, reg);
tcg_gen_ext32u_tl(s->T0, s->T0);
- tcg_gen_bswap32_tl(s->T0, s->T0);
+ tcg_gen_bswap32_tl(s->T0, s->T0, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
gen_op_mov_reg_v(s, MO_32, reg, s->T0);
}
break;
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index fb0a811af6..c12cf78df7 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -861,7 +861,7 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
if (sel == 1) {
/* S32LDDR */
- tcg_gen_bswap32_tl(t1, t1);
+ tcg_gen_bswap32_tl(t1, t1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
}
gen_store_mxu_gpr(t1, XRa);
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index e243624d2a..03dab9f350 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -3939,13 +3939,13 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o)
static DisasJumpType op_rev16(DisasContext *s, DisasOps *o)
{
- tcg_gen_bswap16_i64(o->out, o->in2);
+ tcg_gen_bswap16_i64(o->out, o->in2, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
return DISAS_NEXT;
}
static DisasJumpType op_rev32(DisasContext *s, DisasOps *o)
{
- tcg_gen_bswap32_i64(o->out, o->in2);
+ tcg_gen_bswap32_i64(o->out, o->in2, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
return DISAS_NEXT;
}
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 9312790623..147219759b 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -677,7 +677,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv low = tcg_temp_new();
tcg_gen_ext16u_i32(low, REG(B7_4));
- tcg_gen_bswap16_i32(low, low);
+ tcg_gen_bswap16_i32(low, low, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
tcg_gen_deposit_i32(REG(B11_8), REG(B7_4), low, 0, 16);
tcg_temp_free(low);
}
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index dc65577e2f..949cbf2f03 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1001,20 +1001,35 @@ void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
}
}
-/* Note: we assume the two high bytes are set to zero */
-void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
+void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags)
{
+ /* Only one extension flag may be present. */
+ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));
+
if (TCG_TARGET_HAS_bswap16_i32) {
- tcg_gen_op3i_i32(INDEX_op_bswap16_i32, ret, arg,
- TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_op3i_i32(INDEX_op_bswap16_i32, ret, arg, flags);
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
- tcg_gen_ext8u_i32(t0, arg);
- tcg_gen_shli_i32(t0, t0, 8);
- tcg_gen_shri_i32(ret, arg, 8);
- tcg_gen_or_i32(ret, ret, t0);
+ tcg_gen_shri_i32(t0, arg, 8);
+ if (!(flags & TCG_BSWAP_IZ)) {
+ tcg_gen_ext8u_i32(t0, t0);
+ }
+
+ if (flags & TCG_BSWAP_OS) {
+ tcg_gen_shli_i32(t1, arg, 24);
+ tcg_gen_sari_i32(t1, t1, 16);
+ } else if (flags & TCG_BSWAP_OZ) {
+ tcg_gen_ext8u_i32(t1, arg);
+ tcg_gen_shli_i32(t1, t1, 8);
+ } else {
+ tcg_gen_shli_i32(t1, arg, 8);
+ }
+
+ tcg_gen_or_i32(ret, t0, t1);
tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
}
}
@@ -1655,51 +1670,79 @@ void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
}
}
-/* Note: we assume the six high bytes are set to zero */
-void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
+void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
{
+ /* Only one extension flag may be present. */
+ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));
+
if (TCG_TARGET_REG_BITS == 32) {
- tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
- tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
+ tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg), flags);
+ if (flags & TCG_BSWAP_OS) {
+ tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
+ } else {
+ tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
+ }
} else if (TCG_TARGET_HAS_bswap16_i64) {
- tcg_gen_op3i_i64(INDEX_op_bswap16_i64, ret, arg,
- TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_op3i_i64(INDEX_op_bswap16_i64, ret, arg, flags);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
- tcg_gen_ext8u_i64(t0, arg);
- tcg_gen_shli_i64(t0, t0, 8);
- tcg_gen_shri_i64(ret, arg, 8);
- tcg_gen_or_i64(ret, ret, t0);
+ tcg_gen_shri_i64(t0, arg, 8);
+ if (!(flags & TCG_BSWAP_IZ)) {
+ tcg_gen_ext8u_i64(t0, t0);
+ }
+
+ if (flags & TCG_BSWAP_OS) {
+ tcg_gen_shli_i64(t1, arg, 56);
+ tcg_gen_sari_i64(t1, t1, 48);
+ } else if (flags & TCG_BSWAP_OZ) {
+ tcg_gen_ext8u_i64(t1, arg);
+ tcg_gen_shli_i64(t1, t1, 8);
+ } else {
+ tcg_gen_shli_i64(t1, arg, 8);
+ }
+
+ tcg_gen_or_i64(ret, t0, t1);
tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
}
}
-/* Note: we assume the four high bytes are set to zero */
-void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
+void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags)
{
+ /* Only one extension flag may be present. */
+ tcg_debug_assert(!(flags & TCG_BSWAP_OS) || !(flags & TCG_BSWAP_OZ));
+
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
- tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
+ if (flags & TCG_BSWAP_OS) {
+ tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
+ } else {
+ tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
+ }
} else if (TCG_TARGET_HAS_bswap32_i64) {
- tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg,
- TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_op3i_i64(INDEX_op_bswap32_i64, ret, arg, flags);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_constant_i64(0x00ff00ff);
- /* arg = ....abcd */
- tcg_gen_shri_i64(t0, arg, 8); /* t0 = .....abc */
- tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */
- tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */
- tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */
- tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */
+ /* arg = xxxxabcd */
+ tcg_gen_shri_i64(t0, arg, 8); /* t0 = .xxxxabc */
+ tcg_gen_and_i64(t1, arg, t2); /* t1 = .....b.d */
+ tcg_gen_and_i64(t0, t0, t2); /* t0 = .....a.c */
+ tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. */
+ tcg_gen_or_i64(ret, t0, t1); /* ret = ....badc */
- tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */
- tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */
- tcg_gen_shri_i64(t1, t1, 32); /* t1 = ....dc.. */
- tcg_gen_or_i64(ret, t0, t1); /* ret = ....dcba */
+ tcg_gen_shli_i64(t1, ret, 48); /* t1 = dc...... */
+ tcg_gen_shri_i64(t0, ret, 16); /* t0 = ......ba */
+ if (flags & TCG_BSWAP_OS) {
+ tcg_gen_sari_i64(t1, t1, 32); /* t1 = ssssdc.. */
+ } else {
+ tcg_gen_shri_i64(t1, t1, 32); /* t1 = ....dc.. */
+ }
+ tcg_gen_or_i64(ret, t0, t1); /* ret = ssssdcba */
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
@@ -2846,7 +2889,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
if ((orig_memop ^ memop) & MO_BSWAP) {
switch (orig_memop & MO_SIZE) {
case MO_16:
- tcg_gen_bswap16_i32(val, val);
+ tcg_gen_bswap16_i32(val, val, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
if (orig_memop & MO_SIGN) {
tcg_gen_ext16s_i32(val, val);
}
@@ -2874,7 +2917,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
switch (memop & MO_SIZE) {
case MO_16:
tcg_gen_ext16u_i32(swap, val);
- tcg_gen_bswap16_i32(swap, swap);
+ tcg_gen_bswap16_i32(swap, swap, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_32:
tcg_gen_bswap32_i32(swap, val);
@@ -2935,13 +2978,13 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
if ((orig_memop ^ memop) & MO_BSWAP) {
switch (orig_memop & MO_SIZE) {
case MO_16:
- tcg_gen_bswap16_i64(val, val);
+ tcg_gen_bswap16_i64(val, val, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
if (orig_memop & MO_SIGN) {
tcg_gen_ext16s_i64(val, val);
}
break;
case MO_32:
- tcg_gen_bswap32_i64(val, val);
+ tcg_gen_bswap32_i64(val, val, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
if (orig_memop & MO_SIGN) {
tcg_gen_ext32s_i64(val, val);
}
@@ -2975,11 +3018,11 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
switch (memop & MO_SIZE) {
case MO_16:
tcg_gen_ext16u_i64(swap, val);
- tcg_gen_bswap16_i64(swap, swap);
+ tcg_gen_bswap16_i64(swap, swap, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_32:
tcg_gen_ext32u_i64(swap, val);
- tcg_gen_bswap32_i64(swap, swap);
+ tcg_gen_bswap32_i64(swap, swap, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_64:
tcg_gen_bswap64_i64(swap, val);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 19/29] tcg: Make use of bswap flags in tcg_gen_qemu_ld_*
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (17 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 18/29] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 20/29] tcg: Make use of bswap flags in tcg_gen_qemu_st_* Richard Henderson
` (10 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé
We can perform any required sign-extension via TCG_BSWAP_OS.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 949cbf2f03..0eac2d1969 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2876,7 +2876,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
orig_memop = memop;
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
memop &= ~MO_BSWAP;
- /* The bswap primitive requires zero-extended input. */
+ /* The bswap primitive benefits from zero-extended input. */
if ((memop & MO_SSIZE) == MO_SW) {
memop &= ~MO_SIGN;
}
@@ -2889,10 +2889,9 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
if ((orig_memop ^ memop) & MO_BSWAP) {
switch (orig_memop & MO_SIZE) {
case MO_16:
- tcg_gen_bswap16_i32(val, val, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- if (orig_memop & MO_SIGN) {
- tcg_gen_ext16s_i32(val, val);
- }
+ tcg_gen_bswap16_i32(val, val, (orig_memop & MO_SIGN
+ ? TCG_BSWAP_IZ | TCG_BSWAP_OS
+ : TCG_BSWAP_IZ | TCG_BSWAP_OZ));
break;
case MO_32:
tcg_gen_bswap32_i32(val, val);
@@ -2965,7 +2964,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
orig_memop = memop;
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
memop &= ~MO_BSWAP;
- /* The bswap primitive requires zero-extended input. */
+ /* The bswap primitive benefits from zero-extended input. */
if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) {
memop &= ~MO_SIGN;
}
@@ -2976,18 +2975,15 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
plugin_gen_mem_callbacks(addr, info);
if ((orig_memop ^ memop) & MO_BSWAP) {
+ int flags = (orig_memop & MO_SIGN
+ ? TCG_BSWAP_IZ | TCG_BSWAP_OS
+ : TCG_BSWAP_IZ | TCG_BSWAP_OZ);
switch (orig_memop & MO_SIZE) {
case MO_16:
- tcg_gen_bswap16_i64(val, val, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- if (orig_memop & MO_SIGN) {
- tcg_gen_ext16s_i64(val, val);
- }
+ tcg_gen_bswap16_i64(val, val, flags);
break;
case MO_32:
- tcg_gen_bswap32_i64(val, val, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- if (orig_memop & MO_SIGN) {
- tcg_gen_ext32s_i64(val, val);
- }
+ tcg_gen_bswap32_i64(val, val, flags);
break;
case MO_64:
tcg_gen_bswap64_i64(val, val);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 20/29] tcg: Make use of bswap flags in tcg_gen_qemu_st_*
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (18 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 19/29] tcg: Make use of bswap flags in tcg_gen_qemu_ld_* Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 21/29] target/arm: Improve REV32 Richard Henderson
` (9 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
By removing TCG_BSWAP_IZ we indicate that the input is
not zero-extended, and thus can remove an explicit extend.
By removing TCG_BSWAP_OZ, we allow the implementation to
leave high bits set, which will be ignored by the store.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 0eac2d1969..44d711c0fc 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2915,8 +2915,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
swap = tcg_temp_new_i32();
switch (memop & MO_SIZE) {
case MO_16:
- tcg_gen_ext16u_i32(swap, val);
- tcg_gen_bswap16_i32(swap, swap, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_bswap16_i32(swap, val, 0);
break;
case MO_32:
tcg_gen_bswap32_i32(swap, val);
@@ -3013,12 +3012,10 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
swap = tcg_temp_new_i64();
switch (memop & MO_SIZE) {
case MO_16:
- tcg_gen_ext16u_i64(swap, val);
- tcg_gen_bswap16_i64(swap, swap, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_bswap16_i64(swap, val, 0);
break;
case MO_32:
- tcg_gen_ext32u_i64(swap, val);
- tcg_gen_bswap32_i64(swap, swap, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_bswap32_i64(swap, val, 0);
break;
case MO_64:
tcg_gen_bswap64_i64(swap, val);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 21/29] target/arm: Improve REV32
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (19 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 20/29] tcg: Make use of bswap flags in tcg_gen_qemu_st_* Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 22/29] target/arm: Improve vector REV Richard Henderson
` (8 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé
For the sf version, we are performing two 32-bit bswaps
in either half of the register. This is equivalent to
performing one 64-bit bswap followed by a rotate.
For the non-sf version, we can remove TCG_BSWAP_IZ
and the preceding zero-extension.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 17 ++++-------------
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index f2641a37ba..304fd3d370 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5430,22 +5430,13 @@ static void handle_rev32(DisasContext *s, unsigned int sf,
unsigned int rn, unsigned int rd)
{
TCGv_i64 tcg_rd = cpu_reg(s, rd);
+ TCGv_i64 tcg_rn = cpu_reg(s, rn);
if (sf) {
- TCGv_i64 tcg_tmp = tcg_temp_new_i64();
- TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
-
- /* bswap32_i64 requires zero high word */
- tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
- tcg_gen_bswap32_i64(tcg_rd, tcg_tmp, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
- tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);
-
- tcg_temp_free_i64(tcg_tmp);
+ tcg_gen_bswap64_i64(tcg_rd, tcg_rn);
+ tcg_gen_rotri_i64(tcg_rd, tcg_rd, 32);
} else {
- tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
- tcg_gen_bswap32_i64(tcg_rd, tcg_rd, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_bswap32_i64(tcg_rd, tcg_rn, TCG_BSWAP_OZ);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 22/29] target/arm: Improve vector REV
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (20 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 21/29] target/arm: Improve REV32 Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 23/29] target/arm: Improve REVSH Richard Henderson
` (7 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé
We can eliminate the requirement for a zero-extended output,
because the following store will ignore any garbage high bits.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 304fd3d370..1a40e49db7 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -12444,12 +12444,10 @@ static void handle_rev(DisasContext *s, int opcode, bool u,
read_vec_element(s, tcg_tmp, rn, i, grp_size);
switch (grp_size) {
case MO_16:
- tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp,
- TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ);
break;
case MO_32:
- tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp,
- TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ);
break;
case MO_64:
tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 23/29] target/arm: Improve REVSH
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (21 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 22/29] target/arm: Improve vector REV Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 24/29] target/i386: Improve bswap translation Richard Henderson
` (6 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Philippe Mathieu-Daudé
The new bswap flags can implement the semantics exactly.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 669b0be578..a0c6cfa902 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -354,9 +354,7 @@ void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
/* Byteswap low halfword and sign extend. */
static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
{
- tcg_gen_ext16u_i32(var, var);
- tcg_gen_bswap16_i32(var, var, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- tcg_gen_ext16s_i32(dest, var);
+ tcg_gen_bswap16_i32(var, var, TCG_BSWAP_OS);
}
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 24/29] target/i386: Improve bswap translation
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (22 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 23/29] target/arm: Improve REVSH Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 25/29] target/sh4: Improve swap.b translation Richard Henderson
` (5 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Use a break instead of an ifdefed else.
There's no need to move the values through s->T0.
Remove TCG_BSWAP_IZ and the preceding zero-extension.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/translate.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index e8a9dcd21a..b21873ed23 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -7195,17 +7195,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
reg = (b & 7) | REX_B(s);
#ifdef TARGET_X86_64
if (dflag == MO_64) {
- gen_op_mov_v_reg(s, MO_64, s->T0, reg);
- tcg_gen_bswap64_i64(s->T0, s->T0);
- gen_op_mov_reg_v(s, MO_64, reg, s->T0);
- } else
-#endif
- {
- gen_op_mov_v_reg(s, MO_32, s->T0, reg);
- tcg_gen_ext32u_tl(s->T0, s->T0);
- tcg_gen_bswap32_tl(s->T0, s->T0, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- gen_op_mov_reg_v(s, MO_32, reg, s->T0);
+ tcg_gen_bswap64_i64(cpu_regs[reg], cpu_regs[reg]);
+ break;
}
+#endif
+ tcg_gen_bswap32_tl(cpu_regs[reg], cpu_regs[reg], TCG_BSWAP_OZ);
break;
case 0xd6: /* salc */
if (CODE64(s))
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 25/29] target/sh4: Improve swap.b translation
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (23 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 24/29] target/i386: Improve bswap translation Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 26/29] target/mips: Fix gen_mxu_s32ldd_s32lddr Richard Henderson
` (4 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Remove TCG_BSWAP_IZ and the preceding zero-extension.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 147219759b..4dcfff81f6 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -676,8 +676,7 @@ static void _decode_opc(DisasContext * ctx)
case 0x6008: /* swap.b Rm,Rn */
{
TCGv low = tcg_temp_new();
- tcg_gen_ext16u_i32(low, REG(B7_4));
- tcg_gen_bswap16_i32(low, low, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
+ tcg_gen_bswap16_i32(low, REG(B7_4), 0);
tcg_gen_deposit_i32(REG(B11_8), REG(B7_4), low, 0, 16);
tcg_temp_free(low);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 26/29] target/mips: Fix gen_mxu_s32ldd_s32lddr
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (24 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 25/29] target/sh4: Improve swap.b translation Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 27/29] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP Richard Henderson
` (3 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
There were two bugs here: (1) the required endianness was
not present in the MemOp, and (2) we were not providing a
zero-extended input to the bswap as semantics required.
The best fix is to fold the bswap into the memory operation,
producing the desired result directly.
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/mxu_translate.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index c12cf78df7..f4356432c7 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -857,12 +857,8 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
tcg_gen_ori_tl(t1, t1, 0xFFFFF000);
}
tcg_gen_add_tl(t1, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL);
+ tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP));
- if (sel == 1) {
- /* S32LDDR */
- tcg_gen_bswap32_tl(t1, t1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- }
gen_store_mxu_gpr(t1, XRa);
tcg_temp_free(t0);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 27/29] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (25 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 26/29] target/mips: Fix gen_mxu_s32ldd_s32lddr Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 28/29] tcg/aarch64: " Richard Henderson
` (2 subsequent siblings)
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
Now that the middle-end can replicate the same tricks as tcg/arm
used for optimizing bswap for signed loads and for stores, do not
pretend to have these memory ops in the backend.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 214 ++++++++++++++-------------------------
2 files changed, 77 insertions(+), 139 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 57fd0c0c74..95fcef33bc 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -174,7 +174,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
-#define TCG_TARGET_HAS_MEMORY_BSWAP 1
+#define TCG_TARGET_HAS_MEMORY_BSWAP 0
/* not defined -- call should be eliminated at compile time */
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 73e0455511..7a761a602e 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1393,34 +1393,38 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[16] = {
+static void * const qemu_ld_helpers[8] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
-
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_LESW] = helper_le_ldsw_mmu,
- [MO_LESL] = helper_le_ldul_mmu,
-
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
- [MO_BESW] = helper_be_ldsw_mmu,
- [MO_BESL] = helper_be_ldul_mmu,
+#ifdef HOST_WORDS_BIGENDIAN
+ [MO_UW] = helper_be_lduw_mmu,
+ [MO_UL] = helper_be_ldul_mmu,
+ [MO_Q] = helper_be_ldq_mmu,
+ [MO_SW] = helper_be_ldsw_mmu,
+ [MO_SL] = helper_be_ldul_mmu,
+#else
+ [MO_UW] = helper_le_lduw_mmu,
+ [MO_UL] = helper_le_ldul_mmu,
+ [MO_Q] = helper_le_ldq_mmu,
+ [MO_SW] = helper_le_ldsw_mmu,
+ [MO_SL] = helper_le_ldul_mmu,
+#endif
};
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
+static void * const qemu_st_helpers[4] = {
+ [MO_8] = helper_ret_stb_mmu,
+#ifdef HOST_WORDS_BIGENDIAN
+ [MO_16] = helper_be_stw_mmu,
+ [MO_32] = helper_be_stl_mmu,
+ [MO_64] = helper_be_stq_mmu,
+#else
+ [MO_16] = helper_le_stw_mmu,
+ [MO_32] = helper_le_stl_mmu,
+ [MO_64] = helper_le_stq_mmu,
+#endif
};
/* Helper routines for marshalling helper function arguments into
@@ -1625,9 +1629,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
icache usage. For pre-armv6, use the signed helpers since we do
not have a single insn sign-extend. */
if (use_armv6_instructions) {
- func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)];
+ func = qemu_ld_helpers[opc & MO_SIZE];
} else {
- func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)];
+ func = qemu_ld_helpers[opc & MO_SSIZE];
if (opc & MO_SIGN) {
opc = MO_UL;
}
@@ -1705,7 +1709,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
/* Tail-call to the helper, which will return to the fast path. */
- tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+ tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]);
return true;
}
#endif /* SOFTMMU */
@@ -1714,7 +1718,8 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addend)
{
- MemOp bswap = opc & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & MO_SSIZE) {
case MO_UB:
@@ -1725,51 +1730,30 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
break;
case MO_UW:
tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
- if (bswap) {
- tcg_out_bswap16(s, COND_AL, datalo, datalo,
- TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- }
break;
case MO_SW:
- if (bswap) {
- tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
- tcg_out_bswap16(s, COND_AL, datalo, datalo,
- TCG_BSWAP_IZ | TCG_BSWAP_OS);
- } else {
- tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
- }
+ tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
break;
case MO_UL:
- default:
tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend);
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, datalo, datalo);
- }
break;
case MO_Q:
- {
- TCGReg dl = (bswap ? datahi : datalo);
- TCGReg dh = (bswap ? datalo : datahi);
-
- /* Avoid ldrd for user-only emulation, to handle unaligned. */
- if (USING_SOFTMMU && use_armv6_instructions
- && (dl & 1) == 0 && dh == dl + 1) {
- tcg_out_ldrd_r(s, COND_AL, dl, addrlo, addend);
- } else if (dl != addend) {
- tcg_out_ld32_rwb(s, COND_AL, dl, addend, addrlo);
- tcg_out_ld32_12(s, COND_AL, dh, addend, 4);
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP,
- addend, addrlo, SHIFT_IMM_LSL(0));
- tcg_out_ld32_12(s, COND_AL, dl, TCG_REG_TMP, 0);
- tcg_out_ld32_12(s, COND_AL, dh, TCG_REG_TMP, 4);
- }
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, dl, dl);
- tcg_out_bswap32(s, COND_AL, dh, dh);
- }
+ /* Avoid ldrd for user-only emulation, to handle unaligned. */
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
+ tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
+ } else if (datalo != addend) {
+ tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
+ tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP,
+ addend, addrlo, SHIFT_IMM_LSL(0));
+ tcg_out_ld32_12(s, COND_AL, datalo, TCG_REG_TMP, 0);
+ tcg_out_ld32_12(s, COND_AL, datahi, TCG_REG_TMP, 4);
}
break;
+ default:
+ g_assert_not_reached();
}
}
@@ -1777,7 +1761,8 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo)
{
- MemOp bswap = opc & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & MO_SSIZE) {
case MO_UB:
@@ -1788,49 +1773,28 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,
break;
case MO_UW:
tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
- if (bswap) {
- tcg_out_bswap16(s, COND_AL, datalo, datalo,
- TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- }
break;
case MO_SW:
- if (bswap) {
- tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
- tcg_out_bswap16(s, COND_AL, datalo, datalo,
- TCG_BSWAP_IZ | TCG_BSWAP_OS);
- } else {
- tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
- }
+ tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
break;
case MO_UL:
- default:
tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, datalo, datalo);
- }
break;
case MO_Q:
- {
- TCGReg dl = (bswap ? datahi : datalo);
- TCGReg dh = (bswap ? datalo : datahi);
-
- /* Avoid ldrd for user-only emulation, to handle unaligned. */
- if (USING_SOFTMMU && use_armv6_instructions
- && (dl & 1) == 0 && dh == dl + 1) {
- tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0);
- } else if (dl == addrlo) {
- tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
- tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
- } else {
- tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
- tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
- }
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, dl, dl);
- tcg_out_bswap32(s, COND_AL, dh, dh);
- }
+ /* Avoid ldrd for user-only emulation, to handle unaligned. */
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
+ tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0);
+ } else if (datalo == addrlo) {
+ tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4);
+ tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
+ } else {
+ tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
+ tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4);
}
break;
+ default:
+ g_assert_not_reached();
}
}
@@ -1879,44 +1843,31 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addend)
{
- MemOp bswap = opc & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & MO_SIZE) {
case MO_8:
tcg_out_st8_r(s, cond, datalo, addrlo, addend);
break;
case MO_16:
- if (bswap) {
- tcg_out_bswap16(s, cond, TCG_REG_R0, datalo, 0);
- tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend);
- } else {
- tcg_out_st16_r(s, cond, datalo, addrlo, addend);
- }
+ tcg_out_st16_r(s, cond, datalo, addrlo, addend);
break;
case MO_32:
- default:
- if (bswap) {
- tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
- tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend);
- } else {
- tcg_out_st32_r(s, cond, datalo, addrlo, addend);
- }
+ tcg_out_st32_r(s, cond, datalo, addrlo, addend);
break;
case MO_64:
/* Avoid strd for user-only emulation, to handle unaligned. */
- if (bswap) {
- tcg_out_bswap32(s, cond, TCG_REG_R0, datahi);
- tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo);
- tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
- tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4);
- } else if (USING_SOFTMMU && use_armv6_instructions
- && (datalo & 1) == 0 && datahi == datalo + 1) {
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
tcg_out_strd_r(s, cond, datalo, addrlo, addend);
} else {
tcg_out_st32_rwb(s, cond, datalo, addend, addrlo);
tcg_out_st32_12(s, cond, datahi, addend, 4);
}
break;
+ default:
+ g_assert_not_reached();
}
}
@@ -1924,44 +1875,31 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo)
{
- MemOp bswap = opc & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & MO_SIZE) {
case MO_8:
tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);
break;
case MO_16:
- if (bswap) {
- tcg_out_bswap16(s, COND_AL, TCG_REG_R0, datalo, 0);
- tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0);
- } else {
- tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
- }
+ tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
break;
case MO_32:
- default:
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
- tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
- } else {
- tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
- }
+ tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
break;
case MO_64:
/* Avoid strd for user-only emulation, to handle unaligned. */
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi);
- tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
- tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
- tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4);
- } else if (USING_SOFTMMU && use_armv6_instructions
- && (datalo & 1) == 0 && datahi == datalo + 1) {
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0);
} else {
tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4);
}
break;
+ default:
+ g_assert_not_reached();
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 28/29] tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAP
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (26 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 27/29] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 29/29] tcg/riscv: Remove MO_BSWAP handling Richard Henderson
2021-06-26 7:03 ` [PATCH v3 00/29] tcg: bswap improvements no-reply
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell
The memory bswap support in the aarch64 backend merely dates from
a time when it was required. There is nothing special about the
backend support that could not have been provided by the middle-end
even prior to the introduction of the bswap flags.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 2 +-
tcg/aarch64/tcg-target.c.inc | 87 +++++++++++++-----------------------
2 files changed, 32 insertions(+), 57 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index ef55f7c185..551baf8da3 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -148,7 +148,7 @@ typedef enum {
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
-#define TCG_TARGET_HAS_MEMORY_BSWAP 1
+#define TCG_TARGET_HAS_MEMORY_BSWAP 0
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 72aa7e0e74..5924977b42 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1547,28 +1547,34 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
+static void * const qemu_ld_helpers[4] = {
+ [MO_8] = helper_ret_ldub_mmu,
+#ifdef HOST_WORDS_BIGENDIAN
+ [MO_16] = helper_be_lduw_mmu,
+ [MO_32] = helper_be_ldul_mmu,
+ [MO_64] = helper_be_ldq_mmu,
+#else
+ [MO_16] = helper_le_lduw_mmu,
+ [MO_32] = helper_le_ldul_mmu,
+ [MO_64] = helper_le_ldq_mmu,
+#endif
};
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, TCGMemOpIdx oi,
* uintptr_t ra)
*/
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
+static void * const qemu_st_helpers[4] = {
+ [MO_8] = helper_ret_stb_mmu,
+#ifdef HOST_WORDS_BIGENDIAN
+ [MO_16] = helper_be_stw_mmu,
+ [MO_32] = helper_be_stl_mmu,
+ [MO_64] = helper_be_stq_mmu,
+#else
+ [MO_16] = helper_le_stw_mmu,
+ [MO_32] = helper_le_stl_mmu,
+ [MO_64] = helper_le_stq_mmu,
+#endif
};
static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
@@ -1592,7 +1598,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi);
tcg_out_adr(s, TCG_REG_X3, lb->raddr);
- tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+ tcg_out_call(s, qemu_ld_helpers[opc & MO_SIZE]);
if (opc & MO_SIGN) {
tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0);
} else {
@@ -1618,7 +1624,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi);
tcg_out_adr(s, TCG_REG_X4, lb->raddr);
- tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+ tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE]);
tcg_out_goto(s, lb->raddr);
return true;
}
@@ -1714,7 +1720,8 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
TCGReg data_r, TCGReg addr_r,
TCGType otype, TCGReg off_r)
{
- const MemOp bswap = memop & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((memop & MO_BSWAP) == 0);
switch (memop & MO_SSIZE) {
case MO_UB:
@@ -1726,40 +1733,19 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
break;
case MO_UW:
tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
- if (bswap) {
- tcg_out_rev(s, TCG_TYPE_I32, MO_16, data_r, data_r);
- }
break;
case MO_SW:
- if (bswap) {
- tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
- tcg_out_rev(s, TCG_TYPE_I32, MO_16, data_r, data_r);
- tcg_out_sxt(s, ext, MO_16, data_r, data_r);
- } else {
- tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
- data_r, addr_r, otype, off_r);
- }
+ tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
+ data_r, addr_r, otype, off_r);
break;
case MO_UL:
tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
- if (bswap) {
- tcg_out_rev(s, TCG_TYPE_I32, MO_32, data_r, data_r);
- }
break;
case MO_SL:
- if (bswap) {
- tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
- tcg_out_rev(s, TCG_TYPE_I32, MO_32, data_r, data_r);
- tcg_out_sxt(s, TCG_TYPE_I64, MO_32, data_r, data_r);
- } else {
- tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
- }
+ tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
break;
case MO_Q:
tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
- if (bswap) {
- tcg_out_rev(s, TCG_TYPE_I64, MO_64, data_r, data_r);
- }
break;
default:
tcg_abort();
@@ -1770,31 +1756,20 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
TCGReg data_r, TCGReg addr_r,
TCGType otype, TCGReg off_r)
{
- const MemOp bswap = memop & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((memop & MO_BSWAP) == 0);
switch (memop & MO_SIZE) {
case MO_8:
tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
break;
case MO_16:
- if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev(s, TCG_TYPE_I32, MO_16, TCG_REG_TMP, data_r);
- data_r = TCG_REG_TMP;
- }
tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
break;
case MO_32:
- if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev(s, TCG_TYPE_I32, MO_32, TCG_REG_TMP, data_r);
- data_r = TCG_REG_TMP;
- }
tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
break;
case MO_64:
- if (bswap && data_r != TCG_REG_XZR) {
- tcg_out_rev(s, TCG_TYPE_I64, MO_64, TCG_REG_TMP, data_r);
- data_r = TCG_REG_TMP;
- }
tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
break;
default:
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v3 29/29] tcg/riscv: Remove MO_BSWAP handling
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (27 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 28/29] tcg/aarch64: " Richard Henderson
@ 2021-06-26 6:36 ` Richard Henderson
2021-06-26 7:03 ` [PATCH v3 00/29] tcg: bswap improvements no-reply
29 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-26 6:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis
TCG_TARGET_HAS_MEMORY_BSWAP is already unset for this backend,
which means that MO_BSWAP be handled by the middle-end and
will never be seen by the backend. Thus the indexes used with
qemu_{ld,st}_helpers will always be zero.
Tidy the comments and asserts in tcg_out_qemu_{ld,st}_direct.
It is not that we do not handle bswap "yet", but never will.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 64 ++++++++++++++++++++------------------
1 file changed, 33 insertions(+), 31 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index da7eecafc5..c16f96b401 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -852,37 +852,43 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[16] = {
- [MO_UB] = helper_ret_ldub_mmu,
- [MO_SB] = helper_ret_ldsb_mmu,
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LESW] = helper_le_ldsw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
+static void * const qemu_ld_helpers[8] = {
+ [MO_UB] = helper_ret_ldub_mmu,
+ [MO_SB] = helper_ret_ldsb_mmu,
+#ifdef HOST_WORDS_BIGENDIAN
+ [MO_UW] = helper_be_lduw_mmu,
+ [MO_SW] = helper_be_ldsw_mmu,
+ [MO_UL] = helper_be_ldul_mmu,
#if TCG_TARGET_REG_BITS == 64
- [MO_LESL] = helper_le_ldsl_mmu,
+ [MO_SL] = helper_be_ldsl_mmu,
#endif
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BESW] = helper_be_ldsw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
+ [MO_Q] = helper_be_ldq_mmu,
+#else
+ [MO_UW] = helper_le_lduw_mmu,
+ [MO_SW] = helper_le_ldsw_mmu,
+ [MO_UL] = helper_le_ldul_mmu,
#if TCG_TARGET_REG_BITS == 64
- [MO_BESL] = helper_be_ldsl_mmu,
+ [MO_SL] = helper_le_ldsl_mmu,
+#endif
+ [MO_Q] = helper_le_ldq_mmu,
#endif
- [MO_BEQ] = helper_be_ldq_mmu,
};
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, TCGMemOpIdx oi,
* uintptr_t ra)
*/
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
+static void * const qemu_st_helpers[4] = {
+ [MO_8] = helper_ret_stb_mmu,
+#ifdef HOST_WORDS_BIGENDIAN
+ [MO_16] = helper_be_stw_mmu,
+ [MO_32] = helper_be_stl_mmu,
+ [MO_64] = helper_be_stq_mmu,
+#else
+ [MO_16] = helper_le_stw_mmu,
+ [MO_32] = helper_le_stl_mmu,
+ [MO_64] = helper_le_stq_mmu,
+#endif
};
/* We don't support oversize guests */
@@ -997,7 +1003,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
tcg_out_movi(s, TCG_TYPE_PTR, a2, oi);
tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr);
- tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
+ tcg_out_call(s, qemu_ld_helpers[opc & MO_SSIZE]);
tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
tcg_out_goto(s, l->raddr);
@@ -1042,7 +1048,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
tcg_out_movi(s, TCG_TYPE_PTR, a3, oi);
tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr);
- tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
+ tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE]);
tcg_out_goto(s, l->raddr);
return true;
@@ -1052,10 +1058,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
TCGReg base, MemOp opc, bool is_64)
{
- const MemOp bswap = opc & MO_BSWAP;
-
- /* We don't yet handle byteswapping, assert */
- g_assert(!bswap);
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & (MO_SSIZE)) {
case MO_UB:
@@ -1139,10 +1143,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
TCGReg base, MemOp opc)
{
- const MemOp bswap = opc & MO_BSWAP;
-
- /* We don't yet handle byteswapping, assert */
- g_assert(!bswap);
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & (MO_SSIZE)) {
case MO_8:
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v3 00/29] tcg: bswap improvements
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
` (28 preceding siblings ...)
2021-06-26 6:36 ` [PATCH v3 29/29] tcg/riscv: Remove MO_BSWAP handling Richard Henderson
@ 2021-06-26 7:03 ` no-reply
29 siblings, 0 replies; 40+ messages in thread
From: no-reply @ 2021-06-26 7:03 UTC (permalink / raw)
To: richard.henderson; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/20210626063631.2411938-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210626063631.2411938-1-richard.henderson@linaro.org
Subject: [PATCH v3 00/29] tcg: bswap improvements
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20210625112741.12566-1-alex.bennee@linaro.org -> patchew/20210625112741.12566-1-alex.bennee@linaro.org
* [new tag] patchew/20210626063631.2411938-1-richard.henderson@linaro.org -> patchew/20210626063631.2411938-1-richard.henderson@linaro.org
Switched to a new branch 'test'
e51efe0 tcg/riscv: Remove MO_BSWAP handling
4041b9f tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAP
f136558 tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP
bcdc1b2 target/mips: Fix gen_mxu_s32ldd_s32lddr
6a4cd59 target/sh4: Improve swap.b translation
8477587 target/i386: Improve bswap translation
26ccc66 target/arm: Improve REVSH
da8e43e target/arm: Improve vector REV
fa6d277 target/arm: Improve REV32
88f5dcd tcg: Make use of bswap flags in tcg_gen_qemu_st_*
b0a635f tcg: Make use of bswap flags in tcg_gen_qemu_ld_*
3d607ce tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64
5357a0f tcg: Handle new bswap flags during optimize
bdb935c tcg/tci: Support bswap flags
af073d6 tcg/mips: Support bswap flags in tcg_out_bswap32
175d16f tcg/mips: Support bswap flags in tcg_out_bswap16
44fa033 tcg/s390: Support bswap flags
4399baa tcg/ppc: Use power10 byte-reverse instructions
54fe3bc tcg/ppc: Support bswap flags
44cc7ec tcg/ppc: Split out tcg_out_bswap64
012d7ff tcg/ppc: Split out tcg_out_bswap32
c10c9c8 tcg/ppc: Split out tcg_out_bswap16
1a8ab31 tcg/ppc: Split out tcg_out_sari{32,64}
70c6864 tcg/ppc: Split out tcg_out_ext{8,16,32}s
ec5717b tcg/arm: Support bswap flags
935c80a tcg/aarch64: Support bswap flags
d4e209d tcg/aarch64: Merge tcg_out_rev{16,32,64}
6697c42 tcg/i386: Support bswap flags
0b04ca4 tcg: Add flags argument to bswap opcodes
=== OUTPUT BEGIN ===
1/29 Checking commit 0b04ca4453f6 (tcg: Add flags argument to bswap opcodes)
2/29 Checking commit 6697c42f1198 (tcg/i386: Support bswap flags)
3/29 Checking commit d4e209dd23d4 (tcg/aarch64: Merge tcg_out_rev{16,32,64})
4/29 Checking commit 935c80acf207 (tcg/aarch64: Support bswap flags)
5/29 Checking commit ec5717bed008 (tcg/arm: Support bswap flags)
6/29 Checking commit 70c6864db927 (tcg/ppc: Split out tcg_out_ext{8,16,32}s)
7/29 Checking commit 1a8ab31694c7 (tcg/ppc: Split out tcg_out_sari{32,64})
8/29 Checking commit c10c9c82f0ce (tcg/ppc: Split out tcg_out_bswap16)
9/29 Checking commit 012d7ff11df3 (tcg/ppc: Split out tcg_out_bswap32)
10/29 Checking commit 44cc7ec9595f (tcg/ppc: Split out tcg_out_bswap64)
11/29 Checking commit 54fe3bceabce (tcg/ppc: Support bswap flags)
12/29 Checking commit 4399baae7d7f (tcg/ppc: Use power10 byte-reverse instructions)
13/29 Checking commit 44fa033dda86 (tcg/s390: Support bswap flags)
14/29 Checking commit 175d16f1fd15 (tcg/mips: Support bswap flags in tcg_out_bswap16)
15/29 Checking commit af073d696654 (tcg/mips: Support bswap flags in tcg_out_bswap32)
16/29 Checking commit bdb935c7d39b (tcg/tci: Support bswap flags)
17/29 Checking commit 5357a0ff6ff5 (tcg: Handle new bswap flags during optimize)
ERROR: spaces required around that ':' (ctx:VxE)
#41: FILE: tcg/optimize.c:1034:
+ CASE_OP_32_64(bswap16):
^
ERROR: spaces required around that ':' (ctx:VxE)
#94: FILE: tcg/optimize.c:1189:
+ CASE_OP_32_64(bswap16):
^
ERROR: spaces required around that ':' (ctx:VxE)
#95: FILE: tcg/optimize.c:1190:
+ CASE_OP_32_64(bswap32):
^
total: 3 errors, 0 warnings, 82 lines checked
Patch 17/29 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
18/29 Checking commit 3d607ce1c6ac (tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64)
ERROR: code indent should never use tabs
#165: FILE: target/sh4/translate.c:680:
+^I tcg_gen_bswap16_i32(low, low, TCG_BSWAP_IZ | TCG_BSWAP_OZ);$
total: 1 errors, 0 warnings, 296 lines checked
Patch 18/29 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/29 Checking commit b0a635f9e25a (tcg: Make use of bswap flags in tcg_gen_qemu_ld_*)
20/29 Checking commit 88f5dcdc4280 (tcg: Make use of bswap flags in tcg_gen_qemu_st_*)
21/29 Checking commit fa6d27781f5f (target/arm: Improve REV32)
22/29 Checking commit da8e43eac2ba (target/arm: Improve vector REV)
23/29 Checking commit 26ccc66ebc4b (target/arm: Improve REVSH)
24/29 Checking commit 8477587068bc (target/i386: Improve bswap translation)
25/29 Checking commit 6a4cd599d50a (target/sh4: Improve swap.b translation)
26/29 Checking commit bcdc1b2217ec (target/mips: Fix gen_mxu_s32ldd_s32lddr)
27/29 Checking commit f1365589a988 (tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP)
28/29 Checking commit 4041b9ff6ac3 (tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAP)
29/29 Checking commit e51efe0c6b8b (tcg/riscv: Remove MO_BSWAP handling)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210626063631.2411938-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16
2021-06-26 6:36 ` [PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16 Richard Henderson
@ 2021-06-26 9:30 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-26 9:30 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/26/21 8:36 AM, Richard Henderson wrote:
> Merge tcg_out_bswap16 and tcg_out_bswap16s. Use the flags
> in the internal uses for loads and stores.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/mips/tcg-target.c.inc | 63 +++++++++++++++++++--------------------
> 1 file changed, 30 insertions(+), 33 deletions(-)
> -static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
> +static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
> {
> + /* ret and arg can't be register tmp0 */
> + tcg_debug_assert(ret != TCG_TMP0);
> + tcg_debug_assert(arg != TCG_TMP0);
> +
> + /* With arg = abcd: */
> if (use_mips32r2_instructions) {
> - tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
> - } else {
> - /* ret and arg can't be register at */
> - if (ret == TCG_TMP0 || arg == TCG_TMP0) {
> - tcg_abort();
> + tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
> + if (flags & TCG_BSWAP_OS) {
> + tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
> + } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
> + tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
> }
> -
> - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
> - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
> - tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
> - tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
> + return;
> }
> -}
>
> -static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
> -{
> - if (use_mips32r2_instructions) {
> - tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
> - tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
> + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
> + if (!(flags & TCG_BSWAP_IZ)) {
> + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
> + }
> + if (flags & TCG_BSWAP_OS) {
> + tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
> + tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
> } else {
> - /* ret and arg can't be register at */
> - if (ret == TCG_TMP0 || arg == TCG_TMP0) {
> - tcg_abort();
> + tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
> + if (flags & TCG_BSWAP_OZ) {
> + tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
> }
> -
> - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
> - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
> - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
> - tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
> }
> + tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
> }
Thanks for adding the comments!
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v3 11/29] tcg/ppc: Support bswap flags
2021-06-26 6:36 ` [PATCH v3 11/29] tcg/ppc: Support bswap flags Richard Henderson
@ 2021-06-26 9:32 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-26 9:32 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-ppc
On 6/26/21 8:36 AM, Richard Henderson wrote:
> For INDEX_op_bswap32_i32, pass 0 for flags: input not zero-extended,
> output does not need extension within the host 64-bit register.
>
> Cc: qemu-ppc@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/ppc/tcg-target.c.inc | 22 ++++++++++++++++------
> 1 file changed, 16 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v3 04/29] tcg/aarch64: Support bswap flags
2021-06-26 6:36 ` [PATCH v3 04/29] tcg/aarch64: Support bswap flags Richard Henderson
@ 2021-06-26 9:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 40+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-26 9:38 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Peter Maydell
On 6/26/21 8:36 AM, Richard Henderson wrote:
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target.c.inc | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v3 03/29] tcg/aarch64: Merge tcg_out_rev{16,32,64}
2021-06-26 6:36 ` [PATCH v3 03/29] tcg/aarch64: Merge tcg_out_rev{16,32,64} Richard Henderson
@ 2021-06-28 14:16 ` Peter Maydell
0 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2021-06-28 14:16 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Sat, 26 Jun 2021 at 07:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Pass in the input and output size. We currently use 3 of the 5
> possible combinations; the others may be used by new tcg opcodes.
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target.c.inc | 42 ++++++++++++++----------------------
> 1 file changed, 16 insertions(+), 26 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions
2021-06-26 6:36 ` [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions Richard Henderson
@ 2021-06-28 14:33 ` Peter Maydell
2021-06-28 14:45 ` Richard Henderson
0 siblings, 1 reply; 40+ messages in thread
From: Peter Maydell @ 2021-06-28 14:33 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-ppc, QEMU Developers
On Sat, 26 Jun 2021 at 07:41, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Cc: qemu-ppc@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/ppc/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> + if (have_isa_3_10) {
Side note, why do we call this have_isa_3_10 when it's checking
for ISA 3.1, not 3.10 ? The kernel calls its feature bit
#define PPC_FEATURE2_ARCH_3_1 0x00040000 /* ISA 3.1 */
but we seem to have gone for
#define PPC_FEATURE2_ARCH_3_10 0x00040000
in our elf.h.
thanks
-- PMM
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v3 13/29] tcg/s390: Support bswap flags
2021-06-26 6:36 ` [PATCH v3 13/29] tcg/s390: Support bswap flags Richard Henderson
@ 2021-06-28 14:43 ` Peter Maydell
2021-06-28 14:50 ` Richard Henderson
0 siblings, 1 reply; 40+ messages in thread
From: Peter Maydell @ 2021-06-28 14:43 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-s390x, QEMU Developers
On Sat, 26 Jun 2021 at 07:44, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> For INDEX_op_bswap16_i64, use 64-bit instructions so that we can
> easily provide the extension to 64-bits. Drop the special case,
> previously used, where the input is already zero-extended -- the
> minor code size savings is not worth the complication.
>
> Cc: qemu-s390x@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> + case INDEX_op_bswap32_i32:
> tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
> break;
When we're working with i32s, is the top half of the host register
zero or garbage ? I guess either way LRVR does the right thing.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions
2021-06-28 14:33 ` Peter Maydell
@ 2021-06-28 14:45 ` Richard Henderson
2021-06-28 16:22 ` Bruno Piazera Larsen
0 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2021-06-28 14:45 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-ppc, QEMU Developers
On 6/28/21 7:33 AM, Peter Maydell wrote:
>> + if (have_isa_3_10) {
>
> Side note, why do we call this have_isa_3_10 when it's checking
> for ISA 3.1, not 3.10 ?
I think it's just because it made the columns line up:
#define have_isa_2_06 (have_isa >= tcg_isa_2_06)
#define have_isa_2_07 (have_isa >= tcg_isa_2_07)
#define have_isa_3_00 (have_isa >= tcg_isa_3_00)
#define have_isa_3_10 (have_isa >= tcg_isa_3_10)
though I think there's also a missing . or _ there -- should have been 2.0.6 and 2.0.7.
r~
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v3 13/29] tcg/s390: Support bswap flags
2021-06-28 14:43 ` Peter Maydell
@ 2021-06-28 14:50 ` Richard Henderson
0 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-06-28 14:50 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-s390x, QEMU Developers
On 6/28/21 7:43 AM, Peter Maydell wrote:
> On Sat, 26 Jun 2021 at 07:44, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> For INDEX_op_bswap16_i64, use 64-bit instructions so that we can
>> easily provide the extension to 64-bits. Drop the special case,
>> previously used, where the input is already zero-extended -- the
>> minor code size savings is not worth the complication.
>>
>> Cc: qemu-s390x@nongnu.org
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>
>> + case INDEX_op_bswap32_i32:
>> tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
>> break;
>
> When we're working with i32s, is the top half of the host register
> zero or garbage ?
The general case on s390x is that the top half of the host register is unmodified by insns
with 32-bit operands. This is true for LRVR.
It's also true for LRVRH, with its 16-bit operand. Which is why it's not as useful as it
could be.
r~
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions
2021-06-28 14:45 ` Richard Henderson
@ 2021-06-28 16:22 ` Bruno Piazera Larsen
0 siblings, 0 replies; 40+ messages in thread
From: Bruno Piazera Larsen @ 2021-06-28 16:22 UTC (permalink / raw)
To: Richard Henderson, Peter Maydell; +Cc: qemu-ppc, QEMU Developers
[-- Attachment #1: Type: text/plain, Size: 1232 bytes --]
On 28/06/2021 11:45, Richard Henderson wrote:
> On 6/28/21 7:33 AM, Peter Maydell wrote:
>>> + if (have_isa_3_10) {
>>
>> Side note, why do we call this have_isa_3_10 when it's checking
>> for ISA 3.1, not 3.10 ?
>
> I think it's just because it made the columns line up:
>
> #define have_isa_2_06 (have_isa >= tcg_isa_2_06)
> #define have_isa_2_07 (have_isa >= tcg_isa_2_07)
> #define have_isa_3_00 (have_isa >= tcg_isa_3_00)
> #define have_isa_3_10 (have_isa >= tcg_isa_3_10)
>
> though I think there's also a missing . or _ there -- should have been
> 2.0.6 and 2.0.7.
No. The specifications in the Open Power foundation's websites call the
versions
2.07:
https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b
and 2.06: http://kib.kiev.ua/x86docs/POWER/PowerISA_V2.06B_V2_PUBLIC.pdf
Unless the PDFs also lost a . somewhere, which isn't impossible, but I
find more unlikely.
>
>
> r~
>
--
Bruno Piazera Larsen
Instituto de Pesquisas ELDORADO
<https://www.eldorado.org.br/?utm_campaign=assinatura_de_e-mail&utm_medium=email&utm_source=RD+Station>
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
[-- Attachment #2: Type: text/html, Size: 2458 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2021-06-28 16:25 UTC | newest]
Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-26 6:36 [PATCH v3 00/29] tcg: bswap improvements Richard Henderson
2021-06-26 6:36 ` [PATCH v3 01/29] tcg: Add flags argument to bswap opcodes Richard Henderson
2021-06-26 6:36 ` [PATCH v3 02/29] tcg/i386: Support bswap flags Richard Henderson
2021-06-26 6:36 ` [PATCH v3 03/29] tcg/aarch64: Merge tcg_out_rev{16,32,64} Richard Henderson
2021-06-28 14:16 ` Peter Maydell
2021-06-26 6:36 ` [PATCH v3 04/29] tcg/aarch64: Support bswap flags Richard Henderson
2021-06-26 9:38 ` Philippe Mathieu-Daudé
2021-06-26 6:36 ` [PATCH v3 05/29] tcg/arm: " Richard Henderson
2021-06-26 6:36 ` [PATCH v3 06/29] tcg/ppc: Split out tcg_out_ext{8,16,32}s Richard Henderson
2021-06-26 6:36 ` [PATCH v3 07/29] tcg/ppc: Split out tcg_out_sari{32,64} Richard Henderson
2021-06-26 6:36 ` [PATCH v3 08/29] tcg/ppc: Split out tcg_out_bswap16 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 09/29] tcg/ppc: Split out tcg_out_bswap32 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 10/29] tcg/ppc: Split out tcg_out_bswap64 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 11/29] tcg/ppc: Support bswap flags Richard Henderson
2021-06-26 9:32 ` Philippe Mathieu-Daudé
2021-06-26 6:36 ` [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions Richard Henderson
2021-06-28 14:33 ` Peter Maydell
2021-06-28 14:45 ` Richard Henderson
2021-06-28 16:22 ` Bruno Piazera Larsen
2021-06-26 6:36 ` [PATCH v3 13/29] tcg/s390: Support bswap flags Richard Henderson
2021-06-28 14:43 ` Peter Maydell
2021-06-28 14:50 ` Richard Henderson
2021-06-26 6:36 ` [PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16 Richard Henderson
2021-06-26 9:30 ` Philippe Mathieu-Daudé
2021-06-26 6:36 ` [PATCH v3 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 16/29] tcg/tci: Support bswap flags Richard Henderson
2021-06-26 6:36 ` [PATCH v3 17/29] tcg: Handle new bswap flags during optimize Richard Henderson
2021-06-26 6:36 ` [PATCH v3 18/29] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 19/29] tcg: Make use of bswap flags in tcg_gen_qemu_ld_* Richard Henderson
2021-06-26 6:36 ` [PATCH v3 20/29] tcg: Make use of bswap flags in tcg_gen_qemu_st_* Richard Henderson
2021-06-26 6:36 ` [PATCH v3 21/29] target/arm: Improve REV32 Richard Henderson
2021-06-26 6:36 ` [PATCH v3 22/29] target/arm: Improve vector REV Richard Henderson
2021-06-26 6:36 ` [PATCH v3 23/29] target/arm: Improve REVSH Richard Henderson
2021-06-26 6:36 ` [PATCH v3 24/29] target/i386: Improve bswap translation Richard Henderson
2021-06-26 6:36 ` [PATCH v3 25/29] target/sh4: Improve swap.b translation Richard Henderson
2021-06-26 6:36 ` [PATCH v3 26/29] target/mips: Fix gen_mxu_s32ldd_s32lddr Richard Henderson
2021-06-26 6:36 ` [PATCH v3 27/29] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP Richard Henderson
2021-06-26 6:36 ` [PATCH v3 28/29] tcg/aarch64: " Richard Henderson
2021-06-26 6:36 ` [PATCH v3 29/29] tcg/riscv: Remove MO_BSWAP handling Richard Henderson
2021-06-26 7:03 ` [PATCH v3 00/29] tcg: bswap improvements no-reply
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