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Tsirkin" To: David Gibson Subject: Re: [PATCH v5 2/7] hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35 Message-ID: <20210702103411-mutt-send-email-mst@kernel.org> References: <20210617190739.3673064-1-jusual@redhat.com> <20210617190739.3673064-3-jusual@redhat.com> MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.377, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , Julia Suvorova , qemu-devel@nongnu.org, Eduardo Habkost Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jul 01, 2021 at 02:36:30PM +1000, David Gibson wrote: > On Thu, Jun 17, 2021 at 09:07:34PM +0200, Julia Suvorova wrote: > > Implement notifications and gpe to support q35 ACPI PCI hot-plug. > > Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports. > > > > Signed-off-by: Julia Suvorova > > Reviewed-by: Igor Mammedov > > Reviewed-by: Marcel Apfelbaum > > I don't know ACPI or x86 particular well, so I could well have missed > something, but.. > > [snip] > > @@ -392,6 +392,9 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, > > > > if (!pdev) { > > if (bsel) { /* add hotplug slots for non present devices */ > > + if (pci_bus_is_express(bus) && slot > 0) { > > + break; > > + } > > dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); > > aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); > > aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); > > @@ -516,7 +519,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, > > QLIST_FOREACH(sec, &bus->child, sibling) { > > int32_t devfn = sec->parent_dev->devfn; > > > > - if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { > > + if (pci_bus_is_root(sec)) { > > continue; > > } > > .. what will this logic do if we encounter a PCIe-switch. AIUI, it > should be possible to hotplug 1 slot under each downstream port, but > we can't hotplug anything directly under the upstream port. AFAICT > both the upstream and downstream ports will show up as 'is_bridge' > though. > > So, IIUC we want to traverse a PCIe upstream switch port, but not > generate hotplug slots until we encounter the downstream ports below > it. Julia could you comment on this please? I already applied the patches so patch on top if necessary please ... > -- > David Gibson | I'll have my music baroque, and my code > david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ > | _way_ _around_! > http://www.ozlabs.org/~dgibson