[PATCH 0/3] hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure

[PATCH 0/3] hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure

[Bin Meng]

As of today, when booting upstream U-Boot for Xilinx Zynq, the UART
does not receive anything. Debugging shows that the UART input clock
frequency is zero which prevents the UART from receiving anything as.
per the logic in uart_receive().

Note the U-Boot can still output data to the UART tx fifo, which should
not happen, as the design seems to prevent the data transmission when
clock is not enabled but somehow it only applies to the Rx side.

For anyone who is interested to give a try, here is the U-Boot defconfig:
$ make xilinx_zynq_virt_defconfig

and QEMU commands to test U-Boot:
$ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial stdio \
    -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0

Note U-Boot used to boot properly in QEMU 4.2.0 which is the QEMU
version used in current U-Boot's CI testing. The UART clock changes
were introduced by the following 3 commits:

38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts")
b636db306e06 ("hw/char/cadence_uart: add clock support")
5b49a34c6800 ("hw/arm/xilinx_zynq: connect uart clocks to slcr")


Bin Meng (3):
  hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit
    phase
  hw/char: cadence_uart: Disable transmit when input clock is disabled
  hw/char: cadence_uart: Move clock/reset check to uart_can_receive()

 hw/char/cadence_uart.c | 16 +++++++++++-----
 hw/misc/zynq_slcr.c    | 31 ++++++++++++++++++-------------
 2 files changed, 29 insertions(+), 18 deletions(-)

-- 
2.25.1

[PATCH 1/3] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase

[Bin Meng]

As of today, when booting upstream U-Boot for Xilinx Zynq, the UART
does not receive anything. Debugging shows that the UART input clock
frequency is zero which prevents the UART from receiving anything as
per the logic in uart_receive().

From zynq_slcr_reset_exit() comment, it intends to compute output
clocks according to ps_clk and registers. zynq_slcr_compute_clocks()
is called to accomplish the task, inside which device_is_in_reset()
is called to actually make the attempt in vain.

Rework reset_hold() and reset_exit() so that in the reset exit phase,
the logic can really compute output clocks in reset_exit().

With this change, upstream U-Boot boots properly again with:

$ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial stdio \
    -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0

Fixes: 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 hw/misc/zynq_slcr.c | 31 ++++++++++++++++++-------------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index 5086e6b7ed..8b70285961 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -269,6 +269,21 @@ static uint64_t zynq_slcr_compute_clock(const uint64_t periods[],
     zynq_slcr_compute_clock((plls), (state)->regs[reg], \
                             reg ## _ ## enable_field ## _SHIFT)
 
+static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk)
+{
+    uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
+    uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
+    uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
+
+    uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
+
+    /* compute uartX reference clocks */
+    clock_set(s->uart0_ref_clk,
+              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
+    clock_set(s->uart1_ref_clk,
+              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
+}
+
 /**
  * Compute and set the ouputs clocks periods.
  * But do not propagate them further. Connected clocks
@@ -283,17 +298,7 @@ static void zynq_slcr_compute_clocks(ZynqSLCRState *s)
         ps_clk = 0;
     }
 
-    uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
-    uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
-    uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
-
-    uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
-
-    /* compute uartX reference clocks */
-    clock_set(s->uart0_ref_clk,
-              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
-    clock_set(s->uart1_ref_clk,
-              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
+    zynq_slcr_compute_clocks_internal(s, ps_clk);
 }
 
 /**
@@ -416,7 +421,7 @@ static void zynq_slcr_reset_hold(Object *obj)
     ZynqSLCRState *s = ZYNQ_SLCR(obj);
 
     /* will disable all output clocks */
-    zynq_slcr_compute_clocks(s);
+    zynq_slcr_compute_clocks_internal(s, 0);
     zynq_slcr_propagate_clocks(s);
 }
 
@@ -425,7 +430,7 @@ static void zynq_slcr_reset_exit(Object *obj)
     ZynqSLCRState *s = ZYNQ_SLCR(obj);
 
     /* will compute output clocks according to ps_clk and registers */
-    zynq_slcr_compute_clocks(s);
+    zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk));
     zynq_slcr_propagate_clocks(s);
 }
 
-- 
2.25.1

[PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Bin Meng]

At present when input clock is disabled, any character transmitted
to tx fifo can still show on the serial line, which is wrong.

Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 hw/char/cadence_uart.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index b4b5e8a3ee..154be34992 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
                                int size)
 {
+    /* ignore characters when unclocked or in reset */
+    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
+        return;
+    }
+
     if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
         return;
     }
-- 
2.25.1

[PATCH 3/3] hw/char: cadence_uart: Move clock/reset check to uart_can_receive()

[Bin Meng]

Currently the clock/reset check is done in uart_receive(), but we
can move the check to uart_can_receive() which is earlier.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

 hw/char/cadence_uart.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 154be34992..7326445385 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -235,6 +235,12 @@ static void uart_parameters_setup(CadenceUARTState *s)
 static int uart_can_receive(void *opaque)
 {
     CadenceUARTState *s = opaque;
+
+    /* ignore characters when unclocked or in reset */
+    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
+        return 0;
+    }
+
     int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 
@@ -358,11 +364,6 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size)
     CadenceUARTState *s = opaque;
     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 
-    /* ignore characters when unclocked or in reset */
-    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
-        return;
-    }
-
     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
         uart_write_rx_fifo(opaque, buf, size);
     }
-- 
2.25.1

Re: [PATCH 1/3] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase

[Alistair Francis]

On Mon, Aug 23, 2021 at 12:09 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> As of today, when booting upstream U-Boot for Xilinx Zynq, the UART
> does not receive anything. Debugging shows that the UART input clock
> frequency is zero which prevents the UART from receiving anything as
> per the logic in uart_receive().
>
> From zynq_slcr_reset_exit() comment, it intends to compute output
> clocks according to ps_clk and registers. zynq_slcr_compute_clocks()
> is called to accomplish the task, inside which device_is_in_reset()
> is called to actually make the attempt in vain.
>
> Rework reset_hold() and reset_exit() so that in the reset exit phase,
> the logic can really compute output clocks in reset_exit().
>
> With this change, upstream U-Boot boots properly again with:
>
> $ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial stdio \
>     -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0
>
> Fixes: 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts")
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/misc/zynq_slcr.c | 31 ++++++++++++++++++-------------
>  1 file changed, 18 insertions(+), 13 deletions(-)
>
> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
> index 5086e6b7ed..8b70285961 100644
> --- a/hw/misc/zynq_slcr.c
> +++ b/hw/misc/zynq_slcr.c
> @@ -269,6 +269,21 @@ static uint64_t zynq_slcr_compute_clock(const uint64_t periods[],
>      zynq_slcr_compute_clock((plls), (state)->regs[reg], \
>                              reg ## _ ## enable_field ## _SHIFT)
>
> +static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk)
> +{
> +    uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
> +    uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
> +    uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
> +
> +    uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
> +
> +    /* compute uartX reference clocks */
> +    clock_set(s->uart0_ref_clk,
> +              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
> +    clock_set(s->uart1_ref_clk,
> +              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
> +}
> +
>  /**
>   * Compute and set the ouputs clocks periods.
>   * But do not propagate them further. Connected clocks
> @@ -283,17 +298,7 @@ static void zynq_slcr_compute_clocks(ZynqSLCRState *s)
>          ps_clk = 0;
>      }
>
> -    uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
> -    uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
> -    uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
> -
> -    uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
> -
> -    /* compute uartX reference clocks */
> -    clock_set(s->uart0_ref_clk,
> -              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
> -    clock_set(s->uart1_ref_clk,
> -              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
> +    zynq_slcr_compute_clocks_internal(s, ps_clk);
>  }
>
>  /**
> @@ -416,7 +421,7 @@ static void zynq_slcr_reset_hold(Object *obj)
>      ZynqSLCRState *s = ZYNQ_SLCR(obj);
>
>      /* will disable all output clocks */
> -    zynq_slcr_compute_clocks(s);
> +    zynq_slcr_compute_clocks_internal(s, 0);
>      zynq_slcr_propagate_clocks(s);
>  }
>
> @@ -425,7 +430,7 @@ static void zynq_slcr_reset_exit(Object *obj)
>      ZynqSLCRState *s = ZYNQ_SLCR(obj);
>
>      /* will compute output clocks according to ps_clk and registers */
> -    zynq_slcr_compute_clocks(s);
> +    zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk));
>      zynq_slcr_propagate_clocks(s);
>  }
>
> --
> 2.25.1
>
>

Re: [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Alistair Francis]

On Mon, Aug 23, 2021 at 12:11 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> At present when input clock is disabled, any character transmitted
> to tx fifo can still show on the serial line, which is wrong.
>
> Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  hw/char/cadence_uart.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> index b4b5e8a3ee..154be34992 100644
> --- a/hw/char/cadence_uart.c
> +++ b/hw/char/cadence_uart.c
> @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
>  static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
>                                 int size)
>  {
> +    /* ignore characters when unclocked or in reset */
> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> +        return;
> +    }

Should we log a guest error here?

Alistair

> +
>      if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
>          return;
>      }
> --
> 2.25.1
>
>

Re: [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Bin Meng]

On Mon, Aug 23, 2021 at 12:43 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Mon, Aug 23, 2021 at 12:11 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > At present when input clock is disabled, any character transmitted
> > to tx fifo can still show on the serial line, which is wrong.
> >
> > Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> >  hw/char/cadence_uart.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> > index b4b5e8a3ee..154be34992 100644
> > --- a/hw/char/cadence_uart.c
> > +++ b/hw/char/cadence_uart.c
> > @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
> >  static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
> >                                 int size)
> >  {
> > +    /* ignore characters when unclocked or in reset */
> > +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> > +        return;
> > +    }
>
> Should we log a guest error here?
>

Not sure. Based on my past experience of many hardware, if the input
clock is disabled, accessing the whole register block might cause a
bus fault. But I believe such bus fault is not modeled in QEMU.

This change just mirrors the same check on the Rx side.

Regards,
Bin

Re: [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Alistair Francis]

On Mon, Aug 23, 2021 at 2:53 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Mon, Aug 23, 2021 at 12:43 PM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Mon, Aug 23, 2021 at 12:11 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > At present when input clock is disabled, any character transmitted
> > > to tx fifo can still show on the serial line, which is wrong.
> > >
> > > Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
> > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > > ---
> > >
> > >  hw/char/cadence_uart.c | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> > > index b4b5e8a3ee..154be34992 100644
> > > --- a/hw/char/cadence_uart.c
> > > +++ b/hw/char/cadence_uart.c
> > > @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
> > >  static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
> > >                                 int size)
> > >  {
> > > +    /* ignore characters when unclocked or in reset */
> > > +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> > > +        return;
> > > +    }
> >
> > Should we log a guest error here?
> >
>
> Not sure. Based on my past experience of many hardware, if the input
> clock is disabled, accessing the whole register block might cause a
> bus fault. But I believe such bus fault is not modeled in QEMU.
>
> This change just mirrors the same check on the Rx side.

Ok:

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> Regards,
> Bin

Re: [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Philippe Mathieu-Daudé]

On 8/23/21 4:08 AM, Bin Meng wrote:
> At present when input clock is disabled, any character transmitted
> to tx fifo can still show on the serial line, which is wrong.
> 
> Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> 
>  hw/char/cadence_uart.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> index b4b5e8a3ee..154be34992 100644
> --- a/hw/char/cadence_uart.c
> +++ b/hw/char/cadence_uart.c
> @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
>  static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
>                                 int size)
>  {
> +    /* ignore characters when unclocked or in reset */
> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> +        return;
> +    }

Incorrect handler?

-- >8 --
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index b4b5e8a3ee0..4f096222f52 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -235,8 +235,16 @@ static void uart_parameters_setup(CadenceUARTState *s)
 static int uart_can_receive(void *opaque)
 {
     CadenceUARTState *s = opaque;
-    int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
-    uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
+    int ret;
+    uint32_t ch_mode;
+
+    /* ignore characters when unclocked or in reset */
+    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
+        return 0;
+    }
+
+    ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
+    ch_mode = s->r[R_MR] & UART_MR_CHMODE;

     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
         ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
---

Re: [PATCH 3/3] hw/char: cadence_uart: Move clock/reset check to uart_can_receive()

[Philippe Mathieu-Daudé]

On 8/23/21 4:08 AM, Bin Meng wrote:
> Currently the clock/reset check is done in uart_receive(), but we
> can move the check to uart_can_receive() which is earlier.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 
> ---
> 
>  hw/char/cadence_uart.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> index 154be34992..7326445385 100644
> --- a/hw/char/cadence_uart.c
> +++ b/hw/char/cadence_uart.c
> @@ -235,6 +235,12 @@ static void uart_parameters_setup(CadenceUARTState *s)
>  static int uart_can_receive(void *opaque)
>  {
>      CadenceUARTState *s = opaque;
> +
> +    /* ignore characters when unclocked or in reset */
> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> +        return 0;
> +    }
> +
>      int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
>      uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
>  
> @@ -358,11 +364,6 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size)
>      CadenceUARTState *s = opaque;
>      uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
>  
> -    /* ignore characters when unclocked or in reset */
> -    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> -        return;
> -    }
> -
>      if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
>          uart_write_rx_fifo(opaque, buf, size);
>      }
> 

Almost the same I just sent in patch #2 (minor you declare variables
mid-scope). Drop #2 and use that (or untested snippet) directly instead.

Re: [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Bin Meng]

On Mon, Aug 23, 2021 at 4:14 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 8/23/21 4:08 AM, Bin Meng wrote:
> > At present when input clock is disabled, any character transmitted
> > to tx fifo can still show on the serial line, which is wrong.
> >
> > Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> >  hw/char/cadence_uart.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> > index b4b5e8a3ee..154be34992 100644
> > --- a/hw/char/cadence_uart.c
> > +++ b/hw/char/cadence_uart.c
> > @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
> >  static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
> >                                 int size)
> >  {
> > +    /* ignore characters when unclocked or in reset */
> > +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> > +        return;
> > +    }
>
> Incorrect handler?
>

Sorry I don't get it. This patch is for the Tx path, while patch #3 is
for the Rx path.

> -- >8 --
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> index b4b5e8a3ee0..4f096222f52 100644
> --- a/hw/char/cadence_uart.c
> +++ b/hw/char/cadence_uart.c
> @@ -235,8 +235,16 @@ static void uart_parameters_setup(CadenceUARTState *s)
>  static int uart_can_receive(void *opaque)
>  {
>      CadenceUARTState *s = opaque;
> -    int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
> -    uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
> +    int ret;
> +    uint32_t ch_mode;
> +
> +    /* ignore characters when unclocked or in reset */
> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> +        return 0;
> +    }
> +
> +    ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
> +    ch_mode = s->r[R_MR] & UART_MR_CHMODE;
>
>      if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
>          ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);

Regards,
Bin

Re: [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Philippe Mathieu-Daudé]

On 8/23/21 11:57 AM, Bin Meng wrote:
> On Mon, Aug 23, 2021 at 4:14 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> On 8/23/21 4:08 AM, Bin Meng wrote:
>>> At present when input clock is disabled, any character transmitted
>>> to tx fifo can still show on the serial line, which is wrong.
>>>
>>> Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>
>>>  hw/char/cadence_uart.c | 5 +++++
>>>  1 file changed, 5 insertions(+)
>>>
>>> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
>>> index b4b5e8a3ee..154be34992 100644
>>> --- a/hw/char/cadence_uart.c
>>> +++ b/hw/char/cadence_uart.c
>>> @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
>>>  static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
>>>                                 int size)
>>>  {
>>> +    /* ignore characters when unclocked or in reset */
>>> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
>>> +        return;
>>> +    }
>>
>> Incorrect handler?
>>
> 
> Sorry I don't get it. This patch is for the Tx path, while patch #3 is
> for the Rx path.

Sorry, I was not totally awake o_O

-- >8 --
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index b4b5e8a3ee0..78990ea79dc 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -403,15 +403,20 @@ static void uart_read_rx_fifo(CadenceUARTState *s,
uint32_t *c)
     uart_update_status(s);
 }

-static void uart_write(void *opaque, hwaddr offset,
-                          uint64_t value, unsigned size)
+static MemTxResult uart_write(void *opaque, hwaddr offset, uint64_t value,
+                              unsigned size, MemTxAttrs attrs)
 {
     CadenceUARTState *s = opaque;

+    /* ignore characters when unclocked or in reset */
+    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
+        return MEMTX_DECODE_ERROR;
+    }
+
     DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
     offset >>= 2;
     if (offset >= CADENCE_UART_R_MAX) {
-        return;
+        return MEMTX_OK;
     }
     switch (offset) {
     case R_IER: /* ier (wts imr) */
@@ -458,14 +463,21 @@ static void uart_write(void *opaque, hwaddr offset,
         break;
     }
     uart_update_status(s);
+
+    return MEMTX_OK;
 }

-static uint64_t uart_read(void *opaque, hwaddr offset,
-        unsigned size)
+static MemTxResult uart_read(void *opaque, hwaddr offset, uint64_t *data,
+                             unsigned size, MemTxAttrs attrs)
 {
     CadenceUARTState *s = opaque;
     uint32_t c = 0;

+    /* ignore characters when unclocked or in reset */
+    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
+        return MEMTX_DECODE_ERROR;
+    }
+
     offset >>= 2;
     if (offset >= CADENCE_UART_R_MAX) {
         c = 0;
@@ -476,12 +488,14 @@ static uint64_t uart_read(void *opaque, hwaddr offset,
     }

     DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2),
(unsigned)c);
-    return c;
+    *data = c;
+
+    return MEMTX_OK;
 }

 static const MemoryRegionOps uart_ops = {
-    .read = uart_read,
-    .write = uart_write,
+    .read_with_attrs = uart_read,
+    .write_with_attrs = uart_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
---

Re: [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Bin Meng]

On Mon, Aug 23, 2021 at 6:43 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 8/23/21 11:57 AM, Bin Meng wrote:
> > On Mon, Aug 23, 2021 at 4:14 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >>
> >> On 8/23/21 4:08 AM, Bin Meng wrote:
> >>> At present when input clock is disabled, any character transmitted
> >>> to tx fifo can still show on the serial line, which is wrong.
> >>>
> >>> Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
> >>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >>> ---
> >>>
> >>>  hw/char/cadence_uart.c | 5 +++++
> >>>  1 file changed, 5 insertions(+)
> >>>
> >>> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> >>> index b4b5e8a3ee..154be34992 100644
> >>> --- a/hw/char/cadence_uart.c
> >>> +++ b/hw/char/cadence_uart.c
> >>> @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
> >>>  static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
> >>>                                 int size)
> >>>  {
> >>> +    /* ignore characters when unclocked or in reset */
> >>> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> >>> +        return;
> >>> +    }
> >>
> >> Incorrect handler?
> >>
> >
> > Sorry I don't get it. This patch is for the Tx path, while patch #3 is
> > for the Rx path.
>
> Sorry, I was not totally awake o_O
>
> -- >8 --
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> index b4b5e8a3ee0..78990ea79dc 100644
> --- a/hw/char/cadence_uart.c
> +++ b/hw/char/cadence_uart.c
> @@ -403,15 +403,20 @@ static void uart_read_rx_fifo(CadenceUARTState *s,
> uint32_t *c)
>      uart_update_status(s);
>  }
>
> -static void uart_write(void *opaque, hwaddr offset,
> -                          uint64_t value, unsigned size)
> +static MemTxResult uart_write(void *opaque, hwaddr offset, uint64_t value,
> +                              unsigned size, MemTxAttrs attrs)
>  {
>      CadenceUARTState *s = opaque;
>
> +    /* ignore characters when unclocked or in reset */
> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> +        return MEMTX_DECODE_ERROR;
> +    }
> +
>      DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
>      offset >>= 2;
>      if (offset >= CADENCE_UART_R_MAX) {
> -        return;
> +        return MEMTX_OK;
>      }
>      switch (offset) {
>      case R_IER: /* ier (wts imr) */
> @@ -458,14 +463,21 @@ static void uart_write(void *opaque, hwaddr offset,
>          break;
>      }
>      uart_update_status(s);
> +
> +    return MEMTX_OK;
>  }
>
> -static uint64_t uart_read(void *opaque, hwaddr offset,
> -        unsigned size)
> +static MemTxResult uart_read(void *opaque, hwaddr offset, uint64_t *data,
> +                             unsigned size, MemTxAttrs attrs)
>  {
>      CadenceUARTState *s = opaque;
>      uint32_t c = 0;
>
> +    /* ignore characters when unclocked or in reset */
> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> +        return MEMTX_DECODE_ERROR;
> +    }
> +
>      offset >>= 2;
>      if (offset >= CADENCE_UART_R_MAX) {
>          c = 0;
> @@ -476,12 +488,14 @@ static uint64_t uart_read(void *opaque, hwaddr offset,
>      }
>
>      DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2),
> (unsigned)c);
> -    return c;
> +    *data = c;
> +
> +    return MEMTX_OK;
>  }
>
>  static const MemoryRegionOps uart_ops = {
> -    .read = uart_read,
> -    .write = uart_write,
> +    .read_with_attrs = uart_read,
> +    .write_with_attrs = uart_write,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>  };

Thanks, but I think the above change should be a totally separate patch.

Regards,
Bin

Re: [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Philippe Mathieu-Daudé]

On 8/23/21 3:14 PM, Bin Meng wrote:
> On Mon, Aug 23, 2021 at 6:43 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> On 8/23/21 11:57 AM, Bin Meng wrote:
>>> On Mon, Aug 23, 2021 at 4:14 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>>>
>>>> On 8/23/21 4:08 AM, Bin Meng wrote:
>>>>> At present when input clock is disabled, any character transmitted
>>>>> to tx fifo can still show on the serial line, which is wrong.
>>>>>
>>>>> Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>>> ---
>>>>>
>>>>>  hw/char/cadence_uart.c | 5 +++++
>>>>>  1 file changed, 5 insertions(+)
>>>>>
>>>>> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
>>>>> index b4b5e8a3ee..154be34992 100644
>>>>> --- a/hw/char/cadence_uart.c
>>>>> +++ b/hw/char/cadence_uart.c
>>>>> @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
>>>>>  static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
>>>>>                                 int size)
>>>>>  {
>>>>> +    /* ignore characters when unclocked or in reset */
>>>>> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
>>>>> +        return;
>>>>> +    }
>>>>
>>>> Incorrect handler?
>>>>
>>>
>>> Sorry I don't get it. This patch is for the Tx path, while patch #3 is
>>> for the Rx path.
>>
>> Sorry, I was not totally awake o_O
>>
>> -- >8 --
>> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
>> index b4b5e8a3ee0..78990ea79dc 100644
>> --- a/hw/char/cadence_uart.c
>> +++ b/hw/char/cadence_uart.c
>> @@ -403,15 +403,20 @@ static void uart_read_rx_fifo(CadenceUARTState *s,
>> uint32_t *c)
>>      uart_update_status(s);
>>  }
>>
>> -static void uart_write(void *opaque, hwaddr offset,
>> -                          uint64_t value, unsigned size)
>> +static MemTxResult uart_write(void *opaque, hwaddr offset, uint64_t value,
>> +                              unsigned size, MemTxAttrs attrs)
>>  {
>>      CadenceUARTState *s = opaque;
>>
>> +    /* ignore characters when unclocked or in reset */
>> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
>> +        return MEMTX_DECODE_ERROR;
>> +    }
>> +
>>      DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
>>      offset >>= 2;
>>      if (offset >= CADENCE_UART_R_MAX) {
>> -        return;
>> +        return MEMTX_OK;
>>      }
>>      switch (offset) {
>>      case R_IER: /* ier (wts imr) */
>> @@ -458,14 +463,21 @@ static void uart_write(void *opaque, hwaddr offset,
>>          break;
>>      }
>>      uart_update_status(s);
>> +
>> +    return MEMTX_OK;
>>  }
>>
>> -static uint64_t uart_read(void *opaque, hwaddr offset,
>> -        unsigned size)
>> +static MemTxResult uart_read(void *opaque, hwaddr offset, uint64_t *data,
>> +                             unsigned size, MemTxAttrs attrs)
>>  {
>>      CadenceUARTState *s = opaque;
>>      uint32_t c = 0;
>>
>> +    /* ignore characters when unclocked or in reset */
>> +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
>> +        return MEMTX_DECODE_ERROR;
>> +    }
>> +
>>      offset >>= 2;
>>      if (offset >= CADENCE_UART_R_MAX) {
>>          c = 0;
>> @@ -476,12 +488,14 @@ static uint64_t uart_read(void *opaque, hwaddr offset,
>>      }
>>
>>      DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2),
>> (unsigned)c);
>> -    return c;
>> +    *data = c;
>> +
>> +    return MEMTX_OK;
>>  }
>>
>>  static const MemoryRegionOps uart_ops = {
>> -    .read = uart_read,
>> -    .write = uart_write,
>> +    .read_with_attrs = uart_read,
>> +    .write_with_attrs = uart_write,
>>      .endianness = DEVICE_NATIVE_ENDIAN,
>>  };
> 
> Thanks, but I think the above change should be a totally separate patch.

Yes, this was not a patch snippet, but the result.

First patch would be convert to memop_with_attrs() and
second return MEMTX_DECODE_ERROR when unclocked.

Re: [PATCH 1/3] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase

[Edgar E. Iglesias]

On Mon, Aug 23, 2021 at 02:42:03PM +1000, Alistair Francis wrote:
> On Mon, Aug 23, 2021 at 12:09 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > As of today, when booting upstream U-Boot for Xilinx Zynq, the UART
> > does not receive anything. Debugging shows that the UART input clock
> > frequency is zero which prevents the UART from receiving anything as
> > per the logic in uart_receive().
> >
> > From zynq_slcr_reset_exit() comment, it intends to compute output
> > clocks according to ps_clk and registers. zynq_slcr_compute_clocks()
> > is called to accomplish the task, inside which device_is_in_reset()
> > is called to actually make the attempt in vain.
> >
> > Rework reset_hold() and reset_exit() so that in the reset exit phase,
> > the logic can really compute output clocks in reset_exit().
> >
> > With this change, upstream U-Boot boots properly again with:
> >
> > $ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial stdio \
> >     -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0
> >
> > Fixes: 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts")
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 
> Acked-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>



> 
> Alistair
> 
> > ---
> >
> >  hw/misc/zynq_slcr.c | 31 ++++++++++++++++++-------------
> >  1 file changed, 18 insertions(+), 13 deletions(-)
> >
> > diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
> > index 5086e6b7ed..8b70285961 100644
> > --- a/hw/misc/zynq_slcr.c
> > +++ b/hw/misc/zynq_slcr.c
> > @@ -269,6 +269,21 @@ static uint64_t zynq_slcr_compute_clock(const uint64_t periods[],
> >      zynq_slcr_compute_clock((plls), (state)->regs[reg], \
> >                              reg ## _ ## enable_field ## _SHIFT)
> >
> > +static void zynq_slcr_compute_clocks_internal(ZynqSLCRState *s, uint64_t ps_clk)
> > +{
> > +    uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
> > +    uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
> > +    uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
> > +
> > +    uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
> > +
> > +    /* compute uartX reference clocks */
> > +    clock_set(s->uart0_ref_clk,
> > +              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
> > +    clock_set(s->uart1_ref_clk,
> > +              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
> > +}
> > +
> >  /**
> >   * Compute and set the ouputs clocks periods.
> >   * But do not propagate them further. Connected clocks
> > @@ -283,17 +298,7 @@ static void zynq_slcr_compute_clocks(ZynqSLCRState *s)
> >          ps_clk = 0;
> >      }
> >
> > -    uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
> > -    uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
> > -    uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
> > -
> > -    uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
> > -
> > -    /* compute uartX reference clocks */
> > -    clock_set(s->uart0_ref_clk,
> > -              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
> > -    clock_set(s->uart1_ref_clk,
> > -              ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
> > +    zynq_slcr_compute_clocks_internal(s, ps_clk);
> >  }
> >
> >  /**
> > @@ -416,7 +421,7 @@ static void zynq_slcr_reset_hold(Object *obj)
> >      ZynqSLCRState *s = ZYNQ_SLCR(obj);
> >
> >      /* will disable all output clocks */
> > -    zynq_slcr_compute_clocks(s);
> > +    zynq_slcr_compute_clocks_internal(s, 0);
> >      zynq_slcr_propagate_clocks(s);
> >  }
> >
> > @@ -425,7 +430,7 @@ static void zynq_slcr_reset_exit(Object *obj)
> >      ZynqSLCRState *s = ZYNQ_SLCR(obj);
> >
> >      /* will compute output clocks according to ps_clk and registers */
> > -    zynq_slcr_compute_clocks(s);
> > +    zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk));
> >      zynq_slcr_propagate_clocks(s);
> >  }
> >
> > --
> > 2.25.1
> >
> >

Re: [PATCH 2/3] hw/char: cadence_uart: Disable transmit when input clock is disabled

[Edgar E. Iglesias]

On Mon, Aug 23, 2021 at 02:43:26PM +1000, Alistair Francis wrote:
> On Mon, Aug 23, 2021 at 12:11 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > At present when input clock is disabled, any character transmitted
> > to tx fifo can still show on the serial line, which is wrong.
> >
> > Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> >  hw/char/cadence_uart.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> > index b4b5e8a3ee..154be34992 100644
> > --- a/hw/char/cadence_uart.c
> > +++ b/hw/char/cadence_uart.c
> > @@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
> >  static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
> >                                 int size)
> >  {
> > +    /* ignore characters when unclocked or in reset */
> > +    if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
> > +        return;
> > +    }
> 
> Should we log a guest error here?
> 


I think it's a good idea to log a guest error on the TX path.

It's not uncommon for bare-metal applications to rely on FSBL/Bootloaders
setting up clocks/resets. On QEMU, it's convenient to run applications
directly without boot-loaders, particularly FSBL since it requires Xilinx tools
to generate it. It's going to be hard for users to figure out what's going on
with no console output and no guest error.

I also wonder how Linux handles this when CCF is not active?
Do we need to use TYPE_ARM_LINUX_BOOT_IF?

Best regards,
Edgar