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([141.164.41.4]) by smtp.gmail.com with ESMTPSA id ev12sm4700796pjb.57.2021.08.23.07.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 07:20:42 -0700 (PDT) From: Changbin Du To: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/3] riscv: gdbstub: add support for switchable endianness Date: Mon, 23 Aug 2021 22:20:04 +0800 Message-Id: <20210823142004.17935-4-changbin.du@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210823142004.17935-1-changbin.du@gmail.com> References: <20210823142004.17935-1-changbin.du@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=changbin.du@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-riscv@nongnu.org, Bin Meng , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Alistair Francis , Paolo Bonzini , Palmer Dabbelt , Changbin Du Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Apply new gdbstub interfaces we added previously to support both little and big endian guest debugging for RISC-V. And enable the TARGET_SWICHABLE_ENDIANNESS option. Signed-off-by: Changbin Du --- configs/targets/riscv32-softmmu.mak | 1 + configs/targets/riscv64-softmmu.mak | 1 + target/riscv/gdbstub.c | 12 ++++++------ 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak index d8b71cddcd..7f02e67c72 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=riscv TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml TARGET_NEED_FDT=y +TARGET_SWICHABLE_ENDIANNESS=y diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak index 7c0e7eeb42..c3e812495c 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=riscv TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml TARGET_NEED_FDT=y +TARGET_SWICHABLE_ENDIANNESS=y diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a7a9c0b1fe..d639cea859 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -42,10 +42,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) /* discard writes to x0 */ return sizeof(target_ulong); } else if (n < 32) { - env->gpr[n] = ldtul_p(mem_buf); + env->gpr[n] = gdb_read_regl(mem_buf); return sizeof(target_ulong); } else if (n == 32) { - env->pc = ldtul_p(mem_buf); + env->pc = gdb_read_regl(mem_buf); return sizeof(target_ulong); } return 0; @@ -81,11 +81,11 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) { if (n < 32) { - env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */ + env->fpr[n] = gdb_read_reg64(mem_buf); /* always 64-bit */ return sizeof(uint64_t); /* there is hole between ft11 and fflags in fpu.xml */ } else if (n < 36 && n > 32) { - target_ulong val = ldtul_p(mem_buf); + target_ulong val = gdb_read_regl(mem_buf); int result; /* * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP @@ -118,7 +118,7 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) { if (n < CSR_TABLE_SIZE) { - target_ulong val = ldtul_p(mem_buf); + target_ulong val = gdb_read_regl(mem_buf); int result; result = riscv_csrrw_debug(env, n, NULL, val, -1); @@ -145,7 +145,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) { if (n == 0) { #ifndef CONFIG_USER_ONLY - cs->priv = ldtul_p(mem_buf) & 0x3; + cs->priv = gdb_read_regl(mem_buf) & 0x3; if (cs->priv == PRV_H) { cs->priv = PRV_S; } -- 2.32.0