From: Luis Pires <luis.pires@eldorado.org.br>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: Luis Pires <luis.pires@eldorado.org.br>,
richard.henderson@linaro.org, groug@kaod.org,
david@gibson.dropbear.id.au
Subject: [PATCH 12/19] target/ppc: Implement DCTFIXQQ
Date: Tue, 24 Aug 2021 11:27:23 -0300 [thread overview]
Message-ID: <20210824142730.102421-13-luis.pires@eldorado.org.br> (raw)
In-Reply-To: <20210824142730.102421-1-luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
dctfixqq: DFP Convert To Fixed Quadword Quad
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
---
target/ppc/dfp_helper.c | 53 +++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 5 +++
target/ppc/translate/dfp-impl.c.inc | 17 +++++++++
4 files changed, 76 insertions(+)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index 01a7ead783..ef1c370c3c 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -51,6 +51,12 @@ static void set_dfp128(ppc_fprp_t *dfp, ppc_vsr_t *src)
dfp[1].VsrD(0) = src->VsrD(1);
}
+static void set_dfp128_to_avr(ppc_avr_t *dst, ppc_vsr_t *src)
+{
+ dst->VsrD(0) = src->VsrD(0);
+ dst->VsrD(1) = src->VsrD(1);
+}
+
struct PPC_DFP {
CPUPPCState *env;
ppc_vsr_t vt, va, vb;
@@ -1019,6 +1025,53 @@ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \
DFP_HELPER_CTFIX(dctfix, 64)
DFP_HELPER_CTFIX(dctfixq, 128)
+void helper_DCTFIXQQ(CPUPPCState *env, ppc_avr_t *t, ppc_fprp_t *b)
+{
+ struct PPC_DFP dfp;
+ dfp_prepare_decimal128(&dfp, 0, b, env);
+
+ if (unlikely(decNumberIsSpecial(&dfp.b))) {
+ uint64_t invalid_flags = FP_VX | FP_VXCVI;
+ if (decNumberIsInfinite(&dfp.b)) {
+ if (decNumberIsNegative(&dfp.b)) {
+ dfp.vt.VsrD(0) = INT64_MIN;
+ dfp.vt.VsrD(1) = 0;
+ } else {
+ dfp.vt.VsrD(0) = INT64_MAX;
+ dfp.vt.VsrD(1) = UINT64_MAX;
+ }
+ } else { /* NaN */
+ dfp.vt.VsrD(0) = INT64_MIN;
+ dfp.vt.VsrD(1) = 0;
+ if (decNumberIsSNaN(&dfp.b)) {
+ invalid_flags |= FP_VXSNAN;
+ }
+ }
+ dfp_set_FPSCR_flag(&dfp, invalid_flags, FP_VE);
+ } else if (unlikely(decNumberIsZero(&dfp.b))) {
+ dfp.vt.VsrD(0) = 0;
+ dfp.vt.VsrD(1) = 0;
+ } else {
+ decNumberToIntegralExact(&dfp.b, &dfp.b, &dfp.context);
+ decNumberIntegralToInt128(&dfp.b, &dfp.context,
+ &dfp.vt.VsrD(1), &dfp.vt.VsrD(0));
+ if (decContextTestStatus(&dfp.context, DEC_Invalid_operation)) {
+ if (decNumberIsNegative(&dfp.b)) {
+ dfp.vt.VsrD(0) = INT64_MIN;
+ dfp.vt.VsrD(1) = 0;
+ } else {
+ dfp.vt.VsrD(0) = INT64_MAX;
+ dfp.vt.VsrD(1) = UINT64_MAX;
+ }
+ dfp_set_FPSCR_flag(&dfp, FP_VX | FP_VXCVI, FP_VE);
+ } else {
+ dfp_check_for_XX(&dfp);
+ }
+ }
+
+ set_dfp128_to_avr(t, &dfp.vt);
+}
+
static inline void dfp_set_bcd_digit_64(ppc_vsr_t *t, uint8_t digit,
unsigned n)
{
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index fff7bd46ad..20041ce977 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -737,6 +737,7 @@ DEF_HELPER_3(dcffixq, void, env, fprp, fprp)
DEF_HELPER_3(DCFFIXQQ, void, env, fprp, avr)
DEF_HELPER_3(dctfix, void, env, fprp, fprp)
DEF_HELPER_3(dctfixq, void, env, fprp, fprp)
+DEF_HELPER_3(DCTFIXQQ, void, env, avr, fprp)
DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32)
DEF_HELPER_4(ddedpdq, void, env, fprp, fprp, i32)
DEF_HELPER_4(denbcd, void, env, fprp, fprp, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 92ea2d0739..6d97f9ae3b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -47,6 +47,10 @@
%x_frtp 22:4 !function=times_2
@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
+&X_vrt_frbp vrt frbp
+%x_frbp 12:4 !function=times_2
+@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -128,6 +132,7 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
### Decimal Floating-Point Conversion Instructions
DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
+DCTFIXQQ 111111 ..... 00001 ..... 1111100010 - @X_vrt_frbp
## Vector Bit Manipulation Instruction
diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc
index d5b66567a6..e149777481 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -247,3 +247,20 @@ static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
return true;
}
+
+static bool trans_DCTFIXQQ(DisasContext *ctx, arg_DCTFIXQQ *a)
+{
+ TCGv_ptr rt, rb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, DFP);
+ REQUIRE_FPU(ctx);
+ REQUIRE_VECTOR(ctx);
+
+ rt = gen_avr_ptr(a->vrt);
+ rb = gen_fprp_ptr(a->frbp);
+ gen_helper_DCTFIXQQ(cpu_env, rt, rb);
+ tcg_temp_free_ptr(rt);
+ tcg_temp_free_ptr(rb);
+
+ return true;
+}
--
2.25.1
next prev parent reply other threads:[~2021-08-24 14:37 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-24 14:27 [PATCH 00/19] target/ppc: DFP instructions using decodetree Luis Pires
2021-08-24 14:27 ` [PATCH 01/19] host-utils: Fix overflow detection in divu128() Luis Pires
2021-08-24 14:27 ` [PATCH 02/19] host-utils: move abs64() to host-utils Luis Pires
2021-08-25 3:43 ` David Gibson
2021-08-25 12:48 ` Luis Fernando Fujita Pires
2021-08-25 20:26 ` Eduardo Habkost
2021-08-25 20:37 ` Luis Fernando Fujita Pires
2021-08-25 21:18 ` Eduardo Habkost
2021-08-25 21:27 ` Philippe Mathieu-Daudé
2021-08-27 14:28 ` Luis Fernando Fujita Pires
2021-08-24 14:27 ` [PATCH 03/19] host-utils: move checks out of divu128/divs128 Luis Pires
2021-08-24 14:27 ` [PATCH 04/19] host-utils: add 128-bit quotient support to divu128/divs128 Luis Pires
2021-08-24 14:27 ` [PATCH 05/19] host-utils: add unit tests for divu128/divs128 Luis Pires
2021-08-24 14:27 ` [PATCH 06/19] libdecnumber: introduce decNumberFrom[U]Int128 Luis Pires
2021-08-24 14:27 ` [PATCH 07/19] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c Luis Pires
2021-08-25 3:46 ` David Gibson
2021-08-24 14:27 ` [PATCH 08/19] target/ppc: Introduce REQUIRE_FPU Luis Pires
2021-08-25 3:46 ` David Gibson
2021-08-24 14:27 ` [PATCH 09/19] target/ppc: Implement DCFFIXQQ Luis Pires
2021-08-24 14:27 ` [PATCH 10/19] host-utils: Introduce mulu128 Luis Pires
2021-08-24 14:27 ` [PATCH 11/19] libdecnumber: Introduce decNumberIntegralToInt128 Luis Pires
2021-08-24 14:27 ` Luis Pires [this message]
2021-08-24 14:27 ` [PATCH 13/19] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree Luis Pires
2021-08-25 13:15 ` Philippe Mathieu-Daudé
2021-08-24 14:27 ` [PATCH 14/19] target/ppc: Move d{add, sub, mul, div, iex}[q] " Luis Pires
2021-08-25 13:16 ` Philippe Mathieu-Daudé
2021-08-24 14:27 ` [PATCH 15/19] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] " Luis Pires
2021-08-24 14:27 ` [PATCH 16/19] target/ppc: Move dquai[q], drint{x,n}[q] " Luis Pires
2021-08-25 13:18 ` Philippe Mathieu-Daudé
2021-08-24 14:27 ` [PATCH 17/19] target/ppc: Move dqua[q], drrnd[q] " Luis Pires
2021-08-25 13:18 ` Philippe Mathieu-Daudé
2021-08-24 14:27 ` [PATCH 18/19] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] " Luis Pires
2021-08-25 13:19 ` Philippe Mathieu-Daudé
2021-08-24 14:27 ` [PATCH 19/19] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] " Luis Pires
2021-08-25 13:20 ` Philippe Mathieu-Daudé
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