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Tue, 24 Aug 2021 09:31:27 -0700 (PDT) Received: from rekt.ihost.com ([179.247.162.205]) by smtp.gmail.com with ESMTPSA id 75sm10951474qko.100.2021.08.24.09.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Aug 2021 09:31:27 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 16/16] target/ppc/power8_pmu.c: handle overflow bits when PMU is running Date: Tue, 24 Aug 2021 13:30:32 -0300 Message-Id: <20210824163032.394099-17-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210824163032.394099-1-danielhb413@gmail.com> References: <20210824163032.394099-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::834; envelope-from=danielhb413@gmail.com; helo=mail-qt1-x834.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Up until this moment we were assuming that the counter negative enabled bits, PMC1CE and PMCjCE, would never be changed when the PMU is already started. Turns out that there is no such restriction in the PowerISA v3.1, and software can enable/disable overflow conditions of the counters at any time. To support this scenario, track the overflow bits state when a write in MMCR0 is made in which the run state of the PMU (MMCR0_FC bit) didn't change and, if some overflow bit were changed in the middle of a cycle count session, restart it. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8_pmu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index d235cc2b53..e02986f18a 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -340,6 +340,30 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value) } else { start_cycle_count_session(env); } + } else { + /* + * No change in MMCR0_FC state, but if the PMU is running and + * a change in the counter negative overflow bits is made, + * we need to restart a new cycle count session to restart + * the appropriate overflow timers. + */ + if (curr_FC) { + return; + } + + bool pmc1ce_curr = curr_value & MMCR0_PMC1CE; + bool pmc1ce_new = value & MMCR0_PMC1CE; + bool pmcjce_curr = curr_value & MMCR0_PMCjCE; + bool pmcjce_new = value & MMCR0_PMCjCE; + + if (pmc1ce_curr == pmc1ce_new && pmcjce_curr == pmcjce_new) { + return; + } + + /* Update the counter with the events counted so far */ + update_cycles_PMCs(env); + + start_cycle_count_session(env); } } -- 2.31.1