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Tue, 24 Aug 2021 09:31:03 -0700 (PDT) Received: from rekt.ihost.com ([179.247.162.205]) by smtp.gmail.com with ESMTPSA id 75sm10951474qko.100.2021.08.24.09.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Aug 2021 09:31:03 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v2 07/16] target/ppc/power8_pmu.c: add PM_RUN_INST_CMPL (0xFA) event Date: Tue, 24 Aug 2021 13:30:23 -0300 Message-Id: <20210824163032.394099-8-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210824163032.394099-1-danielhb413@gmail.com> References: <20210824163032.394099-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gustavo.romero@linaro.org, Daniel Henrique Barboza , richard.henderson@linaro.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PM_RUN_INST_CMPL, instructions completed with the run latch set, is the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA. Implement it by checking for the CTRL RUN bit before incrementing the counter. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 3 +++ target/ppc/power8_pmu.c | 25 ++++++++++++++++++++----- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e5df644a3c..60e5e1159a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -358,6 +358,9 @@ typedef struct ppc_v3_pate_t { #define MMCR1_PMC3SEL PPC_BITMASK(48, 55) #define MMCR1_PMC4SEL PPC_BITMASK(56, 63) +/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ +#define CTRL_RUN PPC_BIT(63) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index 311eaa358f..9154fca5fd 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -131,10 +131,10 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value) } } -static bool pmc_counting_insns(CPUPPCState *env, int sprn) +static bool pmc_counting_insns(CPUPPCState *env, int sprn, + uint8_t event) { bool ret = false; - uint8_t event; if (sprn == SPR_POWER_PMC5) { return true; @@ -156,8 +156,15 @@ static bool pmc_counting_insns(CPUPPCState *env, int sprn) return event == 0x2 || event == 0xFE; case SPR_POWER_PMC2: case SPR_POWER_PMC3: - case SPR_POWER_PMC4: return event == 0x2; + case SPR_POWER_PMC4: + /* + * Event 0xFA is the "instructions completed with run latch + * set" event. Consider it as instruction counting event. + * The caller is responsible for handling it separately + * from PM_INST_CMPL. + */ + return event == 0x2 || event == 0xFA; default: break; } @@ -171,8 +178,16 @@ void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) int sprn; for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { - if (pmc_counting_insns(env, sprn)) { - env->spr[sprn] += num_insns; + uint8_t event = get_PMC_event(env, sprn); + + if (pmc_counting_insns(env, sprn, event)) { + if (sprn == SPR_POWER_PMC4 && event == 0xFA) { + if (env->spr[SPR_CTRL] & CTRL_RUN) { + env->spr[SPR_POWER_PMC4] += num_insns; + } + } else { + env->spr[sprn] += num_insns; + } } } } -- 2.31.1