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Tue, 31 Aug 2021 11:06:39 +0000 From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v4 0/4] QEMU RISC-V ACLINT Support Date: Tue, 31 Aug 2021 16:35:59 +0530 Message-Id: <20210831110603.338681-1-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MAXPR01CA0111.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:5d::29) To SJ0PR04MB7821.namprd04.prod.outlook.com (2603:10b6:a03:3ac::8) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.35.197) by MAXPR01CA0111.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:5d::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4457.18 via Frontend Transport; Tue, 31 Aug 2021 11:06:36 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3af27c4d-9944-40bf-fa05-08d96c6f67f1 X-MS-TrafficTypeDiagnostic: SJ0PR04MB7886: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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envelope-from=prvs=870f666b0=Anup.Patel@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, MSGID_FROM_MTA_HEADER=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement over the SiFive CLINT but also maintains backward compatibility with the SiFive CLINT. Latest RISC-V ACLINT specification (will be frozen soon) can be found at: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc This series: 1) Replaces SiFive CLINT implementation with RISC-V ACLINT 2) Refactors RISC-V virt machine FDT generation 3) Adds optional full ACLINT support in QEMU RISC-V virt machine This series can be found in the riscv_aclint_v4 branch at: https://github.com/avpatel/qemu.git Changes since v3: - Rebased on Alistair's CPU GPIO pins v3 series - Replaced error_report() in PATCH2 with qemu_log_mask() Changes since v2: - Addresed nit comments in PATCH2 - Update SSWI device emulation to match final ACLINT draft specification Changes since v1: - Split PATCH1 into two patches where one patch renames CLINT sources and another patch updates the implementation - Addressed comments from Alistar and Bin Anup Patel (4): hw/intc: Rename sifive_clint sources to riscv_aclint sources hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT hw/riscv: virt: Re-factor FDT generation hw/riscv: virt: Add optional ACLINT support to virt machine docs/system/riscv/virt.rst | 10 + hw/intc/Kconfig | 2 +- hw/intc/meson.build | 2 +- hw/intc/riscv_aclint.c | 460 +++++++++++++++++++++++ hw/intc/sifive_clint.c | 315 ---------------- hw/riscv/Kconfig | 12 +- hw/riscv/microchip_pfsoc.c | 11 +- hw/riscv/shakti_c.c | 13 +- hw/riscv/sifive_e.c | 13 +- hw/riscv/sifive_u.c | 11 +- hw/riscv/spike.c | 16 +- hw/riscv/virt.c | 652 ++++++++++++++++++++++----------- include/hw/intc/riscv_aclint.h | 80 ++++ include/hw/intc/sifive_clint.h | 62 ---- include/hw/riscv/virt.h | 2 + 15 files changed, 1047 insertions(+), 614 deletions(-) create mode 100644 hw/intc/riscv_aclint.c delete mode 100644 hw/intc/sifive_clint.c create mode 100644 include/hw/intc/riscv_aclint.h delete mode 100644 include/hw/intc/sifive_clint.h -- 2.25.1