* [PATCH v4 0/4] QEMU RISC-V ACLINT Support
@ 2021-08-31 11:05 Anup Patel
2021-08-31 11:06 ` [PATCH v4 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources Anup Patel
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Anup Patel @ 2021-08-31 11:05 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement
over the SiFive CLINT but also maintains backward compatibility with
the SiFive CLINT.
Latest RISC-V ACLINT specification (will be frozen soon) can be found at:
https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
This series:
1) Replaces SiFive CLINT implementation with RISC-V ACLINT
2) Refactors RISC-V virt machine FDT generation
3) Adds optional full ACLINT support in QEMU RISC-V virt machine
This series can be found in the riscv_aclint_v4 branch at:
https://github.com/avpatel/qemu.git
Changes since v3:
- Rebased on Alistair's CPU GPIO pins v3 series
- Replaced error_report() in PATCH2 with qemu_log_mask()
Changes since v2:
- Addresed nit comments in PATCH2
- Update SSWI device emulation to match final ACLINT draft specification
Changes since v1:
- Split PATCH1 into two patches where one patch renames CLINT sources
and another patch updates the implementation
- Addressed comments from Alistar and Bin
Anup Patel (4):
hw/intc: Rename sifive_clint sources to riscv_aclint sources
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
hw/riscv: virt: Re-factor FDT generation
hw/riscv: virt: Add optional ACLINT support to virt machine
docs/system/riscv/virt.rst | 10 +
hw/intc/Kconfig | 2 +-
hw/intc/meson.build | 2 +-
hw/intc/riscv_aclint.c | 460 +++++++++++++++++++++++
hw/intc/sifive_clint.c | 315 ----------------
hw/riscv/Kconfig | 12 +-
hw/riscv/microchip_pfsoc.c | 11 +-
hw/riscv/shakti_c.c | 13 +-
hw/riscv/sifive_e.c | 13 +-
hw/riscv/sifive_u.c | 11 +-
hw/riscv/spike.c | 16 +-
hw/riscv/virt.c | 652 ++++++++++++++++++++++-----------
include/hw/intc/riscv_aclint.h | 80 ++++
include/hw/intc/sifive_clint.h | 62 ----
include/hw/riscv/virt.h | 2 +
15 files changed, 1047 insertions(+), 614 deletions(-)
create mode 100644 hw/intc/riscv_aclint.c
delete mode 100644 hw/intc/sifive_clint.c
create mode 100644 include/hw/intc/riscv_aclint.h
delete mode 100644 include/hw/intc/sifive_clint.h
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources
2021-08-31 11:05 [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
@ 2021-08-31 11:06 ` Anup Patel
2021-08-31 11:06 ` [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Anup Patel @ 2021-08-31 11:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
We will be upgrading SiFive CLINT implementation into RISC-V ACLINT
implementation so let's first rename the sources.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
hw/intc/Kconfig | 2 +-
hw/intc/meson.build | 2 +-
hw/intc/{sifive_clint.c => riscv_aclint.c} | 2 +-
hw/riscv/Kconfig | 12 ++++++------
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/shakti_c.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 2 +-
include/hw/intc/{sifive_clint.h => riscv_aclint.h} | 0
11 files changed, 15 insertions(+), 15 deletions(-)
rename hw/intc/{sifive_clint.c => riscv_aclint.c} (99%)
rename include/hw/intc/{sifive_clint.h => riscv_aclint.h} (100%)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index f4694088a4..78aed93c45 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -62,7 +62,7 @@ config RX_ICU
config LOONGSON_LIOINTC
bool
-config SIFIVE_CLINT
+config RISCV_ACLINT
bool
config SIFIVE_PLIC
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 6e52a166e3..9c9338a9e4 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -46,7 +46,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
-specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
+specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
diff --git a/hw/intc/sifive_clint.c b/hw/intc/riscv_aclint.c
similarity index 99%
rename from hw/intc/sifive_clint.c
rename to hw/intc/riscv_aclint.c
index ab172d8e40..31ce990d0e 100644
--- a/hw/intc/sifive_clint.c
+++ b/hw/intc/riscv_aclint.c
@@ -26,7 +26,7 @@
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
#include "hw/qdev-properties.h"
-#include "hw/intc/sifive_clint.h"
+#include "hw/intc/riscv_aclint.h"
#include "qemu/timer.h"
#include "hw/irq.h"
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index ff75add6f3..f065e32dea 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -12,7 +12,7 @@ config MICROCHIP_PFSOC
select MCHP_PFSOC_MMUART
select MCHP_PFSOC_SYSREG
select MSI_NONBROKEN
- select SIFIVE_CLINT
+ select RISCV_ACLINT
select SIFIVE_PDMA
select SIFIVE_PLIC
select UNIMP
@@ -26,7 +26,7 @@ config SHAKTI_C
bool
select UNIMP
select SHAKTI_UART
- select SIFIVE_CLINT
+ select RISCV_ACLINT
select SIFIVE_PLIC
config RISCV_VIRT
@@ -41,7 +41,7 @@ config RISCV_VIRT
select PCI_EXPRESS_GENERIC_BRIDGE
select PFLASH_CFI01
select SERIAL
- select SIFIVE_CLINT
+ select RISCV_ACLINT
select SIFIVE_PLIC
select SIFIVE_TEST
select VIRTIO_MMIO
@@ -50,7 +50,7 @@ config RISCV_VIRT
config SIFIVE_E
bool
select MSI_NONBROKEN
- select SIFIVE_CLINT
+ select RISCV_ACLINT
select SIFIVE_GPIO
select SIFIVE_PLIC
select SIFIVE_UART
@@ -61,7 +61,7 @@ config SIFIVE_U
bool
select CADENCE
select MSI_NONBROKEN
- select SIFIVE_CLINT
+ select RISCV_ACLINT
select SIFIVE_GPIO
select SIFIVE_PDMA
select SIFIVE_PLIC
@@ -78,5 +78,5 @@ config SPIKE
select RISCV_NUMA
select HTIF
select MSI_NONBROKEN
- select SIFIVE_CLINT
+ select RISCV_ACLINT
select SIFIVE_PLIC
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index eef55f69fd..eed9e81355 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -49,7 +49,7 @@
#include "hw/riscv/boot.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/microchip_pfsoc.h"
-#include "hw/intc/sifive_clint.h"
+#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
#include "sysemu/device_tree.h"
#include "sysemu/sysemu.h"
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 09d4e1433e..f9f0a45651 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -21,7 +21,7 @@
#include "hw/riscv/shakti_c.h"
#include "qapi/error.h"
#include "hw/intc/sifive_plic.h"
-#include "hw/intc/sifive_clint.h"
+#include "hw/intc/riscv_aclint.h"
#include "sysemu/sysemu.h"
#include "hw/qdev-properties.h"
#include "exec/address-spaces.h"
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 04265c5640..a73848958e 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -41,7 +41,7 @@
#include "hw/riscv/sifive_e.h"
#include "hw/riscv/boot.h"
#include "hw/char/sifive_uart.h"
-#include "hw/intc/sifive_clint.h"
+#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_e_prci.h"
#include "chardev/char.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6766edc1d0..5a7c202dad 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -51,7 +51,7 @@
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "hw/char/sifive_uart.h"
-#include "hw/intc/sifive_clint.h"
+#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
#include "chardev/char.h"
#include "net/eth.h"
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index aae36f2cb4..690c19c12a 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -35,7 +35,7 @@
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
#include "hw/char/riscv_htif.h"
-#include "hw/intc/sifive_clint.h"
+#include "hw/intc/riscv_aclint.h"
#include "chardev/char.h"
#include "sysemu/device_tree.h"
#include "sysemu/sysemu.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 47f1beb473..df33fd74c2 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -32,7 +32,7 @@
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
-#include "hw/intc/sifive_clint.h"
+#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_test.h"
#include "chardev/char.h"
diff --git a/include/hw/intc/sifive_clint.h b/include/hw/intc/riscv_aclint.h
similarity index 100%
rename from include/hw/intc/sifive_clint.h
rename to include/hw/intc/riscv_aclint.h
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
2021-08-31 11:05 [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
2021-08-31 11:06 ` [PATCH v4 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources Anup Patel
@ 2021-08-31 11:06 ` Anup Patel
2021-09-08 6:14 ` Bin Meng
2021-08-31 11:06 ` [PATCH v4 3/4] hw/riscv: virt: Re-factor FDT generation Anup Patel
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Anup Patel @ 2021-08-31 11:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis
The RISC-V ACLINT is more modular and backward compatible with
original SiFive CLINT so instead of duplicating the original
SiFive CLINT implementation we upgrade the current SiFive CLINT
implementation to RISC-V ACLINT implementation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aclint.c | 373 +++++++++++++++++++++++----------
hw/riscv/microchip_pfsoc.c | 9 +-
hw/riscv/shakti_c.c | 11 +-
hw/riscv/sifive_e.c | 11 +-
hw/riscv/sifive_u.c | 9 +-
hw/riscv/spike.c | 14 +-
hw/riscv/virt.c | 14 +-
include/hw/intc/riscv_aclint.h | 54 +++--
8 files changed, 339 insertions(+), 156 deletions(-)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index 31ce990d0e..f1a5d3d284 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -1,8 +1,10 @@
/*
- * SiFive CLINT (Core Local Interruptor)
+ * RISC-V ACLINT (Advanced Core Local Interruptor)
+ * URL: https://github.com/riscv/riscv-aclint
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
*
* This provides real-time clock, timer and interprocessor interrupts.
*
@@ -22,6 +24,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
+#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
@@ -30,10 +33,10 @@
#include "qemu/timer.h"
#include "hw/irq.h"
-typedef struct sifive_clint_callback {
- SiFiveCLINTState *s;
+typedef struct riscv_aclint_mtimer_callback {
+ RISCVAclintMTimerState *s;
int num;
-} sifive_clint_callback;
+} riscv_aclint_mtimer_callback;
static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
{
@@ -45,10 +48,11 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
* Called when timecmp is written to update the QEMU timer or immediately
* trigger timer interrupt if mtimecmp <= current timer value.
*/
-static void sifive_clint_write_timecmp(SiFiveCLINTState *s, RISCVCPU *cpu,
- int hartid,
- uint64_t value,
- uint32_t timebase_freq)
+static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
+ RISCVCPU *cpu,
+ int hartid,
+ uint64_t value,
+ uint32_t timebase_freq)
{
uint64_t next;
uint64_t diff;
@@ -57,14 +61,16 @@ static void sifive_clint_write_timecmp(SiFiveCLINTState *s, RISCVCPU *cpu,
cpu->env.timecmp = value;
if (cpu->env.timecmp <= rtc_r) {
- /* if we're setting an MTIMECMP value in the "past",
- immediately raise the timer interrupt */
- qemu_irq_raise(s->timer_irqs[hartid - s->hartid_base]);
+ /*
+ * If we're setting an MTIMECMP value in the "past",
+ * immediately raise the timer interrupt
+ */
+ qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
return;
}
/* otherwise, set up the future timer interrupt */
- qemu_irq_lower(s->timer_irqs[hartid - s->hartid_base]);
+ qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
diff = cpu->env.timecmp - rtc_r;
/* back to ns (note args switched in muldiv64) */
uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
@@ -97,38 +103,28 @@ static void sifive_clint_write_timecmp(SiFiveCLINTState *s, RISCVCPU *cpu,
* Callback used when the timer set using timer_mod expires.
* Should raise the timer interrupt line
*/
-static void sifive_clint_timer_cb(void *opaque)
+static void riscv_aclint_mtimer_cb(void *opaque)
{
- sifive_clint_callback *state = opaque;
+ riscv_aclint_mtimer_callback *state = opaque;
qemu_irq_raise(state->s->timer_irqs[state->num]);
}
-/* CPU wants to read rtc or timecmp register */
-static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
+/* CPU read MTIMER register */
+static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
+ unsigned size)
{
- SiFiveCLINTState *clint = opaque;
- if (addr >= clint->sip_base &&
- addr < clint->sip_base + (clint->num_harts << 2)) {
- size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
- CPUState *cpu = qemu_get_cpu(hartid);
- CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
- if (!env) {
- error_report("clint: invalid timecmp hartid: %zu", hartid);
- } else if ((addr & 0x3) == 0) {
- return (env->mip & MIP_MSIP) > 0;
- } else {
- error_report("clint: invalid read: %08x", (uint32_t)addr);
- return 0;
- }
- } else if (addr >= clint->timecmp_base &&
- addr < clint->timecmp_base + (clint->num_harts << 3)) {
- size_t hartid = clint->hartid_base +
- ((addr - clint->timecmp_base) >> 3);
+ RISCVAclintMTimerState *mtimer = opaque;
+
+ if (addr >= mtimer->timecmp_base &&
+ addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
+ size_t hartid = mtimer->hartid_base +
+ ((addr - mtimer->timecmp_base) >> 3);
CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
- error_report("clint: invalid timecmp hartid: %zu", hartid);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "aclint-mtimer: invalid hartid: %zu", hartid);
} else if ((addr & 0x7) == 0) {
/* timecmp_lo */
uint64_t timecmp = env->timecmp;
@@ -138,79 +134,76 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
uint64_t timecmp = env->timecmp;
return (timecmp >> 32) & 0xFFFFFFFF;
} else {
- error_report("clint: invalid read: %08x", (uint32_t)addr);
+ qemu_log_mask(LOG_UNIMP,
+ "aclint-mtimer: invalid read: %08x", (uint32_t)addr);
return 0;
}
- } else if (addr == clint->time_base) {
+ } else if (addr == mtimer->time_base) {
/* time_lo */
- return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF;
- } else if (addr == clint->time_base + 4) {
+ return cpu_riscv_read_rtc(mtimer->timebase_freq) & 0xFFFFFFFF;
+ } else if (addr == mtimer->time_base + 4) {
/* time_hi */
- return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFFFF;
+ return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF;
}
- error_report("clint: invalid read: %08x", (uint32_t)addr);
+ qemu_log_mask(LOG_UNIMP,
+ "aclint-mtimer: invalid read: %08x", (uint32_t)addr);
return 0;
}
-/* CPU wrote to rtc or timecmp register */
-static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
- unsigned size)
+/* CPU write MTIMER register */
+static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
- SiFiveCLINTState *clint = opaque;
+ RISCVAclintMTimerState *mtimer = opaque;
- if (addr >= clint->sip_base &&
- addr < clint->sip_base + (clint->num_harts << 2)) {
- size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
- CPUState *cpu = qemu_get_cpu(hartid);
- CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
- if (!env) {
- error_report("clint: invalid timecmp hartid: %zu", hartid);
- } else if ((addr & 0x3) == 0) {
- qemu_set_irq(clint->soft_irqs[hartid - clint->hartid_base], value);
- } else {
- error_report("clint: invalid sip write: %08x", (uint32_t)addr);
- }
- return;
- } else if (addr >= clint->timecmp_base &&
- addr < clint->timecmp_base + (clint->num_harts << 3)) {
- size_t hartid = clint->hartid_base +
- ((addr - clint->timecmp_base) >> 3);
+ if (addr >= mtimer->timecmp_base &&
+ addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
+ size_t hartid = mtimer->hartid_base +
+ ((addr - mtimer->timecmp_base) >> 3);
CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
- error_report("clint: invalid timecmp hartid: %zu", hartid);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "aclint-mtimer: invalid hartid: %zu", hartid);
} else if ((addr & 0x7) == 0) {
/* timecmp_lo */
uint64_t timecmp_hi = env->timecmp >> 32;
- sifive_clint_write_timecmp(clint, RISCV_CPU(cpu), hartid,
- timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_freq);
+ riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
+ timecmp_hi << 32 | (value & 0xFFFFFFFF),
+ mtimer->timebase_freq);
return;
} else if ((addr & 0x7) == 4) {
/* timecmp_hi */
uint64_t timecmp_lo = env->timecmp;
- sifive_clint_write_timecmp(clint, RISCV_CPU(cpu), hartid,
- value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_freq);
+ riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
+ value << 32 | (timecmp_lo & 0xFFFFFFFF),
+ mtimer->timebase_freq);
} else {
- error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
+ qemu_log_mask(LOG_UNIMP,
+ "aclint-mtimer: invalid timecmp write: %08x",
+ (uint32_t)addr);
}
return;
- } else if (addr == clint->time_base) {
+ } else if (addr == mtimer->time_base) {
/* time_lo */
- error_report("clint: time_lo write not implemented");
+ qemu_log_mask(LOG_UNIMP,
+ "aclint-mtimer: time_lo write not implemented");
return;
- } else if (addr == clint->time_base + 4) {
+ } else if (addr == mtimer->time_base + 4) {
/* time_hi */
- error_report("clint: time_hi write not implemented");
+ qemu_log_mask(LOG_UNIMP,
+ "aclint-mtimer: time_hi write not implemented");
return;
}
- error_report("clint: invalid write: %08x", (uint32_t)addr);
+ qemu_log_mask(LOG_UNIMP,
+ "aclint-mtimer: invalid write: %08x", (uint32_t)addr);
}
-static const MemoryRegionOps sifive_clint_ops = {
- .read = sifive_clint_read,
- .write = sifive_clint_write,
+static const MemoryRegionOps riscv_aclint_mtimer_ops = {
+ .read = riscv_aclint_mtimer_read,
+ .write = riscv_aclint_mtimer_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
@@ -218,66 +211,75 @@ static const MemoryRegionOps sifive_clint_ops = {
}
};
-static Property sifive_clint_properties[] = {
- DEFINE_PROP_UINT32("hartid-base", SiFiveCLINTState, hartid_base, 0),
- DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
- DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
- DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
- DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
- DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
- DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0),
+static Property riscv_aclint_mtimer_properties[] = {
+ DEFINE_PROP_UINT32("hartid-base", RISCVAclintMTimerState,
+ hartid_base, 0),
+ DEFINE_PROP_UINT32("num-harts", RISCVAclintMTimerState, num_harts, 1),
+ DEFINE_PROP_UINT32("timecmp-base", RISCVAclintMTimerState,
+ timecmp_base, RISCV_ACLINT_DEFAULT_MTIMECMP),
+ DEFINE_PROP_UINT32("time-base", RISCVAclintMTimerState,
+ time_base, RISCV_ACLINT_DEFAULT_MTIME),
+ DEFINE_PROP_UINT32("aperture-size", RISCVAclintMTimerState,
+ aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE),
+ DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState,
+ timebase_freq, 0),
DEFINE_PROP_END_OF_LIST(),
};
-static void sifive_clint_realize(DeviceState *dev, Error **errp)
+static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
{
- SiFiveCLINTState *s = SIFIVE_CLINT(dev);
- memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_clint_ops, s,
- TYPE_SIFIVE_CLINT, s->aperture_size);
+ RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev);
+ int i;
+
+ memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops,
+ s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
s->timer_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts);
- s->soft_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
- qdev_init_gpio_out(dev, s->soft_irqs, s->num_harts);
+ /* Claim timer interrupt bits */
+ for (i = 0; i < s->num_harts; i++) {
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
+ if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
+ error_report("MTIP already claimed");
+ exit(1);
+ }
+ }
}
-static void sifive_clint_class_init(ObjectClass *klass, void *data)
+static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->realize = sifive_clint_realize;
- device_class_set_props(dc, sifive_clint_properties);
+ dc->realize = riscv_aclint_mtimer_realize;
+ device_class_set_props(dc, riscv_aclint_mtimer_properties);
}
-static const TypeInfo sifive_clint_info = {
- .name = TYPE_SIFIVE_CLINT,
+static const TypeInfo riscv_aclint_mtimer_info = {
+ .name = TYPE_RISCV_ACLINT_MTIMER,
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(SiFiveCLINTState),
- .class_init = sifive_clint_class_init,
+ .instance_size = sizeof(RISCVAclintMTimerState),
+ .class_init = riscv_aclint_mtimer_class_init,
};
-static void sifive_clint_register_types(void)
-{
- type_register_static(&sifive_clint_info);
-}
-
-type_init(sifive_clint_register_types)
-
/*
- * Create CLINT device.
+ * Create ACLINT MTIMER device.
*/
-DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
- uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
+DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
+ uint32_t hartid_base, uint32_t num_harts,
uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
bool provide_rdtime)
{
int i;
+ DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER);
+
+ assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
+ assert(!(addr & 0x7));
+ assert(!(timecmp_base & 0x7));
+ assert(!(time_base & 0x7));
- DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT);
qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
qdev_prop_set_uint32(dev, "num-harts", num_harts);
- qdev_prop_set_uint32(dev, "sip-base", sip_base);
qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
qdev_prop_set_uint32(dev, "time-base", time_base);
qdev_prop_set_uint32(dev, "aperture-size", size);
@@ -289,7 +291,8 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
CPUState *cpu = qemu_get_cpu(hartid_base + i);
RISCVCPU *rvcpu = RISCV_CPU(cpu);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
- sifive_clint_callback *cb = g_malloc0(sizeof(sifive_clint_callback));
+ riscv_aclint_mtimer_callback *cb =
+ g_malloc0(sizeof(riscv_aclint_mtimer_callback));
if (!env) {
g_free(cb);
@@ -299,17 +302,159 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
}
- cb->s = SIFIVE_CLINT(dev);
+ cb->s = RISCV_ACLINT_MTIMER(dev);
cb->num = i;
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- &sifive_clint_timer_cb, cb);
+ &riscv_aclint_mtimer_cb, cb);
env->timecmp = 0;
qdev_connect_gpio_out(dev, i,
qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER));
- qdev_connect_gpio_out(dev, num_harts + i,
- qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_SOFT));
}
return dev;
}
+
+/* CPU read [M|S]SWI register */
+static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ RISCVAclintSwiState *swi = opaque;
+
+ if (addr < (swi->num_harts << 2)) {
+ size_t hartid = swi->hartid_base + (addr >> 2);
+ CPUState *cpu = qemu_get_cpu(hartid);
+ CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+ if (!env) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "aclint-swi: invalid hartid: %zu", hartid);
+ } else if ((addr & 0x3) == 0) {
+ return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0);
+ }
+ }
+
+ qemu_log_mask(LOG_UNIMP,
+ "aclint-swi: invalid read: %08x", (uint32_t)addr);
+ return 0;
+}
+
+/* CPU write [M|S]SWI register */
+static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ RISCVAclintSwiState *swi = opaque;
+
+ if (addr < (swi->num_harts << 2)) {
+ size_t hartid = swi->hartid_base + (addr >> 2);
+ CPUState *cpu = qemu_get_cpu(hartid);
+ CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+ if (!env) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "aclint-swi: invalid hartid: %zu", hartid);
+ } else if ((addr & 0x3) == 0) {
+ if (value & 0x1) {
+ qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]);
+ } else {
+ if (!swi->sswi) {
+ qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]);
+ }
+ }
+ return;
+ }
+ }
+
+ qemu_log_mask(LOG_UNIMP,
+ "aclint-swi: invalid write: %08x", (uint32_t)addr);
+}
+
+static const MemoryRegionOps riscv_aclint_swi_ops = {
+ .read = riscv_aclint_swi_read,
+ .write = riscv_aclint_swi_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+};
+
+static Property riscv_aclint_swi_properties[] = {
+ DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0),
+ DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1),
+ DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
+{
+ RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(dev);
+ int i;
+
+ memory_region_init_io(&swi->mmio, OBJECT(dev), &riscv_aclint_swi_ops, swi,
+ TYPE_RISCV_ACLINT_SWI, RISCV_ACLINT_SWI_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &swi->mmio);
+
+ swi->soft_irqs = g_malloc(sizeof(qemu_irq) * swi->num_harts);
+ qdev_init_gpio_out(dev, swi->soft_irqs, swi->num_harts);
+
+ /* Claim software interrupt bits */
+ for (i = 0; i < swi->num_harts; i++) {
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
+ /* We don't claim mip.SSIP because it is writeable by software */
+ if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
+ error_report("MSIP already claimed");
+ exit(1);
+ }
+ }
+}
+
+static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = riscv_aclint_swi_realize;
+ device_class_set_props(dc, riscv_aclint_swi_properties);
+}
+
+static const TypeInfo riscv_aclint_swi_info = {
+ .name = TYPE_RISCV_ACLINT_SWI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RISCVAclintSwiState),
+ .class_init = riscv_aclint_swi_class_init,
+};
+
+/*
+ * Create ACLINT [M|S]SWI device.
+ */
+DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
+ uint32_t num_harts, bool sswi)
+{
+ int i;
+ DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_SWI);
+
+ assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
+ assert(!(addr & 0x3));
+
+ qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
+ qdev_prop_set_uint32(dev, "num-harts", num_harts);
+ qdev_prop_set_uint32(dev, "sswi", sswi ? true : false);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+
+ for (i = 0; i < num_harts; i++) {
+ CPUState *cpu = qemu_get_cpu(hartid_base + i);
+ RISCVCPU *rvcpu = RISCV_CPU(cpu);
+
+ qdev_connect_gpio_out(dev, i,
+ qdev_get_gpio_in(DEVICE(rvcpu),
+ (sswi) ? IRQ_S_SOFT : IRQ_M_SOFT));
+ }
+
+ return dev;
+}
+
+static void riscv_aclint_register_types(void)
+{
+ type_register_static(&riscv_aclint_mtimer_info);
+ type_register_static(&riscv_aclint_swi_info);
+}
+
+type_init(riscv_aclint_register_types)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index eed9e81355..e475b6d511 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -234,9 +234,12 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
/* CLINT */
- sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
- memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base,
+ 0, ms->smp.cpus, false);
+ riscv_aclint_mtimer_create(
+ memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
CLINT_TIMEBASE_FREQ, false);
/* L2 cache controller */
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index f9f0a45651..2f084d3c8d 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -124,10 +124,13 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
SHAKTI_C_PLIC_CONTEXT_STRIDE,
shakti_c_memmap[SHAKTI_C_PLIC].size);
- sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
- shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
+ 0, 1, false);
+ riscv_aclint_mtimer_create(shakti_c_memmap[SHAKTI_C_CLINT].base +
+ RISCV_ACLINT_SWI_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, 1,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index a73848958e..6e95ea5896 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -207,10 +207,13 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_E_PLIC_CONTEXT_BASE,
SIFIVE_E_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_E_DEV_PLIC].size);
- sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
- memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
+ 0, ms->smp.cpus, false);
+ riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
+ RISCV_ACLINT_SWI_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
create_unimplemented_device("riscv.sifive.e.aon",
memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5a7c202dad..c680bcb161 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -847,9 +847,12 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
- sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
- memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0,
+ ms->smp.cpus, false);
+ riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base +
+ RISCV_ACLINT_SWI_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
CLINT_TIMEBASE_FREQ, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 690c19c12a..79ae355ae2 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -84,7 +84,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/cpus");
qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
- SIFIVE_CLINT_TIMEBASE_FREQ);
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
@@ -227,11 +227,15 @@ static void spike_board_init(MachineState *machine)
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
/* Core Local Interruptor (timer and IPI) for each socket */
- sifive_clint_create(
+ riscv_aclint_swi_create(
memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
- memmap[SPIKE_CLINT].size, base_hartid, hart_count,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ base_hartid, hart_count, false);
+ riscv_aclint_mtimer_create(
+ memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size +
+ RISCV_ACLINT_SWI_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
}
/* register system main memory (actual RAM) */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index df33fd74c2..1cd7ac1546 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -228,7 +228,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/cpus");
qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
- SIFIVE_CLINT_TIMEBASE_FREQ);
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
@@ -613,11 +613,15 @@ static void virt_machine_init(MachineState *machine)
sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
/* Per-socket CLINT */
- sifive_clint_create(
+ riscv_aclint_swi_create(
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
- memmap[VIRT_CLINT].size, base_hartid, hart_count,
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- SIFIVE_CLINT_TIMEBASE_FREQ, true);
+ base_hartid, hart_count, false);
+ riscv_aclint_mtimer_create(
+ memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size +
+ RISCV_ACLINT_SWI_SIZE,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
/* Per-socket PLIC hart topology configuration string */
plic_hart_config = plic_hart_config_string(hart_count);
diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h
index 921b1561dd..229bd08d25 100644
--- a/include/hw/intc/riscv_aclint.h
+++ b/include/hw/intc/riscv_aclint.h
@@ -1,8 +1,9 @@
/*
- * SiFive CLINT (Core Local Interruptor) interface
+ * RISC-V ACLINT (Advanced Core Local Interruptor) interface
*
* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
* Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -17,17 +18,17 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef HW_SIFIVE_CLINT_H
-#define HW_SIFIVE_CLINT_H
+#ifndef HW_RISCV_ACLINT_H
+#define HW_RISCV_ACLINT_H
#include "hw/sysbus.h"
-#define TYPE_SIFIVE_CLINT "riscv.sifive.clint"
+#define TYPE_RISCV_ACLINT_MTIMER "riscv.aclint.mtimer"
-#define SIFIVE_CLINT(obj) \
- OBJECT_CHECK(SiFiveCLINTState, (obj), TYPE_SIFIVE_CLINT)
+#define RISCV_ACLINT_MTIMER(obj) \
+ OBJECT_CHECK(RISCVAclintMTimerState, (obj), TYPE_RISCV_ACLINT_MTIMER)
-typedef struct SiFiveCLINTState {
+typedef struct RISCVAclintMTimerState {
/*< private >*/
SysBusDevice parent_obj;
@@ -35,28 +36,45 @@ typedef struct SiFiveCLINTState {
MemoryRegion mmio;
uint32_t hartid_base;
uint32_t num_harts;
- uint32_t sip_base;
uint32_t timecmp_base;
uint32_t time_base;
uint32_t aperture_size;
uint32_t timebase_freq;
qemu_irq *timer_irqs;
- qemu_irq *soft_irqs;
-} SiFiveCLINTState;
+} RISCVAclintMTimerState;
-DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
- uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
+DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
+ uint32_t hartid_base, uint32_t num_harts,
uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
bool provide_rdtime);
-enum {
- SIFIVE_SIP_BASE = 0x0,
- SIFIVE_TIMECMP_BASE = 0x4000,
- SIFIVE_TIME_BASE = 0xBFF8
-};
+#define TYPE_RISCV_ACLINT_SWI "riscv.aclint.swi"
+
+#define RISCV_ACLINT_SWI(obj) \
+ OBJECT_CHECK(RISCVAclintSwiState, (obj), TYPE_RISCV_ACLINT_SWI)
+
+typedef struct RISCVAclintSwiState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion mmio;
+ uint32_t hartid_base;
+ uint32_t num_harts;
+ uint32_t sswi;
+ qemu_irq *soft_irqs;
+} RISCVAclintSwiState;
+
+DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
+ uint32_t num_harts, bool sswi);
enum {
- SIFIVE_CLINT_TIMEBASE_FREQ = 10000000
+ RISCV_ACLINT_DEFAULT_MTIMECMP = 0x0,
+ RISCV_ACLINT_DEFAULT_MTIME = 0x7ff8,
+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE = 0x8000,
+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ = 10000000,
+ RISCV_ACLINT_MAX_HARTS = 4095,
+ RISCV_ACLINT_SWI_SIZE = 0x4000
};
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 3/4] hw/riscv: virt: Re-factor FDT generation
2021-08-31 11:05 [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
2021-08-31 11:06 ` [PATCH v4 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources Anup Patel
2021-08-31 11:06 ` [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel
@ 2021-08-31 11:06 ` Anup Patel
2021-08-31 11:06 ` [PATCH v4 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine Anup Patel
2021-09-29 4:07 ` [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
4 siblings, 0 replies; 9+ messages in thread
From: Anup Patel @ 2021-08-31 11:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
We re-factor and break the FDT generation into smaller functions
so that it is easier to modify FDT generation for different
configurations of virt machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
hw/riscv/virt.c | 527 ++++++++++++++++++++++++++++++------------------
1 file changed, 327 insertions(+), 200 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 1cd7ac1546..7f716901ef 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -176,214 +176,262 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
0x1800, 0, 0, 0x7);
}
-static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
- uint64_t mem_size, const char *cmdline, bool is_32_bit)
+static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
+ char *clust_name, uint32_t *phandle,
+ bool is_32_bit, uint32_t *intc_phandles)
{
- void *fdt;
- int i, cpu, socket;
+ int cpu;
+ uint32_t cpu_phandle;
MachineState *mc = MACHINE(s);
+ char *name, *cpu_name, *core_name, *intc_name;
+
+ for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
+ cpu_phandle = (*phandle)++;
+
+ cpu_name = g_strdup_printf("/cpus/cpu@%d",
+ s->soc[socket].hartid_base + cpu);
+ qemu_fdt_add_subnode(mc->fdt, cpu_name);
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+ (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
+ name = riscv_isa_string(&s->soc[socket].harts[cpu]);
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
+ g_free(name);
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
+ qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
+ s->soc[socket].hartid_base + cpu);
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
+ riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
+ qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
+
+ intc_phandles[cpu] = (*phandle)++;
+
+ intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
+ qemu_fdt_add_subnode(mc->fdt, intc_name);
+ qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
+ intc_phandles[cpu]);
+ qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+ "riscv,cpu-intc");
+ qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
+
+ core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
+ qemu_fdt_add_subnode(mc->fdt, core_name);
+ qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
+
+ g_free(core_name);
+ g_free(intc_name);
+ g_free(cpu_name);
+ }
+}
+
+static void create_fdt_socket_memory(RISCVVirtState *s,
+ const MemMapEntry *memmap, int socket)
+{
+ char *mem_name;
uint64_t addr, size;
- uint32_t *clint_cells, *plic_cells;
- unsigned long clint_addr, plic_addr;
- uint32_t plic_phandle[MAX_NODES];
- uint32_t cpu_phandle, intc_phandle, test_phandle;
- uint32_t phandle = 1, plic_mmio_phandle = 1;
- uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
- char *mem_name, *cpu_name, *core_name, *intc_name;
- char *name, *clint_name, *plic_name, *clust_name;
- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
- hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
+ MachineState *mc = MACHINE(s);
+
+ addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
+ size = riscv_socket_mem_size(mc, socket);
+ mem_name = g_strdup_printf("/memory@%lx", (long)addr);
+ qemu_fdt_add_subnode(mc->fdt, mem_name);
+ qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
+ addr >> 32, addr, size >> 32, size);
+ qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
+ riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
+ g_free(mem_name);
+}
+
+static void create_fdt_socket_clint(RISCVVirtState *s,
+ const MemMapEntry *memmap, int socket,
+ uint32_t *intc_phandles)
+{
+ int cpu;
+ char *clint_name;
+ uint32_t *clint_cells;
+ unsigned long clint_addr;
+ MachineState *mc = MACHINE(s);
static const char * const clint_compat[2] = {
"sifive,clint0", "riscv,clint0"
};
+
+ clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
+ clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
+ clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
+ }
+
+ clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
+ clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
+ qemu_fdt_add_subnode(mc->fdt, clint_name);
+ qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
+ (char **)&clint_compat,
+ ARRAY_SIZE(clint_compat));
+ qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
+ 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
+ qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
+ clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+ riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
+ g_free(clint_name);
+
+ g_free(clint_cells);
+}
+
+static void create_fdt_socket_plic(RISCVVirtState *s,
+ const MemMapEntry *memmap, int socket,
+ uint32_t *phandle, uint32_t *intc_phandles,
+ uint32_t *plic_phandles)
+{
+ int cpu;
+ char *plic_name;
+ uint32_t *plic_cells;
+ unsigned long plic_addr;
+ MachineState *mc = MACHINE(s);
static const char * const plic_compat[2] = {
"sifive,plic-1.0.0", "riscv,plic0"
};
- if (mc->dtb) {
- fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
- if (!fdt) {
- error_report("load_device_tree() failed");
- exit(1);
- }
- goto update_bootargs;
- } else {
- fdt = mc->fdt = create_device_tree(&s->fdt_size);
- if (!fdt) {
- error_report("create_device_tree() failed");
- exit(1);
- }
+ plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
+ plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
+ plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
}
- qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
- qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
- qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
- qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
+ plic_phandles[socket] = (*phandle)++;
+ plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
+ plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
+ qemu_fdt_add_subnode(mc->fdt, plic_name);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ "#address-cells", FDT_PLIC_ADDR_CELLS);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name,
+ "#interrupt-cells", FDT_PLIC_INT_CELLS);
+ qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
+ (char **)&plic_compat,
+ ARRAY_SIZE(plic_compat));
+ qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
+ plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+ qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
+ 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
+ riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
+ plic_phandles[socket]);
+ g_free(plic_name);
+
+ g_free(plic_cells);
+}
- qemu_fdt_add_subnode(fdt, "/soc");
- qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
- qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
- qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
- qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
+static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
+ bool is_32_bit, uint32_t *phandle,
+ uint32_t *irq_mmio_phandle,
+ uint32_t *irq_pcie_phandle,
+ uint32_t *irq_virtio_phandle)
+{
+ int socket;
+ char *clust_name;
+ uint32_t *intc_phandles;
+ MachineState *mc = MACHINE(s);
+ uint32_t xplic_phandles[MAX_NODES];
- qemu_fdt_add_subnode(fdt, "/cpus");
- qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
+ qemu_fdt_add_subnode(mc->fdt, "/cpus");
+ qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
- qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
- qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
- qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
+ qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
+ qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
- qemu_fdt_add_subnode(fdt, clust_name);
-
- plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
- clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
-
- for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
- cpu_phandle = phandle++;
-
- cpu_name = g_strdup_printf("/cpus/cpu@%d",
- s->soc[socket].hartid_base + cpu);
- qemu_fdt_add_subnode(fdt, cpu_name);
- if (is_32_bit) {
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
- } else {
- qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
- }
- name = riscv_isa_string(&s->soc[socket].harts[cpu]);
- qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
- g_free(name);
- qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
- qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
- qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
- s->soc[socket].hartid_base + cpu);
- qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
- riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
- qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
-
- intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
- qemu_fdt_add_subnode(fdt, intc_name);
- intc_phandle = phandle++;
- qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
- qemu_fdt_setprop_string(fdt, intc_name, "compatible",
- "riscv,cpu-intc");
- qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
-
- clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
- clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
- clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
- clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
-
- plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
- plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
- plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
- plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
-
- core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
- qemu_fdt_add_subnode(fdt, core_name);
- qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
-
- g_free(core_name);
- g_free(intc_name);
- g_free(cpu_name);
- }
+ qemu_fdt_add_subnode(mc->fdt, clust_name);
+
+ intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts);
+
+ create_fdt_socket_cpus(s, socket, clust_name, phandle,
+ is_32_bit, intc_phandles);
- addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
- size = riscv_socket_mem_size(mc, socket);
- mem_name = g_strdup_printf("/memory@%lx", (long)addr);
- qemu_fdt_add_subnode(fdt, mem_name);
- qemu_fdt_setprop_cells(fdt, mem_name, "reg",
- addr >> 32, addr, size >> 32, size);
- qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
- riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
- g_free(mem_name);
-
- clint_addr = memmap[VIRT_CLINT].base +
- (memmap[VIRT_CLINT].size * socket);
- clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
- qemu_fdt_add_subnode(fdt, clint_name);
- qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
- (char **)&clint_compat, ARRAY_SIZE(clint_compat));
- qemu_fdt_setprop_cells(fdt, clint_name, "reg",
- 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
- qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
- clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
- riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
- g_free(clint_name);
-
- plic_phandle[socket] = phandle++;
- plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
- plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
- qemu_fdt_add_subnode(fdt, plic_name);
- qemu_fdt_setprop_cell(fdt, plic_name,
- "#address-cells", FDT_PLIC_ADDR_CELLS);
- qemu_fdt_setprop_cell(fdt, plic_name,
- "#interrupt-cells", FDT_PLIC_INT_CELLS);
- qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
- (char **)&plic_compat, ARRAY_SIZE(plic_compat));
- qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
- plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
- qemu_fdt_setprop_cells(fdt, plic_name, "reg",
- 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
- qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
- riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
- qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
- g_free(plic_name);
-
- g_free(clint_cells);
- g_free(plic_cells);
+ create_fdt_socket_memory(s, memmap, socket);
+
+ create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+
+ create_fdt_socket_plic(s, memmap, socket, phandle,
+ intc_phandles, xplic_phandles);
+
+ g_free(intc_phandles);
g_free(clust_name);
}
for (socket = 0; socket < riscv_socket_count(mc); socket++) {
if (socket == 0) {
- plic_mmio_phandle = plic_phandle[socket];
- plic_virtio_phandle = plic_phandle[socket];
- plic_pcie_phandle = plic_phandle[socket];
+ *irq_mmio_phandle = xplic_phandles[socket];
+ *irq_virtio_phandle = xplic_phandles[socket];
+ *irq_pcie_phandle = xplic_phandles[socket];
}
if (socket == 1) {
- plic_virtio_phandle = plic_phandle[socket];
- plic_pcie_phandle = plic_phandle[socket];
+ *irq_virtio_phandle = xplic_phandles[socket];
+ *irq_pcie_phandle = xplic_phandles[socket];
}
if (socket == 2) {
- plic_pcie_phandle = plic_phandle[socket];
+ *irq_pcie_phandle = xplic_phandles[socket];
}
}
- riscv_socket_fdt_write_distance_matrix(mc, fdt);
+ riscv_socket_fdt_write_distance_matrix(mc, mc->fdt);
+}
+
+static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
+ uint32_t irq_virtio_phandle)
+{
+ int i;
+ char *name;
+ MachineState *mc = MACHINE(s);
for (i = 0; i < VIRTIO_COUNT; i++) {
name = g_strdup_printf("/soc/virtio_mmio@%lx",
(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
- qemu_fdt_setprop_cells(fdt, name, "reg",
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
0x0, memmap[VIRT_VIRTIO].size);
- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
- plic_virtio_phandle);
- qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
+ irq_virtio_phandle);
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", VIRTIO_IRQ + i);
g_free(name);
}
+}
+
+static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
+ uint32_t irq_pcie_phandle)
+{
+ char *name;
+ MachineState *mc = MACHINE(s);
name = g_strdup_printf("/soc/pci@%lx",
(long) memmap[VIRT_PCIE_ECAM].base);
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
- qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
- qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
- qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
- qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
- qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
- qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
+ FDT_PCI_ADDR_CELLS);
+ qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
+ FDT_PCI_INT_CELLS);
+ qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ "pci-host-ecam-generic");
+ qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
+ qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
+ qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
- qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
- qemu_fdt_setprop_cells(fdt, name, "reg", 0,
+ qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
- qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
+ qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
1, FDT_PCI_RANGE_IOPORT, 2, 0,
2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
1, FDT_PCI_RANGE_MMIO,
@@ -393,66 +441,96 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
2, virt_high_pcie_memmap.base,
2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
- create_pcie_irq_map(fdt, name, plic_pcie_phandle);
+ create_pcie_irq_map(mc->fdt, name, irq_pcie_phandle);
g_free(name);
+}
- test_phandle = phandle++;
+static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
+ uint32_t *phandle)
+{
+ char *name;
+ uint32_t test_phandle;
+ MachineState *mc = MACHINE(s);
+
+ test_phandle = (*phandle)++;
name = g_strdup_printf("/soc/test@%lx",
(long)memmap[VIRT_TEST].base);
- qemu_fdt_add_subnode(fdt, name);
+ qemu_fdt_add_subnode(mc->fdt, name);
{
static const char * const compat[3] = {
"sifive,test1", "sifive,test0", "syscon"
};
- qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat,
- ARRAY_SIZE(compat));
+ qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
+ (char **)&compat, ARRAY_SIZE(compat));
}
- qemu_fdt_setprop_cells(fdt, name, "reg",
- 0x0, memmap[VIRT_TEST].base,
- 0x0, memmap[VIRT_TEST].size);
- qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
- test_phandle = qemu_fdt_get_phandle(fdt, name);
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
+ qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
+ test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
g_free(name);
name = g_strdup_printf("/soc/reboot");
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
+ qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
+ qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
+ qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
g_free(name);
name = g_strdup_printf("/soc/poweroff");
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
+ qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
+ qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
+ qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
g_free(name);
+}
+
+static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
+ uint32_t irq_mmio_phandle)
+{
+ char *name;
+ MachineState *mc = MACHINE(s);
name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
- qemu_fdt_setprop_cells(fdt, name, "reg",
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
0x0, memmap[VIRT_UART0].base,
0x0, memmap[VIRT_UART0].size);
- qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
- qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
+ qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
- qemu_fdt_add_subnode(fdt, "/chosen");
- qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
+ qemu_fdt_add_subnode(mc->fdt, "/chosen");
+ qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
g_free(name);
+}
+
+static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
+ uint32_t irq_mmio_phandle)
+{
+ char *name;
+ MachineState *mc = MACHINE(s);
name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
- qemu_fdt_add_subnode(fdt, name);
- qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
- qemu_fdt_setprop_cells(fdt, name, "reg",
- 0x0, memmap[VIRT_RTC].base,
- 0x0, memmap[VIRT_RTC].size);
- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
- qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ "google,goldfish-rtc");
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
+ irq_mmio_phandle);
+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
g_free(name);
+}
+
+static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
+{
+ char *name;
+ MachineState *mc = MACHINE(s);
+ hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
+ hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
name = g_strdup_printf("/flash@%" PRIx64, flashbase);
qemu_fdt_add_subnode(mc->fdt, name);
@@ -462,10 +540,59 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
2, flashbase + flashsize, 2, flashsize);
qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
g_free(name);
+}
+
+static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+ uint64_t mem_size, const char *cmdline, bool is_32_bit)
+{
+ MachineState *mc = MACHINE(s);
+ uint32_t phandle = 1, irq_mmio_phandle = 1;
+ uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
+
+ if (mc->dtb) {
+ mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
+ if (!mc->fdt) {
+ error_report("load_device_tree() failed");
+ exit(1);
+ }
+ goto update_bootargs;
+ } else {
+ mc->fdt = create_device_tree(&s->fdt_size);
+ if (!mc->fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
+ }
+
+ qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
+ qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
+ qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
+
+ qemu_fdt_add_subnode(mc->fdt, "/soc");
+ qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
+ qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
+ qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
+
+ create_fdt_sockets(s, memmap, is_32_bit, &phandle,
+ &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle);
+
+ create_fdt_virtio(s, memmap, irq_virtio_phandle);
+
+ create_fdt_pcie(s, memmap, irq_pcie_phandle);
+
+ create_fdt_reset(s, memmap, &phandle);
+
+ create_fdt_uart(s, memmap, irq_mmio_phandle);
+
+ create_fdt_rtc(s, memmap, irq_mmio_phandle);
+
+ create_fdt_flash(s, memmap);
update_bootargs:
if (cmdline) {
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine
2021-08-31 11:05 [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
` (2 preceding siblings ...)
2021-08-31 11:06 ` [PATCH v4 3/4] hw/riscv: virt: Re-factor FDT generation Anup Patel
@ 2021-08-31 11:06 ` Anup Patel
2021-09-29 4:07 ` [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
4 siblings, 0 replies; 9+ messages in thread
From: Anup Patel @ 2021-08-31 11:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: qemu-riscv, Anup Patel, Anup Patel, qemu-devel, Atish Patra,
Alistair Francis, Bin Meng
We extend virt machine to emulate ACLINT devices only when "aclint=on"
parameter is passed along with machine name in QEMU command-line.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
docs/system/riscv/virt.rst | 10 ++++
hw/riscv/virt.c | 113 ++++++++++++++++++++++++++++++++++++-
include/hw/riscv/virt.h | 2 +
3 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index 321d77e07d..fa016584bf 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -53,6 +53,16 @@ with the default OpenSBI firmware image as the -bios. It also supports
the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dynamic
firmware and U-Boot proper (S-mode), using the standard -bios functionality.
+Machine-specific options
+------------------------
+
+The following machine-specific options are supported:
+
+- aclint=[on|off]
+
+ When this option is "on", ACLINT devices will be emulated instead of
+ SiFive CLINT. When not specified, this option is assumed to be "off".
+
Running Linux kernel
--------------------
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 7f716901ef..ec0cb69b8c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -48,6 +48,7 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_TEST] = { 0x100000, 0x1000 },
[VIRT_RTC] = { 0x101000, 0x1000 },
[VIRT_CLINT] = { 0x2000000, 0x10000 },
+ [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
[VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
[VIRT_UART0] = { 0x10000000, 0x100 },
@@ -281,6 +282,82 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
g_free(clint_cells);
}
+static void create_fdt_socket_aclint(RISCVVirtState *s,
+ const MemMapEntry *memmap, int socket,
+ uint32_t *intc_phandles)
+{
+ int cpu;
+ char *name;
+ unsigned long addr;
+ uint32_t aclint_cells_size;
+ uint32_t *aclint_mswi_cells;
+ uint32_t *aclint_sswi_cells;
+ uint32_t *aclint_mtimer_cells;
+ MachineState *mc = MACHINE(s);
+
+ aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+ aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+ aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
+ aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
+ aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
+ }
+ aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
+
+ addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
+ name = g_strdup_printf("/soc/mswi@%lx", addr);
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mswi");
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
+ qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ aclint_mswi_cells, aclint_cells_size);
+ qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+ riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+ g_free(name);
+
+ addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
+ (memmap[VIRT_CLINT].size * socket);
+ name = g_strdup_printf("/soc/mtimer@%lx", addr);
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+ "riscv,aclint-mtimer");
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
+ 0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE -
+ RISCV_ACLINT_DEFAULT_MTIME,
+ 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
+ 0x0, RISCV_ACLINT_DEFAULT_MTIME);
+ qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ aclint_mtimer_cells, aclint_cells_size);
+ riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+ g_free(name);
+
+ addr = memmap[VIRT_ACLINT_SSWI].base +
+ (memmap[VIRT_ACLINT_SSWI].size * socket);
+ name = g_strdup_printf("/soc/sswi@%lx", addr);
+ qemu_fdt_add_subnode(mc->fdt, name);
+ qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-sswi");
+ qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+ 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
+ qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+ aclint_sswi_cells, aclint_cells_size);
+ qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
+ riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+ g_free(name);
+
+ g_free(aclint_mswi_cells);
+ g_free(aclint_mtimer_cells);
+ g_free(aclint_sswi_cells);
+}
+
static void create_fdt_socket_plic(RISCVVirtState *s,
const MemMapEntry *memmap, int socket,
uint32_t *phandle, uint32_t *intc_phandles,
@@ -359,7 +436,11 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
create_fdt_socket_memory(s, memmap, socket);
- create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+ if (s->have_aclint) {
+ create_fdt_socket_aclint(s, memmap, socket, intc_phandles);
+ } else {
+ create_fdt_socket_clint(s, memmap, socket, intc_phandles);
+ }
create_fdt_socket_plic(s, memmap, socket, phandle,
intc_phandles, xplic_phandles);
@@ -750,6 +831,14 @@ static void virt_machine_init(MachineState *machine)
RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
+ /* Per-socket ACLINT SSWI */
+ if (s->have_aclint) {
+ riscv_aclint_swi_create(
+ memmap[VIRT_ACLINT_SSWI].base +
+ i * memmap[VIRT_ACLINT_SSWI].size,
+ base_hartid, hart_count, true);
+ }
+
/* Per-socket PLIC hart topology configuration string */
plic_hart_config = plic_hart_config_string(hart_count);
@@ -914,6 +1003,22 @@ static void virt_machine_instance_init(Object *obj)
{
}
+static bool virt_get_aclint(Object *obj, Error **errp)
+{
+ MachineState *ms = MACHINE(obj);
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+
+ return s->have_aclint;
+}
+
+static void virt_set_aclint(Object *obj, bool value, Error **errp)
+{
+ MachineState *ms = MACHINE(obj);
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+
+ s->have_aclint = value;
+}
+
static void virt_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -929,6 +1034,12 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
mc->numa_mem_supported = true;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+
+ object_class_property_add_bool(oc, "aclint", virt_get_aclint,
+ virt_set_aclint);
+ object_class_property_set_description(oc, "aclint",
+ "Set on/off to enable/disable "
+ "emulating ACLINT devices");
}
static const TypeInfo virt_machine_typeinfo = {
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 349fee1f89..d9105c1886 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -43,6 +43,7 @@ struct RISCVVirtState {
FWCfgState *fw_cfg;
int fdt_size;
+ bool have_aclint;
};
enum {
@@ -51,6 +52,7 @@ enum {
VIRT_TEST,
VIRT_RTC,
VIRT_CLINT,
+ VIRT_ACLINT_SSWI,
VIRT_PLIC,
VIRT_UART0,
VIRT_VIRTIO,
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
2021-08-31 11:06 ` [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel
@ 2021-09-08 6:14 ` Bin Meng
0 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2021-09-08 6:14 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Tue, Aug 31, 2021 at 7:07 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The RISC-V ACLINT is more modular and backward compatible with
> original SiFive CLINT so instead of duplicating the original
> SiFive CLINT implementation we upgrade the current SiFive CLINT
> implementation to RISC-V ACLINT implementation.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/riscv_aclint.c | 373 +++++++++++++++++++++++----------
> hw/riscv/microchip_pfsoc.c | 9 +-
> hw/riscv/shakti_c.c | 11 +-
> hw/riscv/sifive_e.c | 11 +-
> hw/riscv/sifive_u.c | 9 +-
> hw/riscv/spike.c | 14 +-
> hw/riscv/virt.c | 14 +-
> include/hw/intc/riscv_aclint.h | 54 +++--
> 8 files changed, 339 insertions(+), 156 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 0/4] QEMU RISC-V ACLINT Support
2021-08-31 11:05 [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
` (3 preceding siblings ...)
2021-08-31 11:06 ` [PATCH v4 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine Anup Patel
@ 2021-09-29 4:07 ` Anup Patel
2021-09-29 4:22 ` Alistair Francis
4 siblings, 1 reply; 9+ messages in thread
From: Anup Patel @ 2021-09-29 4:07 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
QEMU Developers, Atish Patra, Palmer Dabbelt
On Tue, Aug 31, 2021 at 4:36 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement
> over the SiFive CLINT but also maintains backward compatibility with
> the SiFive CLINT.
>
> Latest RISC-V ACLINT specification (will be frozen soon) can be found at:
> https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>
> This series:
> 1) Replaces SiFive CLINT implementation with RISC-V ACLINT
> 2) Refactors RISC-V virt machine FDT generation
> 3) Adds optional full ACLINT support in QEMU RISC-V virt machine
>
> This series can be found in the riscv_aclint_v4 branch at:
> https://github.com/avpatel/qemu.git
>
> Changes since v3:
> - Rebased on Alistair's CPU GPIO pins v3 series
> - Replaced error_report() in PATCH2 with qemu_log_mask()
>
> Changes since v2:
> - Addresed nit comments in PATCH2
> - Update SSWI device emulation to match final ACLINT draft specification
>
> Changes since v1:
> - Split PATCH1 into two patches where one patch renames CLINT sources
> and another patch updates the implementation
> - Addressed comments from Alistar and Bin
>
> Anup Patel (4):
> hw/intc: Rename sifive_clint sources to riscv_aclint sources
> hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
> hw/riscv: virt: Re-factor FDT generation
> hw/riscv: virt: Add optional ACLINT support to virt machine
>
> docs/system/riscv/virt.rst | 10 +
> hw/intc/Kconfig | 2 +-
> hw/intc/meson.build | 2 +-
> hw/intc/riscv_aclint.c | 460 +++++++++++++++++++++++
> hw/intc/sifive_clint.c | 315 ----------------
> hw/riscv/Kconfig | 12 +-
> hw/riscv/microchip_pfsoc.c | 11 +-
> hw/riscv/shakti_c.c | 13 +-
> hw/riscv/sifive_e.c | 13 +-
> hw/riscv/sifive_u.c | 11 +-
> hw/riscv/spike.c | 16 +-
> hw/riscv/virt.c | 652 ++++++++++++++++++++++-----------
> include/hw/intc/riscv_aclint.h | 80 ++++
> include/hw/intc/sifive_clint.h | 62 ----
> include/hw/riscv/virt.h | 2 +
> 15 files changed, 1047 insertions(+), 614 deletions(-)
> create mode 100644 hw/intc/riscv_aclint.c
> delete mode 100644 hw/intc/sifive_clint.c
> create mode 100644 include/hw/intc/riscv_aclint.h
> delete mode 100644 include/hw/intc/sifive_clint.h
>
> --
> 2.25.1
>
Ping ??
Regards,
Anup
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 0/4] QEMU RISC-V ACLINT Support
2021-09-29 4:07 ` [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
@ 2021-09-29 4:22 ` Alistair Francis
2021-09-29 4:25 ` Anup Patel
0 siblings, 1 reply; 9+ messages in thread
From: Alistair Francis @ 2021-09-29 4:22 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
QEMU Developers, Atish Patra, Alistair Francis, Palmer Dabbelt
On Wed, Sep 29, 2021 at 2:09 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Aug 31, 2021 at 4:36 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement
> > over the SiFive CLINT but also maintains backward compatibility with
> > the SiFive CLINT.
> >
> > Latest RISC-V ACLINT specification (will be frozen soon) can be found at:
> > https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> >
> > This series:
> > 1) Replaces SiFive CLINT implementation with RISC-V ACLINT
> > 2) Refactors RISC-V virt machine FDT generation
> > 3) Adds optional full ACLINT support in QEMU RISC-V virt machine
> >
> > This series can be found in the riscv_aclint_v4 branch at:
> > https://github.com/avpatel/qemu.git
> >
> > Changes since v3:
> > - Rebased on Alistair's CPU GPIO pins v3 series
> > - Replaced error_report() in PATCH2 with qemu_log_mask()
> >
> > Changes since v2:
> > - Addresed nit comments in PATCH2
> > - Update SSWI device emulation to match final ACLINT draft specification
> >
> > Changes since v1:
> > - Split PATCH1 into two patches where one patch renames CLINT sources
> > and another patch updates the implementation
> > - Addressed comments from Alistar and Bin
> >
> > Anup Patel (4):
> > hw/intc: Rename sifive_clint sources to riscv_aclint sources
> > hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
> > hw/riscv: virt: Re-factor FDT generation
> > hw/riscv: virt: Add optional ACLINT support to virt machine
> >
> > docs/system/riscv/virt.rst | 10 +
> > hw/intc/Kconfig | 2 +-
> > hw/intc/meson.build | 2 +-
> > hw/intc/riscv_aclint.c | 460 +++++++++++++++++++++++
> > hw/intc/sifive_clint.c | 315 ----------------
> > hw/riscv/Kconfig | 12 +-
> > hw/riscv/microchip_pfsoc.c | 11 +-
> > hw/riscv/shakti_c.c | 13 +-
> > hw/riscv/sifive_e.c | 13 +-
> > hw/riscv/sifive_u.c | 11 +-
> > hw/riscv/spike.c | 16 +-
> > hw/riscv/virt.c | 652 ++++++++++++++++++++++-----------
> > include/hw/intc/riscv_aclint.h | 80 ++++
> > include/hw/intc/sifive_clint.h | 62 ----
> > include/hw/riscv/virt.h | 2 +
> > 15 files changed, 1047 insertions(+), 614 deletions(-)
> > create mode 100644 hw/intc/riscv_aclint.c
> > delete mode 100644 hw/intc/sifive_clint.c
> > create mode 100644 include/hw/intc/riscv_aclint.h
> > delete mode 100644 include/hw/intc/sifive_clint.h
> >
> > --
> > 2.25.1
> >
>
> Ping ??
Sorry, it looks like I forgot to reply indicating the status. This has
been merged into master
Alistair
>
> Regards,
> Anup
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 0/4] QEMU RISC-V ACLINT Support
2021-09-29 4:22 ` Alistair Francis
@ 2021-09-29 4:25 ` Anup Patel
0 siblings, 0 replies; 9+ messages in thread
From: Anup Patel @ 2021-09-29 4:25 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
QEMU Developers, Atish Patra, Alistair Francis, Palmer Dabbelt
On Wed, Sep 29, 2021 at 9:52 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Sep 29, 2021 at 2:09 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Tue, Aug 31, 2021 at 4:36 PM Anup Patel <anup.patel@wdc.com> wrote:
> > >
> > > The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement
> > > over the SiFive CLINT but also maintains backward compatibility with
> > > the SiFive CLINT.
> > >
> > > Latest RISC-V ACLINT specification (will be frozen soon) can be found at:
> > > https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> > >
> > > This series:
> > > 1) Replaces SiFive CLINT implementation with RISC-V ACLINT
> > > 2) Refactors RISC-V virt machine FDT generation
> > > 3) Adds optional full ACLINT support in QEMU RISC-V virt machine
> > >
> > > This series can be found in the riscv_aclint_v4 branch at:
> > > https://github.com/avpatel/qemu.git
> > >
> > > Changes since v3:
> > > - Rebased on Alistair's CPU GPIO pins v3 series
> > > - Replaced error_report() in PATCH2 with qemu_log_mask()
> > >
> > > Changes since v2:
> > > - Addresed nit comments in PATCH2
> > > - Update SSWI device emulation to match final ACLINT draft specification
> > >
> > > Changes since v1:
> > > - Split PATCH1 into two patches where one patch renames CLINT sources
> > > and another patch updates the implementation
> > > - Addressed comments from Alistar and Bin
> > >
> > > Anup Patel (4):
> > > hw/intc: Rename sifive_clint sources to riscv_aclint sources
> > > hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
> > > hw/riscv: virt: Re-factor FDT generation
> > > hw/riscv: virt: Add optional ACLINT support to virt machine
> > >
> > > docs/system/riscv/virt.rst | 10 +
> > > hw/intc/Kconfig | 2 +-
> > > hw/intc/meson.build | 2 +-
> > > hw/intc/riscv_aclint.c | 460 +++++++++++++++++++++++
> > > hw/intc/sifive_clint.c | 315 ----------------
> > > hw/riscv/Kconfig | 12 +-
> > > hw/riscv/microchip_pfsoc.c | 11 +-
> > > hw/riscv/shakti_c.c | 13 +-
> > > hw/riscv/sifive_e.c | 13 +-
> > > hw/riscv/sifive_u.c | 11 +-
> > > hw/riscv/spike.c | 16 +-
> > > hw/riscv/virt.c | 652 ++++++++++++++++++++++-----------
> > > include/hw/intc/riscv_aclint.h | 80 ++++
> > > include/hw/intc/sifive_clint.h | 62 ----
> > > include/hw/riscv/virt.h | 2 +
> > > 15 files changed, 1047 insertions(+), 614 deletions(-)
> > > create mode 100644 hw/intc/riscv_aclint.c
> > > delete mode 100644 hw/intc/sifive_clint.c
> > > create mode 100644 include/hw/intc/riscv_aclint.h
> > > delete mode 100644 include/hw/intc/sifive_clint.h
> > >
> > > --
> > > 2.25.1
> > >
> >
> > Ping ??
>
> Sorry, it looks like I forgot to reply indicating the status. This has
> been merged into master
Cool, thanks.
Regards,
Anup
>
> Alistair
>
> >
> > Regards,
> > Anup
> >
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-09-29 4:27 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-31 11:05 [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
2021-08-31 11:06 ` [PATCH v4 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources Anup Patel
2021-08-31 11:06 ` [PATCH v4 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel
2021-09-08 6:14 ` Bin Meng
2021-08-31 11:06 ` [PATCH v4 3/4] hw/riscv: virt: Re-factor FDT generation Anup Patel
2021-08-31 11:06 ` [PATCH v4 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine Anup Patel
2021-09-29 4:07 ` [PATCH v4 0/4] QEMU RISC-V ACLINT Support Anup Patel
2021-09-29 4:22 ` Alistair Francis
2021-09-29 4:25 ` Anup Patel
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