From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F739C432BE for ; Thu, 2 Sep 2021 10:32:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F05676103A for ; Thu, 2 Sep 2021 10:32:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F05676103A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:47330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLk1M-0000Ge-UE for qemu-devel@archiver.kernel.org; Thu, 02 Sep 2021 06:32:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrl-0005y3-E0 for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:41 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:57644 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLjrh-0001Vc-Vr for qemu-devel@nongnu.org; Thu, 02 Sep 2021 06:22:41 -0400 Received: from host86-133-17-27.range86-133.btcentralplus.com ([86.133.17.27] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1mLjrH-0000t5-UQ; Thu, 02 Sep 2021 11:22:16 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Thu, 2 Sep 2021 11:22:00 +0100 Message-Id: <20210902102205.7554-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> References: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 86.133.17.27 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 4/9] escc: introduce escc_hard_reset_chn() for hardware reset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This new hardware reset function is to be called for both channels when the hardware reset bit is written to register WR9. Its initial implementation is the same as the existing escc_reset_chn() function used for device reset. Signed-off-by: Mark Cave-Ayland --- hw/char/escc.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 935ec1aef6..691086d97d 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -331,6 +331,40 @@ static void escc_soft_reset_chn(ESCCChannelState *s) clear_queue(s); } +static void escc_hard_reset_chn(ESCCChannelState *s) +{ + int i; + + s->reg = 0; + for (i = 0; i < ESCC_SERIAL_REGS; i++) { + s->rregs[i] = 0; + s->wregs[i] = 0; + } + /* 1X divisor, 1 stop bit, no parity */ + s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; + s->wregs[W_MINTR] = MINTR_RST_ALL; + /* Synch mode tx clock = TRxC */ + s->wregs[W_CLOCK] = CLOCK_TRXC; + /* PLL disabled */ + s->wregs[W_MISC2] = MISC2_PLLDIS; + /* Enable most interrupts */ + s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | + EXTINT_TXUNDRN | EXTINT_BRKINT; + if (s->disabled) { + s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | + STATUS_CTS | STATUS_TXUNDRN; + } else { + s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN; + } + s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT; + + s->rx = s->tx = 0; + s->rxint = s->txint = 0; + s->rxint_under_svc = s->txint_under_svc = 0; + s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0; + clear_queue(s); +} + static void escc_reset(DeviceState *d) { ESCCState *s = ESCC(d); @@ -587,7 +621,8 @@ static void escc_mem_write(void *opaque, hwaddr addr, escc_soft_reset_chn(&serial->chn[1]); return; case MINTR_RST_ALL: - escc_reset(DEVICE(serial)); + escc_hard_reset_chn(&serial->chn[0]); + escc_hard_reset_chn(&serial->chn[1]); return; } break; -- 2.20.1