From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CEF8C433F5 for ; Mon, 6 Sep 2021 15:35:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BBF9260E52 for ; Mon, 6 Sep 2021 15:35:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BBF9260E52 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:35484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mNGeD-0003vJ-RO for qemu-devel@archiver.kernel.org; Mon, 06 Sep 2021 11:35:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNGdd-0003F8-9J for qemu-devel@nongnu.org; Mon, 06 Sep 2021 11:34:25 -0400 Received: from foss.arm.com ([217.140.110.172]:49406) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mNGda-0003oZ-LU for qemu-devel@nongnu.org; Mon, 06 Sep 2021 11:34:24 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7228D31B; Mon, 6 Sep 2021 08:34:19 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E03483F766; Mon, 6 Sep 2021 08:34:18 -0700 (PDT) Date: Mon, 6 Sep 2021 16:34:03 +0100 From: Andre Przywara To: Adam Lackorzynski Subject: Re: arm: Launching EFI-enabled arm32 Linux Message-ID: <20210906163403.7b091544@slackpad.fritz.box> In-Reply-To: References: Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=217.140.110.172; envelope-from=andre.przywara@arm.com; helo=foss.arm.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sat, 4 Sep 2021 21:26:45 +0200 Adam Lackorzynski wrote: Hi Adam, > while trying to launch an EFI-enabled arm32 Linux binary (zImage) I > noticed I get an undefined instruction exception on the first > instruction. Now this is a bit special because Linux uses a nop > instruction there that also is a PE file signature ('MZ') such that the > CPU runs over it and the file is still recognized as a PE binary. Linux > uses 0x13105a4d (tstne r0, #0x4d000) as the instruction (see also > arch/arm/boot/compressed/head.S and efi-header.S in Linux). > However, QEMU's instruction decoder will only recognize TST with bits > 12-15 being 0, which this instruction is not fullfilling, and thus the > undef exception. I guess other CPU implementations will allow this > encoding. So while investigating I was doing the following to make Linux > proceed. I also believe this was working in a previous version of QEMU. > > diff --git a/target/arm/a32.decode b/target/arm/a32.decode > index fcd8cd4f7d..222553750e 100644 > --- a/target/arm/a32.decode > +++ b/target/arm/a32.decode > @@ -127,7 +127,7 @@ ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot > ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot > SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot > RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot > -TST_xri .... 001 1000 1 .... 0000 ............ @S_xri_rot > +TST_xri .... 001 1000 1 .... ---- ............ @S_xri_rot > TEQ_xri .... 001 1001 1 .... 0000 ............ @S_xri_rot > CMP_xri .... 001 1010 1 .... 0000 ............ @S_xri_rot > CMN_xri .... 001 1011 1 .... 0000 ............ @S_xri_rot > > > Any thoughts on this? thanks for the report, I was looking at this and have a kernel patch to fix this properly as Peter suggested. And while I agree on the problem, I was struggling to reproduce this in reality: both with -kernel and when booting through U-Boot the "Z" bit is set, which lets QEMU not even bother about the rest of the encoding - the condition flags don't match, so it proceeds. If I change the __nop to use "tsteq", I see it hanging due to the missing exception handler, but not with "tstne". So can you say how you spotted this issue? This would be needed as a justification for patching the guts of the ARM Linux kernel port. Cheers, Andre