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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Lara Lazier <laramglazier@gmail.com>
Subject: [PULL v4 08/43] target/i386: Added vVMLOAD and vVMSAVE feature
Date: Wed,  8 Sep 2021 12:03:51 +0200	[thread overview]
Message-ID: <20210908100426.264356-9-pbonzini@redhat.com> (raw)
In-Reply-To: <20210908100426.264356-1-pbonzini@redhat.com>

From: Lara Lazier <laramglazier@gmail.com>

The feature allows the VMSAVE and VMLOAD instructions to execute in guest mode without
causing a VMEXIT. (APM2 15.33.1)

Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.h                    |  2 ++
 target/i386/svm.h                    |  2 ++
 target/i386/tcg/sysemu/excp_helper.c |  2 +-
 target/i386/tcg/sysemu/svm_helper.c  | 29 ++++++++++++++++++++++++++++
 4 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6b09b8b62f..71ae3141c3 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2261,6 +2261,8 @@ static inline bool ctl_has_irq(CPUX86State *env)
     return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
 }
 
+hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
+                        int *prot);
 #if defined(TARGET_X86_64) && \
     defined(CONFIG_USER_ONLY) && \
     defined(CONFIG_LINUX)
diff --git a/target/i386/svm.h b/target/i386/svm.h
index 036597a2ff..f9a785489d 100644
--- a/target/i386/svm.h
+++ b/target/i386/svm.h
@@ -24,6 +24,8 @@
 #define V_INTR_MASKING_SHIFT 24
 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
 
+#define V_VMLOAD_VMSAVE_ENABLED_MASK (1 << 1)
+
 #define SVM_INTERRUPT_SHADOW_MASK 1
 
 #define SVM_IOIO_STR_SHIFT 2
diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
index b6d940e04e..7af887be4d 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -358,7 +358,7 @@ do_check_protect_pse36:
     return error_code;
 }
 
-static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
+hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
                         int *prot)
 {
     CPUX86State *env = &X86_CPU(cs)->env;
diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c
index 7bbd3a18c9..6d39611eb6 100644
--- a/target/i386/tcg/sysemu/svm_helper.c
+++ b/target/i386/tcg/sysemu/svm_helper.c
@@ -120,6 +120,25 @@ static inline bool virtual_gif_enabled(CPUX86State *env)
     return false;
 }
 
+static inline bool virtual_vm_load_save_enabled(CPUX86State *env, uint32_t exit_code, uintptr_t retaddr)
+{
+    uint64_t lbr_ctl;
+
+    if (likely(env->hflags & HF_GUEST_MASK)) {
+        if (likely(!(env->hflags2 & HF2_NPT_MASK)) || !(env->efer & MSR_EFER_LMA)) {
+            cpu_vmexit(env, exit_code, 0, retaddr);
+        }
+
+        lbr_ctl = x86_ldl_phys(env_cpu(env), env->vm_vmcb + offsetof(struct vmcb,
+                                                  control.lbr_ctl));
+        return (env->features[FEAT_SVM] & CPUID_SVM_V_VMSAVE_VMLOAD)
+                && (lbr_ctl & V_VMLOAD_VMSAVE_ENABLED_MASK);
+
+    }
+
+    return false;
+}
+
 static inline bool virtual_gif_set(CPUX86State *env)
 {
     return !virtual_gif_enabled(env) || (env->int_ctl & V_GIF_MASK);
@@ -431,6 +450,7 @@ void helper_vmload(CPUX86State *env, int aflag)
 {
     CPUState *cs = env_cpu(env);
     target_ulong addr;
+    int prot;
 
     cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC());
 
@@ -440,6 +460,10 @@ void helper_vmload(CPUX86State *env, int aflag)
         addr = (uint32_t)env->regs[R_EAX];
     }
 
+    if (virtual_vm_load_save_enabled(env, SVM_EXIT_VMLOAD, GETPC())) {
+        addr = get_hphys(cs, addr, MMU_DATA_LOAD, &prot);
+    }
+
     qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx
                   "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
                   addr, x86_ldq_phys(cs, addr + offsetof(struct vmcb,
@@ -473,6 +497,7 @@ void helper_vmsave(CPUX86State *env, int aflag)
 {
     CPUState *cs = env_cpu(env);
     target_ulong addr;
+    int prot;
 
     cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC());
 
@@ -482,6 +507,10 @@ void helper_vmsave(CPUX86State *env, int aflag)
         addr = (uint32_t)env->regs[R_EAX];
     }
 
+    if (virtual_vm_load_save_enabled(env, SVM_EXIT_VMSAVE, GETPC())) {
+        addr = get_hphys(cs, addr, MMU_DATA_STORE, &prot);
+    }
+
     qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx
                   "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
                   addr, x86_ldq_phys(cs,
-- 
2.31.1




  parent reply	other threads:[~2021-09-08 10:09 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-08 10:03 [PULL v4 00/43] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 01/43] target/i386: add missing bits to CR4_RESERVED_MASK Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 02/43] target/i386: VMRUN and VMLOAD canonicalizations Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 03/43] target/i386: Added VGIF feature Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 04/43] target/i386: Moved int_ctl into CPUX86State structure Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 05/43] target/i386: Added VGIF V_IRQ masking capability Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 06/43] target/i386: Added ignore TPR check in ctl_has_irq Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 07/43] target/i386: Added changed priority check for VIRQ Paolo Bonzini
2021-09-08 10:03 ` Paolo Bonzini [this message]
2021-09-08 10:03 ` [PULL v4 09/43] memory: Add RAM_PROTECTED flag to skip IOMMU mappings Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 10/43] hostmem: Add hostmem-epc as a backend for SGX EPC Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 11/43] qom: Add memory-backend-epc ObjectOptions support Paolo Bonzini
2021-09-08 14:51   ` Eric Blake
2021-09-08 10:03 ` [PULL v4 12/43] i386: Add 'sgx-epc' device to expose EPC sections to guest Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 13/43] vl: Add sgx compound properties to expose SGX " Paolo Bonzini
2021-09-08 14:52   ` Eric Blake
2021-09-09  3:01     ` Yang Zhong
2021-09-08 10:03 ` [PULL v4 14/43] i386: Add primary SGX CPUID and MSR defines Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 15/43] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 16/43] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 17/43] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 18/43] i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 19/43] fw_cfg: add etc/msr_feature_control Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 20/43] i386: Add feature control MSR dependency when SGX is enabled Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 21/43] i386: Update SGX CPUID info according to hardware/KVM/user input Paolo Bonzini
2021-09-09 13:09   ` Philippe Mathieu-Daudé
2021-09-08 10:04 ` [PULL v4 22/43] i386: kvm: Add support for exposing PROVISIONKEY to guest Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 23/43] i386: Propagate SGX CPUID sub-leafs to KVM Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 24/43] Adjust min CPUID level to 0x12 when SGX is enabled Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 25/43] hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 26/43] hw/i386/pc: Account for SGX EPC sections when calculating device memory Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 27/43] i386/pc: Add e820 entry for SGX EPC section(s) Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 28/43] i386: acpi: Add SGX EPC entry to ACPI tables Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 29/43] q35: Add support for SGX EPC Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 30/43] i440fx: " Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 31/43] hostmem-epc: Add the reset interface for EPC backend reset Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 32/43] sgx-epc: Add the reset interface for sgx-epc virt device Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 33/43] sgx-epc: Avoid bios reset during sgx epc initialization Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 34/43] hostmem-epc: Make prealloc consistent with qemu cmdline during reset Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 35/43] Kconfig: Add CONFIG_SGX support Paolo Bonzini
2021-09-09 13:16   ` Philippe Mathieu-Daudé
2021-09-09 13:33     ` Philippe Mathieu-Daudé
2021-09-08 10:04 ` [PULL v4 36/43] sgx-epc: Add the fill_device_info() callback support Paolo Bonzini
2021-09-08 14:54   ` Eric Blake
2021-09-08 10:04 ` [PULL v4 37/43] docs: standardize book titles to === with overline Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 38/43] docs: standardize directory index to --- " Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 39/43] docs/system: standardize man page sections " Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 40/43] docs/system: move x86 CPU configuration to a separate document Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 41/43] docs/system: Add SGX documentation to the system manual Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 42/43] meson.build: Do not look for VNC-related libraries if have_system is not set Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 43/43] ebpf: only include in system emulators Paolo Bonzini
2021-09-09 13:25 ` [PULL v4 00/43] (Mostly) x86 changes for 2021-09-06 Peter Maydell
2021-09-09 13:32   ` Philippe Mathieu-Daudé
2021-09-11 12:59 ` Peter Maydell
2021-09-11 13:05   ` Paolo Bonzini

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