From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Subject: [PULL 11/12] escc: re-use escc_reset_chn() for soft reset
Date: Wed, 8 Sep 2021 12:54:50 +0100 [thread overview]
Message-ID: <20210908115451.9821-12-mark.cave-ayland@ilande.co.uk> (raw)
In-Reply-To: <20210908115451.9821-1-mark.cave-ayland@ilande.co.uk>
This removes duplication of the internal device state initialisation between
device reset and soft reset.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-9-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/char/escc.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 22c97414a1..9283ed70a6 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -288,7 +288,8 @@ static void escc_reset_chn(ESCCChannelState *s)
static void escc_soft_reset_chn(ESCCChannelState *s)
{
- s->reg = 0;
+ escc_reset_chn(s);
+
s->wregs[W_CMD] = 0;
s->wregs[W_INTR] &= INTR_PAR_SPEC | INTR_WTRQ_TXRX;
s->wregs[W_RXCTRL] &= ~RXCTRL_RXEN;
@@ -314,12 +315,6 @@ static void escc_soft_reset_chn(ESCCChannelState *s)
s->rregs[R_SPEC] |= SPEC_BITS8;
s->rregs[R_INTR] = 0;
s->rregs[R_MISC] &= MISC_2CLKMISS;
-
- s->rx = s->tx = 0;
- s->rxint = s->txint = 0;
- s->rxint_under_svc = s->txint_under_svc = 0;
- s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
- clear_queue(s);
}
static void escc_hard_reset_chn(ESCCChannelState *s)
--
2.20.1
next prev parent reply other threads:[~2021-09-08 12:03 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-08 11:54 [PULL 00/12] qemu-sparc queue 20210908 Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 01/12] target/sparc: Drop use of gen_io_end() Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 02/12] tcg: Drop gen_io_end() Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 03/12] sun4m: fix setting CPU id when more than one CPU is present Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 04/12] escc: checkpatch fixes Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 05/12] escc: reset register values to zero in escc_reset() Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 06/12] escc: introduce escc_soft_reset_chn() for software reset Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 07/12] escc: introduce escc_hard_reset_chn() for hardware reset Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 08/12] escc: implement soft reset as described in the datasheet Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 09/12] escc: implement hard " Mark Cave-Ayland
2021-09-08 11:54 ` [PULL 10/12] escc: remove register changes from escc_reset_chn() Mark Cave-Ayland
2021-09-08 11:54 ` Mark Cave-Ayland [this message]
2021-09-08 11:54 ` [PULL 12/12] escc: fix STATUS_SYNC bit in R_STATUS register Mark Cave-Ayland
2021-09-10 10:08 ` [PULL 00/12] qemu-sparc queue 20210908 Peter Maydell
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