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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id d9sm6278043wrb.36.2021.09.12.10.28.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 10:28:50 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v4 16/30] target/microblaze: Restrict has_work() handler to sysemu Date: Sun, 12 Sep 2021 19:27:17 +0200 Message-Id: <20210912172731.789788-17-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210912172731.789788-1-f4bug@amsat.org> References: <20210912172731.789788-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Restrict has_work() to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 15db277925f..36e6e540483 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -92,12 +92,13 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; } +#ifndef CONFIG_USER_ONLY + static bool mb_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } -#ifndef CONFIG_USER_ONLY static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) { MicroBlazeCPU *cpu = opaque; @@ -142,7 +143,7 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level) cpu_reset_interrupt(cs, type); } } -#endif +#endif /* !CONFIG_USER_ONLY */ static void mb_cpu_reset(DeviceState *dev) { @@ -368,6 +369,7 @@ static const struct TCGCPUOps mb_tcg_ops = { .tlb_fill = mb_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = mb_cpu_has_work, .cpu_exec_interrupt = mb_cpu_exec_interrupt, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, @@ -386,8 +388,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); cc->class_by_name = mb_cpu_class_by_name; - cc->has_work = mb_cpu_has_work; - cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; cc->gdb_read_register = mb_cpu_gdb_read_register; -- 2.31.1