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From: WANG Xuerui <git@xen0n.name>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"XiaoJuan Yang" <yangxiaojuan@loongson.cn>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Song Gao" <gaosong@loongson.cn>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"WANG Xuerui" <git@xen0n.name>,
	"Laurent Vivier" <laurent@vivier.eu>
Subject: [PATCH v6 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops
Date: Sun, 26 Sep 2021 01:30:18 +0800	[thread overview]
Message-ID: <20210925173032.2434906-17-git@xen0n.name> (raw)
In-Reply-To: <20210925173032.2434906-1-git@xen0n.name>

Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tcg/loongarch64/tcg-target-con-set.h |  1 +
 tcg/loongarch64/tcg-target.c.inc     | 91 ++++++++++++++++++++++++++++
 tcg/loongarch64/tcg-target.h         |  4 +-
 3 files changed, 94 insertions(+), 2 deletions(-)

diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 2975e03127..42f8e28741 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -17,6 +17,7 @@
 C_O0_I1(r)
 C_O1_I1(r, r)
 C_O1_I2(r, r, rC)
+C_O1_I2(r, r, ri)
 C_O1_I2(r, r, rU)
 C_O1_I2(r, r, rW)
 C_O1_I2(r, 0, rZ)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 4c1c1d6182..d0a24cc009 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -608,6 +608,85 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false);
         break;
 
+    case INDEX_op_shl_i32:
+        if (c2) {
+            tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f);
+        } else {
+            tcg_out_opc_sll_w(s, a0, a1, a2);
+        }
+        break;
+    case INDEX_op_shl_i64:
+        if (c2) {
+            tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f);
+        } else {
+            tcg_out_opc_sll_d(s, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_shr_i32:
+        if (c2) {
+            tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f);
+        } else {
+            tcg_out_opc_srl_w(s, a0, a1, a2);
+        }
+        break;
+    case INDEX_op_shr_i64:
+        if (c2) {
+            tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f);
+        } else {
+            tcg_out_opc_srl_d(s, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_sar_i32:
+        if (c2) {
+            tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f);
+        } else {
+            tcg_out_opc_sra_w(s, a0, a1, a2);
+        }
+        break;
+    case INDEX_op_sar_i64:
+        if (c2) {
+            tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f);
+        } else {
+            tcg_out_opc_sra_d(s, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_rotl_i32:
+        /* transform into equivalent rotr/rotri */
+        if (c2) {
+            tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f);
+        } else {
+            tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
+            tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0);
+        }
+        break;
+    case INDEX_op_rotl_i64:
+        /* transform into equivalent rotr/rotri */
+        if (c2) {
+            tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f);
+        } else {
+            tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
+            tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0);
+        }
+        break;
+
+    case INDEX_op_rotr_i32:
+        if (c2) {
+            tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f);
+        } else {
+            tcg_out_opc_rotr_w(s, a0, a1, a2);
+        }
+        break;
+    case INDEX_op_rotr_i64:
+        if (c2) {
+            tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f);
+        } else {
+            tcg_out_opc_rotr_d(s, a0, a1, a2);
+        }
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     default:
@@ -657,6 +736,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
          */
         return C_O1_I2(r, r, rC);
 
+    case INDEX_op_shl_i32:
+    case INDEX_op_shl_i64:
+    case INDEX_op_shr_i32:
+    case INDEX_op_shr_i64:
+    case INDEX_op_sar_i32:
+    case INDEX_op_sar_i64:
+    case INDEX_op_rotl_i32:
+    case INDEX_op_rotl_i64:
+    case INDEX_op_rotr_i32:
+    case INDEX_op_rotr_i64:
+        return C_O1_I2(r, r, ri);
+
     case INDEX_op_and_i32:
     case INDEX_op_and_i64:
     case INDEX_op_nor_i32:
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index ef489cbc86..e59c2a7bec 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -96,7 +96,7 @@ typedef enum {
 #define TCG_TARGET_HAS_div_i32          0
 #define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_div2_i32         0
-#define TCG_TARGET_HAS_rot_i32          0
+#define TCG_TARGET_HAS_rot_i32          1
 #define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_extract_i32      1
 #define TCG_TARGET_HAS_sextract_i32     0
@@ -133,7 +133,7 @@ typedef enum {
 #define TCG_TARGET_HAS_div_i64          0
 #define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_div2_i64         0
-#define TCG_TARGET_HAS_rot_i64          0
+#define TCG_TARGET_HAS_rot_i64          1
 #define TCG_TARGET_HAS_deposit_i64      1
 #define TCG_TARGET_HAS_extract_i64      1
 #define TCG_TARGET_HAS_sextract_i64     0
-- 
2.33.0



  parent reply	other threads:[~2021-09-25 17:50 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-25 17:30 [PATCH v6 00/30] LoongArch64 port of QEMU TCG WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 03/30] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 06/30] tcg/loongarch64: Define the operand constraints WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 07/30] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 08/30] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-26  6:48   ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 10/30] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-09-29 17:13   ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 11/30] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 13/30] tcg/loongarch64: Implement deposit/extract ops WANG Xuerui
2021-09-29 17:14   ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops WANG Xuerui
2021-09-26  6:50   ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 15/30] tcg/loongarch64: Implement clz/ctz ops WANG Xuerui
2021-09-25 17:30 ` WANG Xuerui [this message]
2021-09-25 17:30 ` [PATCH v6 17/30] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 19/30] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 20/30] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 21/30] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 22/30] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 25/30] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 26/30] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-09-26  7:15   ` Philippe Mathieu-Daudé
2021-09-26 23:07     ` Richard Henderson
2021-09-29 17:00       ` WANG Xuerui
2021-09-29 17:11       ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 27/30] tcg/loongarch64: Register the JIT WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 28/30] linux-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler " WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 30/30] configure, meson.build: Mark support " WANG Xuerui
2021-09-26  7:17   ` Philippe Mathieu-Daudé

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