From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Taylor Simpson <tsimpson@quicinc.com>,
alex.bennee@linaro.org, laurent@vivier.eu
Subject: [PATCH v3 25/41] target/hexagon: Remove hexagon_cpu_tlb_fill
Date: Fri, 1 Oct 2021 13:11:35 -0400 [thread overview]
Message-ID: <20211001171151.1739472-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org>
The fallback code in raise_sigsegv is sufficient for hexagon.
Remove the code from cpu_loop that raises SIGSEGV.
Cc: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/hexagon/cpu_loop.c | 24 +-----------------------
target/hexagon/cpu.c | 23 -----------------------
2 files changed, 1 insertion(+), 46 deletions(-)
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index bee2a9e4ea..6b24cbaba9 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -28,8 +28,7 @@
void cpu_loop(CPUHexagonState *env)
{
CPUState *cs = env_cpu(env);
- int trapnr, signum, sigcode;
- target_ulong sigaddr;
+ int trapnr;
target_ulong syscallnum;
target_ulong ret;
@@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env)
cpu_exec_end(cs);
process_queued_cpu_work(cs);
- signum = 0;
- sigcode = 0;
- sigaddr = 0;
-
switch (trapnr) {
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
@@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env)
env->gpr[0] = ret;
}
break;
- case HEX_EXCP_FETCH_NO_UPAGE:
- case HEX_EXCP_PRIV_NO_UREAD:
- case HEX_EXCP_PRIV_NO_UWRITE:
- signum = TARGET_SIGSEGV;
- sigcode = TARGET_SEGV_MAPERR;
- break;
case EXCP_ATOMIC:
cpu_exec_step_atomic(cs);
break;
@@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env)
trapnr);
exit(EXIT_FAILURE);
}
-
- if (signum) {
- target_siginfo_t info = {
- .si_signo = signum,
- .si_errno = 0,
- .si_code = sigcode,
- ._sifields._sigfault._addr = sigaddr
- };
- queue_signal(env, info.si_signo, QEMU_SI_KILL, &info);
- }
-
process_pending_signals(env);
}
}
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 3338365c16..160a46a3d5 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj)
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
}
-static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
-#ifdef CONFIG_USER_ONLY
- switch (access_type) {
- case MMU_INST_FETCH:
- cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE;
- break;
- case MMU_DATA_LOAD:
- cs->exception_index = HEX_EXCP_PRIV_NO_UREAD;
- break;
- case MMU_DATA_STORE:
- cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE;
- break;
- }
- cpu_loop_exit_restore(cs, retaddr);
-#else
-#error System mode not implemented for Hexagon
-#endif
-}
-
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
- .tlb_fill = hexagon_tlb_fill,
};
static void hexagon_cpu_class_init(ObjectClass *c, void *data)
--
2.25.1
next prev parent reply other threads:[~2021-10-01 17:22 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-01 17:11 [PATCH v3 00/41] linux-user: Streamline handling of SIGSEGV Richard Henderson
2021-10-01 17:11 ` [PATCH v3 01/41] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-10-01 17:11 ` [PATCH v3 02/41] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-10-01 17:11 ` [PATCH v3 03/41] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-10-01 17:11 ` [PATCH v3 04/41] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-10-01 17:11 ` [PATCH v3 05/41] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-10-01 17:11 ` [PATCH v3 06/41] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-10-01 17:11 ` [PATCH v3 07/41] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-10-01 17:11 ` [PATCH v3 08/41] linux-user/host/ppc: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 09/41] linux-user/host/alpha: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 10/41] linux-user/host/sparc: " Richard Henderson
2021-10-02 14:14 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 11/41] linux-user/host/arm: " Richard Henderson
2021-10-02 14:15 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 12/41] linux-user/host/aarch64: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 13/41] linux-user/host/s390: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 14/41] linux-user/host/mips: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 15/41] linux-user/host/riscv: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 16/41] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-10-01 17:11 ` [PATCH v3 17/41] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-10-01 17:11 ` [PATCH v3 18/41] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-10-01 17:11 ` [PATCH v3 19/41] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 20/41] linux-user: Add cpu_loop_exit_segv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 21/41] target/alpha: Make alpha_cpu_tlb_fill sysemu only Richard Henderson
2021-10-02 14:18 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 22/41] target/arm: Use cpu_loop_exit_segv for mte tag lookup Richard Henderson
2021-10-02 14:20 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 23/41] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 24/41] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-10-01 17:11 ` Richard Henderson [this message]
2021-10-01 22:38 ` [PATCH v3 25/41] target/hexagon: Remove hexagon_cpu_tlb_fill Taylor Simpson
2021-10-01 17:11 ` [PATCH v3 26/41] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-10-01 17:11 ` [PATCH v3 27/41] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 28/41] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-10-02 14:21 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 29/41] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 30/41] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-10-02 14:23 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 31/41] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
2021-10-02 14:24 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-10-01 17:11 ` [PATCH v3 33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-10-02 14:26 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 34/41] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-10-02 14:27 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 36/41] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-10-01 17:11 ` [PATCH v3 37/41] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 38/41] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-10-01 17:11 ` [PATCH v3 39/41] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
2021-10-02 14:28 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 40/41] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
2021-10-01 20:58 ` Max Filippov
2021-10-02 14:29 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 41/41] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-10-02 14:30 ` Philippe Mathieu-Daudé
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