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Tsirkin" To: Lukasz Maniak Subject: Re: [PATCH 01/15] pcie: Set default and supported MaxReadReq to 512 Message-ID: <20211007181056-mutt-send-email-mst@kernel.org> References: <20211007162406.1920374-1-lukasz.maniak@linux.intel.com> <20211007162406.1920374-2-lukasz.maniak@linux.intel.com> MIME-Version: 1.0 In-Reply-To: <20211007162406.1920374-2-lukasz.maniak@linux.intel.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.05, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-block@nongnu.org, =?utf-8?Q?=C5=81ukasz?= Gieryk , Knut Omang , qemu-devel@nongnu.org, Knut Omang Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Oct 07, 2021 at 06:23:52PM +0200, Lukasz Maniak wrote: > From: Knut Omang > > Make the default PCI Express Capability for PCIe devices set > MaxReadReq to 512. code says 256 > Tyipcal modern devices people would want to typo > emulate or simulate would want this. The previous value would > cause warnings from the root port driver on some kernels. which specifically? > > Signed-off-by: Knut Omang we can't make changes like this unconditionally, this will break migration across versions. Pls tie this to a machine version. Thanks! > --- > hw/pci/pcie.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > index 6e95d82903..c1a12f3744 100644 > --- a/hw/pci/pcie.c > +++ b/hw/pci/pcie.c > @@ -62,8 +62,9 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) > * Functions conforming to the ECN, PCI Express Base > * Specification, Revision 1.1., or subsequent PCI Express Base > * Specification revisions. > + * + set max payload size to 256, which seems to be a common value > */ > - pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); > + pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER | (0x1 & PCI_EXP_DEVCAP_PAYLOAD)); > > pci_set_long(exp_cap + PCI_EXP_LNKCAP, > (port << PCI_EXP_LNKCAP_PN_SHIFT) | > @@ -179,6 +180,8 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, > pci_set_long(exp_cap + PCI_EXP_DEVCAP2, > PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); > > + pci_set_word(exp_cap + PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_READRQ_256B); > + > pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); > > if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { > -- > 2.25.1