qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Lukasz Maniak <lukasz.maniak@linux.intel.com>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: "Łukasz Gieryk" <lukasz.gieryk@linux.intel.com>,
	"Knut Omang" <knuto@ifi.uio.no>,
	qemu-devel@nongnu.org, qemu-block@nongnu.org
Subject: Re: [PATCH 04/15] pcie: Add callback preceding SR-IOV VFs update
Date: Tue, 12 Oct 2021 18:06:46 +0200	[thread overview]
Message-ID: <20211012160646.GA2286339@lmaniak-dev.igk.intel.com> (raw)
In-Reply-To: <20211012032026-mutt-send-email-mst@kernel.org>

On Tue, Oct 12, 2021 at 03:25:12AM -0400, Michael S. Tsirkin wrote:
> On Thu, Oct 07, 2021 at 06:23:55PM +0200, Lukasz Maniak wrote:
> > PCIe devices implementing SR-IOV may need to perform certain actions
> > before the VFs are unrealized or vice versa.
> > 
> > Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com>
> 
> Callbacks are annoying and easy to misuse though.
> VFs are enabled through a config cycle, we generally just
> have devices invoke the capability handler.
> E.g.
> 
> static void pci_bridge_dev_write_config(PCIDevice *d,
>                                         uint32_t address, uint32_t val, int len)
> {
>     pci_bridge_write_config(d, address, val, len);
>     if (msi_present(d)) {
>         msi_write_config(d, address, val, len);
>     }
> }
> 
> this makes it easy to do whatever you want before/after
> the write. You can also add a helper to check
> that SRIOV is being enabled/disabled if necessary.
> 
> > ---
> >  docs/pcie_sriov.txt         |  2 +-
> >  hw/pci/pcie_sriov.c         | 14 +++++++++++++-
> >  include/hw/pci/pcie_sriov.h |  8 +++++++-
> >  3 files changed, 21 insertions(+), 3 deletions(-)
> > 
> > diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt
> > index f5e891e1d4..63ca1a7b8e 100644
> > --- a/docs/pcie_sriov.txt
> > +++ b/docs/pcie_sriov.txt
> > @@ -57,7 +57,7 @@ setting up a BAR for a VF.
> >        /* Add and initialize the SR/IOV capability */
> >        pcie_sriov_pf_init(d, 0x200, "your_virtual_dev",
> >                         vf_devid, initial_vfs, total_vfs,
> > -                       fun_offset, stride);
> > +                       fun_offset, stride, pre_vfs_update_cb);
> >  
> >        /* Set up individual VF BARs (parameters as for normal BARs) */
> >        pcie_sriov_pf_init_vf_bar( ... )
> > diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c
> > index 501a1ff433..cac2aee061 100644
> > --- a/hw/pci/pcie_sriov.c
> > +++ b/hw/pci/pcie_sriov.c
> > @@ -30,7 +30,8 @@ static void unregister_vfs(PCIDevice *dev);
> >  void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
> >                          const char *vfname, uint16_t vf_dev_id,
> >                          uint16_t init_vfs, uint16_t total_vfs,
> > -                        uint16_t vf_offset, uint16_t vf_stride)
> > +                        uint16_t vf_offset, uint16_t vf_stride,
> > +                        SriovVfsUpdate pre_vfs_update)
> >  {
> >      uint8_t *cfg = dev->config + offset;
> >      uint8_t *wmask;
> > @@ -41,6 +42,7 @@ void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
> >      dev->exp.sriov_pf.num_vfs = 0;
> >      dev->exp.sriov_pf.vfname = g_strdup(vfname);
> >      dev->exp.sriov_pf.vf = NULL;
> > +    dev->exp.sriov_pf.pre_vfs_update = pre_vfs_update;
> >  
> >      pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset);
> >      pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride);
> > @@ -180,6 +182,11 @@ static void register_vfs(PCIDevice *dev)
> >      assert(dev->exp.sriov_pf.vf);
> >  
> >      trace_sriov_register_vfs(SRIOV_ID(dev), num_vfs);
> > +
> > +    if (dev->exp.sriov_pf.pre_vfs_update) {
> > +        dev->exp.sriov_pf.pre_vfs_update(dev, dev->exp.sriov_pf.num_vfs, num_vfs);
> > +    }
> > +
> >      for (i = 0; i < num_vfs; i++) {
> >          dev->exp.sriov_pf.vf[i] = register_vf(dev, devfn, dev->exp.sriov_pf.vfname, i);
> >          if (!dev->exp.sriov_pf.vf[i]) {
> > @@ -198,6 +205,11 @@ static void unregister_vfs(PCIDevice *dev)
> >      uint16_t i;
> >  
> >      trace_sriov_unregister_vfs(SRIOV_ID(dev), num_vfs);
> > +
> > +    if (dev->exp.sriov_pf.pre_vfs_update) {
> > +        dev->exp.sriov_pf.pre_vfs_update(dev, dev->exp.sriov_pf.num_vfs, 0);
> > +    }
> > +
> >      for (i = 0; i < num_vfs; i++) {
> >          PCIDevice *vf = dev->exp.sriov_pf.vf[i];
> >          object_property_set_bool(OBJECT(vf), "realized", false, &local_err);
> > diff --git a/include/hw/pci/pcie_sriov.h b/include/hw/pci/pcie_sriov.h
> > index 0974f00054..9ab48b79c0 100644
> > --- a/include/hw/pci/pcie_sriov.h
> > +++ b/include/hw/pci/pcie_sriov.h
> > @@ -13,11 +13,16 @@
> >  #ifndef QEMU_PCIE_SRIOV_H
> >  #define QEMU_PCIE_SRIOV_H
> >  
> > +typedef void (*SriovVfsUpdate)(PCIDevice *dev, uint16_t prev_num_vfs,
> > +                               uint16_t num_vfs);
> > +
> >  struct PCIESriovPF {
> >      uint16_t num_vfs;           /* Number of virtual functions created */
> >      uint8_t vf_bar_type[PCI_NUM_REGIONS];  /* Store type for each VF bar */
> >      const char *vfname;         /* Reference to the device type used for the VFs */
> >      PCIDevice **vf;             /* Pointer to an array of num_vfs VF devices */
> > +
> > +    SriovVfsUpdate pre_vfs_update;  /* Callback preceding VFs count change */
> >  };
> >  
> >  struct PCIESriovVF {
> > @@ -28,7 +33,8 @@ struct PCIESriovVF {
> >  void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
> >                          const char *vfname, uint16_t vf_dev_id,
> >                          uint16_t init_vfs, uint16_t total_vfs,
> > -                        uint16_t vf_offset, uint16_t vf_stride);
> > +                        uint16_t vf_offset, uint16_t vf_stride,
> > +                        SriovVfsUpdate pre_vfs_update);
> >  void pcie_sriov_pf_exit(PCIDevice *dev);
> >  
> >  /* Set up a VF bar in the SR/IOV bar area */
> > -- 
> > 2.25.1
>

Hi Michael,

A custom config_write callback was the first approach we used.
However, once implemented, we realized it looks the same as the
pcie_sriov_config_write function. To avoid code duplication and
interfering with the internal SR-IOV structures for purposes of NVMe,
we opted for this callback prior to the VFs update.
After all, we have callbacks in both approaches, config_write and the
added pre_vfs_update, so both are prone to misuse.

But I agree it may not be a good moment yet to add a new API
specifically for SR-IOV functionality, as NVMe will be the first device
to use it.

CCing Knut, perhaps as the author of SR-IOV you have some thoughts on
how the device notification of an upcoming VFs update would be handled.

Thanks,
Lukasz


  reply	other threads:[~2021-10-12 16:17 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-07 16:23 [PATCH 00/15] hw/nvme: SR-IOV with Virtualization Enhancements Lukasz Maniak
2021-10-07 16:23 ` [PATCH 01/15] pcie: Set default and supported MaxReadReq to 512 Lukasz Maniak
2021-10-07 22:12   ` Michael S. Tsirkin
2021-10-26 14:36     ` Lukasz Maniak
2021-10-26 15:37       ` Knut Omang
2021-10-07 16:23 ` [PATCH 02/15] pcie: Add support for Single Root I/O Virtualization (SR/IOV) Lukasz Maniak
2021-10-07 16:23 ` [PATCH 03/15] pcie: Add some SR/IOV API documentation in docs/pcie_sriov.txt Lukasz Maniak
2021-10-07 16:23 ` [PATCH 04/15] pcie: Add callback preceding SR-IOV VFs update Lukasz Maniak
2021-10-12  7:25   ` Michael S. Tsirkin
2021-10-12 16:06     ` Lukasz Maniak [this message]
2021-10-13  9:10       ` Michael S. Tsirkin
2021-10-15 16:24         ` Lukasz Maniak
2021-10-15 17:30           ` Michael S. Tsirkin
2021-10-20 13:30             ` Lukasz Maniak
2021-10-07 16:23 ` [PATCH 05/15] hw/nvme: Add support for SR-IOV Lukasz Maniak
2021-10-20 19:07   ` Klaus Jensen
2021-10-21 14:33     ` Lukasz Maniak
2021-11-02 14:33   ` Klaus Jensen
2021-11-02 17:33     ` Lukasz Maniak
2021-11-04 14:30       ` Lukasz Maniak
2021-11-08  7:56         ` Klaus Jensen
2021-11-10 13:42           ` Lukasz Maniak
2021-11-10 16:39             ` Klaus Jensen
2021-10-07 16:23 ` [PATCH 06/15] hw/nvme: Add support for Primary Controller Capabilities Lukasz Maniak
2021-11-02 14:34   ` Klaus Jensen
2021-10-07 16:23 ` [PATCH 07/15] hw/nvme: Add support for Secondary Controller List Lukasz Maniak
2021-11-02 14:35   ` Klaus Jensen
2021-10-07 16:23 ` [PATCH 08/15] pcie: Add 1.2 version token for the Power Management Capability Lukasz Maniak
2021-10-07 16:24 ` [PATCH 09/15] hw/nvme: Implement the Function Level Reset Lukasz Maniak
2021-11-02 14:35   ` Klaus Jensen
2021-10-07 16:24 ` [PATCH 10/15] hw/nvme: Make max_ioqpairs and msix_qsize configurable in runtime Lukasz Maniak
2021-10-18 10:06   ` Philippe Mathieu-Daudé
2021-10-18 15:53     ` Łukasz Gieryk
2021-10-20 19:06   ` Klaus Jensen
2021-10-21 13:40     ` Łukasz Gieryk
2021-11-03 12:11       ` Klaus Jensen
2021-10-20 19:26   ` Klaus Jensen
2021-10-07 16:24 ` [PATCH 11/15] hw/nvme: Calculate BAR atributes in a function Lukasz Maniak
2021-10-18  9:52   ` Philippe Mathieu-Daudé
2021-10-07 16:24 ` [PATCH 12/15] hw/nvme: Initialize capability structures for primary/secondary controllers Lukasz Maniak
2021-11-03 12:07   ` Klaus Jensen
2021-11-04 15:48     ` Łukasz Gieryk
2021-11-05  8:46       ` Łukasz Gieryk
2021-11-05 14:04         ` Łukasz Gieryk
2021-11-08  8:25           ` Klaus Jensen
2021-11-08 13:57             ` Łukasz Gieryk
2021-11-09 12:22               ` Klaus Jensen
2021-10-07 16:24 ` [PATCH 13/15] pcie: Add helpers to the SR/IOV API Lukasz Maniak
2021-10-26 16:57   ` Knut Omang
2021-10-07 16:24 ` [PATCH 14/15] hw/nvme: Add support for the Virtualization Management command Lukasz Maniak
2021-10-07 16:24 ` [PATCH 15/15] docs: Add documentation for SR-IOV and Virtualization Enhancements Lukasz Maniak
2021-10-08  6:31 ` [PATCH 00/15] hw/nvme: SR-IOV with " Klaus Jensen
2021-10-26 18:20 ` Klaus Jensen
2021-10-27 16:49   ` Lukasz Maniak
2021-11-02  7:24     ` Klaus Jensen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211012160646.GA2286339@lmaniak-dev.igk.intel.com \
    --to=lukasz.maniak@linux.intel.com \
    --cc=knuto@ifi.uio.no \
    --cc=lukasz.gieryk@linux.intel.com \
    --cc=mst@redhat.com \
    --cc=qemu-block@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).