* [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length
@ 2021-10-13 20:50 Richard Henderson
2021-10-13 20:50 ` [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
` (12 more replies)
0 siblings, 13 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
This is a partial patch set attempting to set things in the
right direction for both the UXL and RV128 patch sets.
Changes for v2:
* Set mxl/sxl/uxl at reset.
* Set sxl/uxl in write_mstatus.
r~
Richard Henderson (13):
target/riscv: Move cpu_get_tb_cpu_state out of line
target/riscv: Create RISCVMXL enumeration
target/riscv: Split misa.mxl and misa.ext
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
target/riscv: Add MXL/SXL/UXL to TB_FLAGS
target/riscv: Use REQUIRE_64BIT in amo_check64
target/riscv: Properly check SEW in amo_op
target/riscv: Replace is_32bit with get_xl/get_xlen
target/riscv: Replace DisasContext.w with DisasContext.ol
target/riscv: Use gen_arith_per_ol for RVM
target/riscv: Adjust trans_rev8_32 for riscv64
target/riscv: Use gen_unary_per_ol for RVB
target/riscv: Use gen_shift*_per_ol for RVB, RVI
target/riscv/cpu.h | 73 +++-------
target/riscv/cpu_bits.h | 8 +-
hw/riscv/boot.c | 2 +-
linux-user/elfload.c | 2 +-
linux-user/riscv/cpu_loop.c | 2 +-
semihosting/arm-compat-semi.c | 2 +-
target/riscv/cpu.c | 108 +++++++++------
target/riscv/cpu_helper.c | 91 ++++++++++++-
target/riscv/csr.c | 71 ++++++----
target/riscv/gdbstub.c | 10 +-
target/riscv/machine.c | 10 +-
target/riscv/monitor.c | 4 +-
target/riscv/translate.c | 170 ++++++++++++++++++------
target/riscv/insn_trans/trans_rvb.c.inc | 140 ++++++++++---------
target/riscv/insn_trans/trans_rvi.c.inc | 44 +++---
target/riscv/insn_trans/trans_rvm.c.inc | 36 +++--
target/riscv/insn_trans/trans_rvv.c.inc | 29 ++--
17 files changed, 510 insertions(+), 292 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
@ 2021-10-13 20:50 ` Richard Henderson
2021-10-13 20:50 ` [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
` (11 subsequent siblings)
12 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
Move the function to cpu_helper.c, as it is large and growing.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 47 ++-------------------------------------
target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 45 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9e55b2f5b1..7084efc452 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -413,51 +413,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
return cpu->cfg.vlen >> (sew + 3 - lmul);
}
-static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
- target_ulong *cs_base, uint32_t *pflags)
-{
- uint32_t flags = 0;
-
- *pc = env->pc;
- *cs_base = 0;
-
- if (riscv_has_ext(env, RVV)) {
- uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
- bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
- flags = FIELD_DP32(flags, TB_FLAGS, VILL,
- FIELD_EX64(env->vtype, VTYPE, VILL));
- flags = FIELD_DP32(flags, TB_FLAGS, SEW,
- FIELD_EX64(env->vtype, VTYPE, VSEW));
- flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
- FIELD_EX64(env->vtype, VTYPE, VLMUL));
- flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
- } else {
- flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
- }
-
-#ifdef CONFIG_USER_ONLY
- flags |= TB_FLAGS_MSTATUS_FS;
-#else
- flags |= cpu_mmu_index(env, 0);
- if (riscv_cpu_fp_enabled(env)) {
- flags |= env->mstatus & MSTATUS_FS;
- }
-
- if (riscv_has_ext(env, RVH)) {
- if (env->priv == PRV_M ||
- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
- get_field(env->hstatus, HSTATUS_HU))) {
- flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
- }
-
- flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
- get_field(env->mstatus_hs, MSTATUS_FS));
- }
-#endif
-
- *pflags = flags;
-}
+void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+ target_ulong *cs_base, uint32_t *pflags);
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d41d5cd27c..14d1d3cb72 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -35,6 +35,52 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+ target_ulong *cs_base, uint32_t *pflags)
+{
+ uint32_t flags = 0;
+
+ *pc = env->pc;
+ *cs_base = 0;
+
+ if (riscv_has_ext(env, RVV)) {
+ uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
+ bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+ flags = FIELD_DP32(flags, TB_FLAGS, VILL,
+ FIELD_EX64(env->vtype, VTYPE, VILL));
+ flags = FIELD_DP32(flags, TB_FLAGS, SEW,
+ FIELD_EX64(env->vtype, VTYPE, VSEW));
+ flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
+ FIELD_EX64(env->vtype, VTYPE, VLMUL));
+ flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
+ } else {
+ flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
+ }
+
+#ifdef CONFIG_USER_ONLY
+ flags |= TB_FLAGS_MSTATUS_FS;
+#else
+ flags |= cpu_mmu_index(env, 0);
+ if (riscv_cpu_fp_enabled(env)) {
+ flags |= env->mstatus & MSTATUS_FS;
+ }
+
+ if (riscv_has_ext(env, RVH)) {
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
+ }
+
+ flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
+ get_field(env->mstatus_hs, MSTATUS_FS));
+ }
+#endif
+
+ *pflags = flags;
+}
+
#ifndef CONFIG_USER_ONLY
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-13 20:50 ` [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
@ 2021-10-13 20:50 ` Richard Henderson
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
` (10 subsequent siblings)
12 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
Move the MXL_RV* defines to enumerators.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_bits.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..e248c6bf6d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -364,9 +364,11 @@
#define MISA32_MXL 0xC0000000
#define MISA64_MXL 0xC000000000000000ULL
-#define MXL_RV32 1
-#define MXL_RV64 2
-#define MXL_RV128 3
+typedef enum {
+ MXL_RV32 = 1,
+ MXL_RV64 = 2,
+ MXL_RV128 = 3,
+} RISCVMXL;
/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-13 20:50 ` [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-13 20:50 ` [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
@ 2021-10-13 20:50 ` Richard Henderson
2021-10-14 7:52 ` LIU Zhiwei
2021-10-15 5:01 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
` (9 subsequent siblings)
12 siblings, 2 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
The hw representation of misa.mxl is at the high bits of the
misa csr. Representing this in the same way inside QEMU
results in overly complex code trying to check that field.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Reset misa.mxl.
---
target/riscv/cpu.h | 15 +++----
linux-user/elfload.c | 2 +-
linux-user/riscv/cpu_loop.c | 2 +-
target/riscv/cpu.c | 78 +++++++++++++++++++++----------------
target/riscv/csr.c | 44 ++++++++++++++-------
target/riscv/gdbstub.c | 8 ++--
target/riscv/machine.c | 10 +++--
target/riscv/translate.c | 10 +++--
8 files changed, 100 insertions(+), 69 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7084efc452..e708fcc168 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,7 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "qom/object.h"
+#include "cpu_bits.h"
#define TCG_GUEST_DEFAULT_MO 0
@@ -51,9 +52,6 @@
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
#endif
-#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
-#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
-
#define RV(x) ((target_ulong)1 << (x - 'A'))
#define RVI RV('I')
@@ -133,8 +131,12 @@ struct CPURISCVState {
target_ulong priv_ver;
target_ulong bext_ver;
target_ulong vext_ver;
- target_ulong misa;
- target_ulong misa_mask;
+
+ /* RISCVMXL, but uint32_t for vmstate migration */
+ uint32_t misa_mxl; /* current mxl */
+ uint32_t misa_mxl_max; /* max mxl for this cpu */
+ uint32_t misa_ext; /* current extensions */
+ uint32_t misa_ext_mask; /* max ext for this cpu */
uint32_t features;
@@ -313,7 +315,7 @@ struct RISCVCPU {
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
- return (env->misa & ext) != 0;
+ return (env->misa_ext & ext) != 0;
}
static inline bool riscv_feature(CPURISCVState *env, int feature)
@@ -322,7 +324,6 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
}
#include "cpu_user.h"
-#include "cpu_bits.h"
extern const char * const riscv_int_regnames[];
extern const char * const riscv_fpr_regnames[];
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 2404d482ba..214c1aa40d 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1448,7 +1448,7 @@ static uint32_t get_elf_hwcap(void)
uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
| MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
- return cpu->env.misa & mask;
+ return cpu->env.misa_ext & mask;
#undef MISA_BIT
}
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 9859a366e4..e5bb6d908a 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -133,7 +133,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
env->gpr[xSP] = regs->sp;
env->elf_flags = info->elf_flags;
- if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
+ if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
exit(EXIT_FAILURE);
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e..fdf031a394 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -110,16 +110,13 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
bool riscv_cpu_is_32bit(CPURISCVState *env)
{
- if (env->misa & RV64) {
- return false;
- }
-
- return true;
+ return env->misa_mxl == MXL_RV32;
}
-static void set_misa(CPURISCVState *env, target_ulong misa)
+static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
{
- env->misa_mask = env->misa = misa;
+ env->misa_mxl_max = env->misa_mxl = mxl;
+ env->misa_ext_mask = env->misa_ext = ext;
}
static void set_priv_version(CPURISCVState *env, int priv_ver)
@@ -148,9 +145,9 @@ static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
#if defined(TARGET_RISCV32)
- set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#elif defined(TARGET_RISCV64)
- set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
set_priv_version(env, PRIV_VERSION_1_11_0);
}
@@ -160,20 +157,20 @@ static void rv64_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
- set_misa(env, RV64);
+ set_misa(env, MXL_RV64, 0);
}
static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
}
static void rv64_sifive_e_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
+ set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
@@ -182,20 +179,20 @@ static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
- set_misa(env, RV32);
+ set_misa(env, MXL_RV32, 0);
}
static void rv32_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
}
static void rv32_sifive_e_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+ set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
@@ -203,7 +200,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
static void rv32_ibex_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVC | RVU);
+ set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
@@ -212,7 +209,7 @@ static void rv32_ibex_cpu_init(Object *obj)
static void rv32_imafcu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
+ set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
@@ -360,6 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev)
mcc->parent_reset(dev);
#ifndef CONFIG_USER_ONLY
+ env->misa_mxl = env->misa_mxl_max;
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
env->mcause = 0;
@@ -388,7 +386,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = 0;
- target_ulong target_misa = env->misa;
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
@@ -434,8 +431,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_resetvec(env, cpu->cfg.resetvec);
- /* If only XLEN is set for misa, then set misa from properties */
- if (env->misa == RV32 || env->misa == RV64) {
+ /* Validate that MISA_MXL is set properly. */
+ switch (env->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+ case MXL_RV64:
+ break;
+#endif
+ case MXL_RV32:
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ assert(env->misa_mxl_max == env->misa_mxl);
+
+ /* If only MISA_EXT is unset for misa, then set it from properties */
+ if (env->misa_ext == 0) {
+ uint32_t ext = 0;
+
/* Do some ISA extension error checking */
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
@@ -462,38 +474,38 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
- target_misa |= RVI;
+ ext |= RVI;
}
if (cpu->cfg.ext_e) {
- target_misa |= RVE;
+ ext |= RVE;
}
if (cpu->cfg.ext_m) {
- target_misa |= RVM;
+ ext |= RVM;
}
if (cpu->cfg.ext_a) {
- target_misa |= RVA;
+ ext |= RVA;
}
if (cpu->cfg.ext_f) {
- target_misa |= RVF;
+ ext |= RVF;
}
if (cpu->cfg.ext_d) {
- target_misa |= RVD;
+ ext |= RVD;
}
if (cpu->cfg.ext_c) {
- target_misa |= RVC;
+ ext |= RVC;
}
if (cpu->cfg.ext_s) {
- target_misa |= RVS;
+ ext |= RVS;
}
if (cpu->cfg.ext_u) {
- target_misa |= RVU;
+ ext |= RVU;
}
if (cpu->cfg.ext_h) {
- target_misa |= RVH;
+ ext |= RVH;
}
if (cpu->cfg.ext_v) {
int vext_version = VEXT_VERSION_0_07_1;
- target_misa |= RVV;
+ ext |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
"Vector extension VLEN must be power of 2");
@@ -532,7 +544,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_vext_version(env, vext_version);
}
- set_misa(env, target_misa);
+ set_misa(env, env->misa_mxl, ext);
}
riscv_cpu_register_gdb_regs_for_features(cs);
@@ -705,7 +717,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
char *isa_str = g_new(char, maxlen);
char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
for (i = 0; i < sizeof(riscv_exts); i++) {
- if (cpu->env.misa & RV(riscv_exts[i])) {
+ if (cpu->env.misa_ext & RV(riscv_exts[i])) {
*p++ = qemu_tolower(riscv_exts[i]);
}
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 23fbbd3216..d0c86a300d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -39,7 +39,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
/* loose check condition for fcsr in vector extension */
- if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
+ if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
return RISCV_EXCP_NONE;
}
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
@@ -51,7 +51,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno)
{
- if (env->misa & RVV) {
+ if (env->misa_ext & RVV) {
return RISCV_EXCP_NONE;
}
return RISCV_EXCP_ILLEGAL_INST;
@@ -557,7 +557,22 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
static RISCVException read_misa(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->misa;
+ target_ulong misa;
+
+ switch (env->misa_mxl) {
+ case MXL_RV32:
+ misa = (target_ulong)MXL_RV32 << 30;
+ break;
+#ifdef TARGET_RISCV64
+ case MXL_RV64:
+ misa = (target_ulong)MXL_RV64 << 62;
+ break;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+
+ *val = misa | env->misa_ext;
return RISCV_EXCP_NONE;
}
@@ -583,8 +598,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+ /*
+ * misa.MXL writes are not supported by QEMU.
+ * Drop writes to those bits.
+ */
+
/* Mask extensions that are not supported by this hart */
- val &= env->misa_mask;
+ val &= env->misa_ext_mask;
/* Mask extensions that are not supported by QEMU */
val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
@@ -601,20 +621,14 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
val &= ~RVC;
}
- /* misa.MXL writes are not supported by QEMU */
- if (riscv_cpu_is_32bit(env)) {
- val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
- } else {
- val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+ /* If nothing changed, do nothing. */
+ if (val == env->misa_ext) {
+ return RISCV_EXCP_NONE;
}
/* flush translation cache */
- if (val != env->misa) {
- tb_flush(env_cpu(env));
- }
-
- env->misa = val;
-
+ tb_flush(env_cpu(env));
+ env->misa_ext = val;
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index a7a9c0b1fe..5257df0217 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -54,10 +54,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
{
if (n < 32) {
- if (env->misa & RVD) {
+ if (env->misa_ext & RVD) {
return gdb_get_reg64(buf, env->fpr[n]);
}
- if (env->misa & RVF) {
+ if (env->misa_ext & RVF) {
return gdb_get_reg32(buf, env->fpr[n]);
}
/* there is hole between ft11 and fflags in fpu.xml */
@@ -191,10 +191,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- if (env->misa & RVD) {
+ if (env->misa_ext & RVD) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-64bit-fpu.xml", 0);
- } else if (env->misa & RVF) {
+ } else if (env->misa_ext & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0);
}
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 16a08302da..f64b2a96c1 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = {
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -153,8 +153,10 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
- VMSTATE_UINTTL(env.misa, RISCVCPU),
- VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
+ VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
+ VMSTATE_UINT32(env.misa_ext, RISCVCPU),
+ VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
+ VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
VMSTATE_UINT32(env.features, RISCVCPU),
VMSTATE_UINTTL(env.priv, RISCVCPU),
VMSTATE_UINTTL(env.virt, RISCVCPU),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d2442f0cf5..422f8ab8d0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -55,7 +55,8 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong priv_ver;
- target_ulong misa;
+ RISCVMXL xl;
+ uint32_t misa_ext;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t mstatus_hs_fs;
@@ -86,7 +87,7 @@ typedef struct DisasContext {
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
{
- return ctx->misa & ext;
+ return ctx->misa_ext & ext;
}
#ifdef TARGET_RISCV32
@@ -96,7 +97,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
#else
static inline bool is_32bit(DisasContext *ctx)
{
- return (ctx->misa & RV32) == RV32;
+ return ctx->xl == MXL_RV32;
}
#endif
@@ -538,7 +539,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#else
ctx->virt_enabled = false;
#endif
- ctx->misa = env->misa;
+ ctx->xl = env->misa_mxl;
+ ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->vlen = cpu->cfg.vlen;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (2 preceding siblings ...)
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
@ 2021-10-13 20:50 ` Richard Henderson
2021-10-14 7:08 ` LIU Zhiwei
2021-10-15 5:05 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
` (8 subsequent siblings)
12 siblings, 2 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 9 ++++++++-
hw/riscv/boot.c | 2 +-
semihosting/arm-compat-semi.c | 2 +-
target/riscv/cpu.c | 24 ++++++++++++++----------
target/riscv/cpu_helper.c | 12 ++++++------
target/riscv/csr.c | 24 ++++++++++++------------
target/riscv/gdbstub.c | 2 +-
target/riscv/monitor.c | 4 ++--
8 files changed, 45 insertions(+), 34 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e708fcc168..87248b562a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1)
FIELD(TB_FLAGS, HLSX, 9, 1)
FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
-bool riscv_cpu_is_32bit(CPURISCVState *env);
+#ifdef CONFIG_RISCV32
+#define riscv_cpu_mxl(env) MXL_RV32
+#else
+static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+{
+ return env->misa_mxl;
+}
+#endif
/*
* A simplification for VLMAX
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 993bf89064..d1ffc7b56c 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -35,7 +35,7 @@
bool riscv_is_32bit(RISCVHartArrayState *harts)
{
- return riscv_cpu_is_32bit(&harts->harts[0].env);
+ return harts->harts[0].env.misa_mxl_max == MXL_RV32;
}
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index 01badea99c..37963becae 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -775,7 +775,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env)
#if defined(TARGET_ARM)
return is_a64(env);
#elif defined(TARGET_RISCV)
- return !riscv_cpu_is_32bit(env);
+ return riscv_cpu_mxl(env) != MXL_RV32;
#else
#error un-handled architecture
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fdf031a394..1857670a69 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -108,11 +108,6 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
}
}
-bool riscv_cpu_is_32bit(CPURISCVState *env)
-{
- return env->misa_mxl == MXL_RV32;
-}
-
static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
{
env->misa_mxl_max = env->misa_mxl = mxl;
@@ -249,7 +244,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
(target_ulong)(env->mstatus >> 32));
}
@@ -372,10 +367,16 @@ static void riscv_cpu_reset(DeviceState *dev)
static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
RISCVCPU *cpu = RISCV_CPU(s);
- if (riscv_cpu_is_32bit(&cpu->env)) {
+
+ switch (riscv_cpu_mxl(&cpu->env)) {
+ case MXL_RV32:
info->print_insn = print_insn_riscv32;
- } else {
+ break;
+ case MXL_RV64:
info->print_insn = print_insn_riscv64;
+ break;
+ default:
+ g_assert_not_reached();
}
}
@@ -631,10 +632,13 @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- if (riscv_cpu_is_32bit(env)) {
+ switch (riscv_cpu_mxl(env)) {
+ case MXL_RV32:
return g_strdup("riscv:rv32");
- } else {
+ case MXL_RV64:
return g_strdup("riscv:rv64");
+ default:
+ g_assert_not_reached();
}
}
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 14d1d3cb72..403f54171d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -152,7 +152,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
- uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
+ uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
MSTATUS64_UXL | sd;
@@ -447,7 +447,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (first_stage == true) {
if (use_background) {
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->vsatp, SATP32_MODE);
} else {
@@ -455,7 +455,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
vm = get_field(env->vsatp, SATP64_MODE);
}
} else {
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP32_MODE);
} else {
@@ -465,7 +465,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
widened = 0;
} else {
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->hgatp, SATP32_MODE);
} else {
@@ -558,7 +558,7 @@ restart:
}
target_ulong pte;
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
} else {
pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
@@ -678,7 +678,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
int page_fault_exceptions, vm;
uint64_t stap_mode;
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
stap_mode = SATP32_MODE;
} else {
stap_mode = SATP64_MODE;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d0c86a300d..9c0753bc8b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -95,7 +95,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
switch (csrno) {
case CSR_CYCLEH:
if (!get_field(env->hcounteren, COUNTEREN_CY) &&
@@ -130,7 +130,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
static RISCVException ctr32(CPURISCVState *env, int csrno)
{
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -145,7 +145,7 @@ static RISCVException any(CPURISCVState *env, int csrno)
static RISCVException any32(CPURISCVState *env, int csrno)
{
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -180,7 +180,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
static RISCVException hmode32(CPURISCVState *env, int csrno)
{
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
if (riscv_cpu_virt_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
} else {
@@ -486,7 +486,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
static int validate_vm(CPURISCVState *env, target_ulong vm)
{
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
return valid_vm_1_10_32[vm & 0xf];
} else {
return valid_vm_1_10_64[vm & 0xf];
@@ -510,7 +510,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW;
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
/*
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
@@ -522,7 +522,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
} else {
mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
@@ -795,7 +795,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
{
target_ulong mask = (sstatus_v1_10_mask);
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
mask |= SSTATUS32_SD;
} else {
mask |= SSTATUS64_SD;
@@ -1006,7 +1006,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
vm = validate_vm(env, get_field(val, SATP32_MODE));
mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
asid = (val ^ env->satp) & SATP32_ASID;
@@ -1034,7 +1034,7 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
target_ulong *val)
{
*val = env->hstatus;
- if (!riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
/* We only support 64-bit VSXL */
*val = set_field(*val, HSTATUS_VSXL, 2);
}
@@ -1047,7 +1047,7 @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
env->hstatus = val;
- if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
+ if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
}
if (get_field(val, HSTATUS_VSBE) != 0) {
@@ -1215,7 +1215,7 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
return RISCV_EXCP_ILLEGAL_INST;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
} else {
env->htimedelta = val;
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 5257df0217..23429179e2 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -161,7 +161,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
CPURISCVState *env = &cpu->env;
GString *s = g_string_new(NULL);
riscv_csr_predicate_fn predicate;
- int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
+ int bitsize = 16 << env->misa_mxl_max;
int i;
g_string_printf(s, "<?xml version=\"1.0\"?>");
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index f7e6ea72b3..7efb4b62c1 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -150,7 +150,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
target_ulong last_size;
int last_attr;
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP32_MODE);
} else {
@@ -220,7 +220,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
- if (riscv_cpu_is_32bit(env)) {
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
if (!(env->satp & SATP32_MODE)) {
monitor_printf(mon, "No translation or protection\n");
return;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (3 preceding siblings ...)
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
@ 2021-10-13 20:50 ` Richard Henderson
2021-10-14 8:20 ` LIU Zhiwei
2021-10-15 12:37 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
` (7 subsequent siblings)
12 siblings, 2 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
Begin adding support for switching XLEN at runtime. Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Force SXL and UXL to valid values.
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 8 ++++++++
target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++
target/riscv/csr.c | 3 +++
target/riscv/translate.c | 2 +-
5 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 87248b562a..445ba5b395 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -395,6 +395,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
/* Is a Hypervisor instruction load/store allowed? */
FIELD(TB_FLAGS, HLSX, 9, 1)
FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
+/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
+FIELD(TB_FLAGS, XL, 12, 2)
#ifdef CONFIG_RISCV32
#define riscv_cpu_mxl(env) MXL_RV32
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1857670a69..840edd66f8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -355,6 +355,14 @@ static void riscv_cpu_reset(DeviceState *dev)
env->misa_mxl = env->misa_mxl_max;
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+ if (env->misa_mxl > MXL_RV32) {
+ /*
+ * The reset status of SXL/UXL is officially undefined,
+ * but invalid settings would result in a tcg assert.
+ */
+ env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
+ env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+ }
env->mcause = 0;
env->pc = env->resetvec;
env->two_stage_lookup = false;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 403f54171d..429afd1f48 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -35,6 +35,37 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
#endif
}
+static RISCVMXL cpu_get_xl(CPURISCVState *env)
+{
+#if defined(TARGET_RISCV32)
+ return MXL_RV32;
+#elif defined(CONFIG_USER_ONLY)
+ return MXL_RV64;
+#else
+ RISCVMXL xl = riscv_cpu_mxl(env);
+
+ /*
+ * When emulating a 32-bit-only cpu, use RV32.
+ * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
+ * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
+ * back to RV64 for lower privs.
+ */
+ if (xl != MXL_RV32) {
+ switch (env->priv) {
+ case PRV_M:
+ break;
+ case PRV_U:
+ xl = get_field(env->mstatus, MSTATUS64_UXL);
+ break;
+ default: /* PRV_S | PRV_H */
+ xl = get_field(env->mstatus, MSTATUS64_SXL);
+ break;
+ }
+ }
+ return xl;
+#endif
+}
+
void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
@@ -78,6 +109,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
}
#endif
+ flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
+
*pflags = flags;
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9c0753bc8b..c4a479ddd2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -526,6 +526,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
} else {
mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+ /* SXL and UXL fields are for now read only */
+ mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
+ mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
}
env->mstatus = mstatus;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 422f8ab8d0..7e7bb67d15 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -539,7 +539,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#else
ctx->virt_enabled = false;
#endif
- ctx->xl = env->misa_mxl;
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
@@ -551,6 +550,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
+ ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->cs = cs;
ctx->w = false;
ctx->ntemp = 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (4 preceding siblings ...)
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
@ 2021-10-13 20:50 ` Richard Henderson
2021-10-14 5:54 ` LIU Zhiwei
2021-10-15 5:08 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
` (6 subsequent siblings)
12 siblings, 2 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index fa451938f1..bbc5c93ef1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
static bool amo_check64(DisasContext *s, arg_rwdvm* a)
{
- return !is_32bit(s) && amo_check(s, a);
+ REQUIRE_64BIT(s);
+ return amo_check(s, a);
}
GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (5 preceding siblings ...)
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
@ 2021-10-13 20:50 ` Richard Henderson
2021-10-14 5:55 ` LIU Zhiwei
2021-10-15 5:09 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
` (5 subsequent siblings)
12 siblings, 2 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less. Use a switch and explicitly
bound both SEW and SEQ for all cases.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index bbc5c93ef1..91fca4a2d1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
gen_helper_exit_atomic(cpu_env);
s->base.is_jmp = DISAS_NORETURN;
return true;
- } else {
- if (s->sew == 3) {
- if (!is_32bit(s)) {
- fn = fnsd[seq];
- } else {
- /* Check done in amo_check(). */
- g_assert_not_reached();
- }
- } else {
- assert(seq < ARRAY_SIZE(fnsw));
- fn = fnsw[seq];
- }
+ }
+
+ switch (s->sew) {
+ case 0 ... 2:
+ assert(seq < ARRAY_SIZE(fnsw));
+ fn = fnsw[seq];
+ break;
+ case 3:
+ /* XLEN check done in amo_check(). */
+ assert(seq < ARRAY_SIZE(fnsd));
+ fn = fnsd[seq];
+ break;
+ default:
+ g_assert_not_reached();
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (6 preceding siblings ...)
2021-10-13 20:50 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
@ 2021-10-13 20:50 ` Richard Henderson
2021-10-14 8:26 ` LIU Zhiwei
2021-10-15 5:11 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
` (4 subsequent siblings)
12 siblings, 2 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
In preparation for RV128, replace a simple predicate
with a more versatile test.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7e7bb67d15..5724a62bb0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -91,16 +91,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
}
#ifdef TARGET_RISCV32
-# define is_32bit(ctx) true
+#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
-# define is_32bit(ctx) false
+#define get_xl(ctx) MXL_RV64
#else
-static inline bool is_32bit(DisasContext *ctx)
-{
- return ctx->xl == MXL_RV32;
-}
+#define get_xl(ctx) ((ctx)->xl)
#endif
+static inline int get_xlen(DisasContext *ctx)
+{
+ return 16 << get_xl(ctx);
+}
+
/* The word size for this operation. */
static inline int oper_len(DisasContext *ctx)
{
@@ -282,7 +284,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
- target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+ target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
if (ctx->mstatus_fs != MSTATUS_FS) {
/* Remember the state change for the rest of the TB. */
@@ -341,16 +343,16 @@ EX_SH(12)
} \
} while (0)
-#define REQUIRE_32BIT(ctx) do { \
- if (!is_32bit(ctx)) { \
- return false; \
- } \
+#define REQUIRE_32BIT(ctx) do { \
+ if (get_xl(ctx) != MXL_RV32) { \
+ return false; \
+ } \
} while (0)
-#define REQUIRE_64BIT(ctx) do { \
- if (is_32bit(ctx)) { \
- return false; \
- } \
+#define REQUIRE_64BIT(ctx) do { \
+ if (get_xl(ctx) < MXL_RV64) { \
+ return false; \
+ } \
} while (0)
static int ex_rvc_register(DisasContext *ctx, int reg)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (7 preceding siblings ...)
2021-10-13 20:50 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
@ 2021-10-13 20:51 ` Richard Henderson
2021-10-14 8:40 ` LIU Zhiwei
2021-10-15 5:19 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
` (3 subsequent siblings)
12 siblings, 2 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:51 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
In preparation for RV128, consider more than just "w" for
operand size modification. This will be used for the "d"
insns from RV128 as well.
Rename oper_len to get_olen to better match get_xlen.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 71 ++++++++++++++++---------
target/riscv/insn_trans/trans_rvb.c.inc | 8 +--
target/riscv/insn_trans/trans_rvi.c.inc | 18 +++----
target/riscv/insn_trans/trans_rvm.c.inc | 10 ++--
4 files changed, 63 insertions(+), 44 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5724a62bb0..6ab5c6aa58 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -67,7 +67,7 @@ typedef struct DisasContext {
to any system register, which includes CSR_FRM, so we do not have
to reset this known value. */
int frm;
- bool w;
+ RISCVMXL ol;
bool virt_enabled;
bool ext_ifencei;
bool hlsx;
@@ -103,12 +103,17 @@ static inline int get_xlen(DisasContext *ctx)
return 16 << get_xl(ctx);
}
-/* The word size for this operation. */
-static inline int oper_len(DisasContext *ctx)
-{
- return ctx->w ? 32 : TARGET_LONG_BITS;
-}
+/* The operation length, as opposed to the xlen. */
+#ifdef TARGET_RISCV32
+#define get_ol(ctx) MXL_RV32
+#else
+#define get_ol(ctx) ((ctx)->ol)
+#endif
+static inline int get_olen(DisasContext *ctx)
+{
+ return 16 << get_ol(ctx);
+}
/*
* RISC-V requires NaN-boxing of narrower width floating point values.
@@ -221,24 +226,34 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
return ctx->zero;
}
- switch (ctx->w ? ext : EXT_NONE) {
- case EXT_NONE:
- return cpu_gpr[reg_num];
- case EXT_SIGN:
- t = temp_new(ctx);
- tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
- return t;
- case EXT_ZERO:
- t = temp_new(ctx);
- tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
- return t;
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
+ switch (ext) {
+ case EXT_NONE:
+ break;
+ case EXT_SIGN:
+ t = temp_new(ctx);
+ tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
+ return t;
+ case EXT_ZERO:
+ t = temp_new(ctx);
+ tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
+ return t;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+ case MXL_RV64:
+ break;
+ default:
+ g_assert_not_reached();
}
- g_assert_not_reached();
+ return cpu_gpr[reg_num];
}
static TCGv dest_gpr(DisasContext *ctx, int reg_num)
{
- if (reg_num == 0 || ctx->w) {
+ if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
return temp_new(ctx);
}
return cpu_gpr[reg_num];
@@ -247,10 +262,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
{
if (reg_num != 0) {
- if (ctx->w) {
+ switch (get_ol(ctx)) {
+ case MXL_RV32:
tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
- } else {
+ break;
+ case MXL_RV64:
tcg_gen_mov_tl(cpu_gpr[reg_num], t);
+ break;
+ default:
+ g_assert_not_reached();
}
}
}
@@ -411,7 +431,7 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
void (*func)(TCGv, TCGv, target_long))
{
TCGv dest, src1;
- int max_len = oper_len(ctx);
+ int max_len = get_olen(ctx);
if (a->shamt >= max_len) {
return false;
@@ -430,7 +450,7 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
void (*func)(TCGv, TCGv, TCGv))
{
TCGv dest, src1, src2;
- int max_len = oper_len(ctx);
+ int max_len = get_olen(ctx);
if (a->shamt >= max_len) {
return false;
@@ -454,7 +474,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
TCGv ext2 = tcg_temp_new();
- tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
+ tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
func(dest, src1, ext2);
gen_set_gpr(ctx, a->rd, dest);
@@ -554,7 +574,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->cs = cs;
- ctx->w = false;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
@@ -578,9 +597,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
CPURISCVState *env = cpu->env_ptr;
uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
+ ctx->ol = ctx->xl;
decode_opc(env, ctx, opcode16);
ctx->base.pc_next = ctx->pc_succ_insn;
- ctx->w = false;
for (int i = ctx->ntemp - 1; i >= 0; --i) {
tcg_temp_free(ctx->temp[i]);
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 185c3e9a60..66dd51de49 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -341,7 +341,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
@@ -367,7 +367,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rorw);
}
@@ -375,7 +375,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
}
@@ -401,7 +401,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rolw);
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 920ae0edb3..c0a46d823f 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -333,14 +333,14 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
REQUIRE_64BIT(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
REQUIRE_64BIT(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
}
@@ -352,7 +352,7 @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
}
@@ -364,42 +364,42 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
REQUIRE_64BIT(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
REQUIRE_64BIT(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
REQUIRE_64BIT(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
REQUIRE_64BIT(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
REQUIRE_64BIT(ctx);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
}
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index b89a85ad3a..9a1fe3c799 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -214,7 +214,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
}
@@ -222,7 +222,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_arith(ctx, a, EXT_SIGN, gen_div);
}
@@ -230,7 +230,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_arith(ctx, a, EXT_ZERO, gen_divu);
}
@@ -238,7 +238,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_arith(ctx, a, EXT_SIGN, gen_rem);
}
@@ -246,6 +246,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
- ctx->w = true;
+ ctx->ol = MXL_RV32;
return gen_arith(ctx, a, EXT_ZERO, gen_remu);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (8 preceding siblings ...)
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
@ 2021-10-13 20:51 ` Richard Henderson
2021-10-13 20:51 ` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
` (2 subsequent siblings)
12 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:51 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 16 +++++++++++++++
target/riscv/insn_trans/trans_rvm.c.inc | 26 ++++++++++++++++++++++---
2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6ab5c6aa58..f960929c16 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -427,6 +427,22 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
return true;
}
+static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
+ void (*f_tl)(TCGv, TCGv, TCGv),
+ void (*f_32)(TCGv, TCGv, TCGv))
+{
+ int olen = get_olen(ctx);
+
+ if (olen != TARGET_LONG_BITS) {
+ if (olen == 32) {
+ f_tl = f_32;
+ } else {
+ g_assert_not_reached();
+ }
+ }
+ return gen_arith(ctx, a, ext, f_tl);
+}
+
static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
void (*func)(TCGv, TCGv, target_long))
{
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index 9a1fe3c799..2af0e5c139 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -33,10 +33,16 @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
tcg_temp_free(discard);
}
+static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
+{
+ tcg_gen_mul_tl(ret, s1, s2);
+ tcg_gen_sari_tl(ret, ret, 32);
+}
+
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, gen_mulh);
+ return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w);
}
static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -54,10 +60,23 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
+static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ tcg_gen_ext32s_tl(t1, arg1);
+ tcg_gen_ext32u_tl(t2, arg2);
+ tcg_gen_mul_tl(ret, t1, t2);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ tcg_gen_sari_tl(ret, ret, 32);
+}
+
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
+ return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w);
}
static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
@@ -71,7 +90,8 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
+ /* gen_mulh_w works for either sign as input. */
+ return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w);
}
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (9 preceding siblings ...)
2021-10-13 20:51 ` [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
@ 2021-10-13 20:51 ` Richard Henderson
2021-10-15 5:21 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-13 20:51 ` [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
12 siblings, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:51 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 66dd51de49..c62eea433a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
+static void gen_rev8_32(TCGv ret, TCGv src1)
+{
+ tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+ return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (10 preceding siblings ...)
2021-10-13 20:51 ` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
@ 2021-10-13 20:51 ` Richard Henderson
2021-10-13 20:51 ` [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
12 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:51 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 16 ++++++++++++
target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++-------------
2 files changed, 32 insertions(+), 17 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f960929c16..be458ae0c2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -510,6 +510,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
return true;
}
+static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+ void (*f_tl)(TCGv, TCGv),
+ void (*f_32)(TCGv, TCGv))
+{
+ int olen = get_olen(ctx);
+
+ if (olen != TARGET_LONG_BITS) {
+ if (olen == 32) {
+ f_tl = f_32;
+ } else {
+ g_assert_not_reached();
+ }
+ }
+ return gen_unary(ctx, a, ext, f_tl);
+}
+
static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index c62eea433a..0c2120428d 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1)
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
}
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shli_tl(t, arg1, 32);
+ tcg_gen_clzi_tl(ret, t, 32);
+ tcg_temp_free(t);
+}
+
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_ZERO, gen_clz);
+ return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
}
static void gen_ctz(TCGv ret, TCGv arg1)
@@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1)
tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
}
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ctzi_tl(ret, arg1, 32);
+}
+
static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
{
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
+ return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
}
static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
@@ -314,14 +327,6 @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
}
-static void gen_clzw(TCGv ret, TCGv arg1)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_shli_tl(t, arg1, 32);
- tcg_gen_clzi_tl(ret, t, 32);
- tcg_temp_free(t);
-}
-
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -329,17 +334,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
return gen_unary(ctx, a, EXT_NONE, gen_clzw);
}
-static void gen_ctzw(TCGv ret, TCGv arg1)
-{
- tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
- tcg_gen_ctzi_tl(ret, ret, 64);
-}
-
static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
+ return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
}
static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
` (11 preceding siblings ...)
2021-10-13 20:51 ` [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
@ 2021-10-13 20:51 ` Richard Henderson
12 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-13 20:51 UTC (permalink / raw)
To: qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, zhiwei_liu, fabien.portas
Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 31 +++++++++
target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++-----------
target/riscv/insn_trans/trans_rvi.c.inc | 26 +++----
3 files changed, 97 insertions(+), 52 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index be458ae0c2..dbe3670ff3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -462,6 +462,22 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
return true;
}
+static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
+ DisasExtend ext,
+ void (*f_tl)(TCGv, TCGv, target_long),
+ void (*f_32)(TCGv, TCGv, target_long))
+{
+ int olen = get_olen(ctx);
+ if (olen != TARGET_LONG_BITS) {
+ if (olen == 32) {
+ f_tl = f_32;
+ } else {
+ g_assert_not_reached();
+ }
+ }
+ return gen_shift_imm_fn(ctx, a, ext, f_tl);
+}
+
static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
void (*func)(TCGv, TCGv, TCGv))
{
@@ -498,6 +514,21 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
return true;
}
+static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
+ void (*f_tl)(TCGv, TCGv, TCGv),
+ void (*f_32)(TCGv, TCGv, TCGv))
+{
+ int olen = get_olen(ctx);
+ if (olen != TARGET_LONG_BITS) {
+ if (olen == 32) {
+ f_tl = f_32;
+ } else {
+ g_assert_not_reached();
+ }
+ }
+ return gen_shift(ctx, a, ext, f_tl);
+}
+
static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
void (*func)(TCGv, TCGv))
{
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 0c2120428d..cc39e6033b 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -227,22 +227,70 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
}
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
REQUIRE_ZBB(ctx);
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
+ return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw);
+}
+
+static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_rotri_i32(t1, t1, shamt);
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
}
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
REQUIRE_ZBB(ctx);
- return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
+ return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+ tcg_gen_rotri_tl, gen_roriw);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ /* truncate to 32-bits */
+ tcg_gen_trunc_tl_i32(t1, arg1);
+ tcg_gen_trunc_tl_i32(t2, arg2);
+
+ tcg_gen_rotl_i32(t1, t1, t2);
+
+ /* sign-extend 64-bits */
+ tcg_gen_ext_i32_tl(ret, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
}
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
REQUIRE_ZBB(ctx);
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
+ return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw);
}
static void gen_rev8_32(TCGv ret, TCGv src1)
@@ -349,24 +397,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
-static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv_i32 t1 = tcg_temp_new_i32();
- TCGv_i32 t2 = tcg_temp_new_i32();
-
- /* truncate to 32-bits */
- tcg_gen_trunc_tl_i32(t1, arg1);
- tcg_gen_trunc_tl_i32(t2, arg2);
-
- tcg_gen_rotr_i32(t1, t1, t2);
-
- /* sign-extend 64-bits */
- tcg_gen_ext_i32_tl(ret, t1);
-
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
-}
-
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
{
REQUIRE_64BIT(ctx);
@@ -380,25 +410,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
ctx->ol = MXL_RV32;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
-}
-
-static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
-{
- TCGv_i32 t1 = tcg_temp_new_i32();
- TCGv_i32 t2 = tcg_temp_new_i32();
-
- /* truncate to 32-bits */
- tcg_gen_trunc_tl_i32(t1, arg1);
- tcg_gen_trunc_tl_i32(t2, arg2);
-
- tcg_gen_rotl_i32(t1, t1, t2);
-
- /* sign-extend 64-bits */
- tcg_gen_ext_i32_tl(ret, t1);
-
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw);
}
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index c0a46d823f..b0fdec97de 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -270,14 +270,26 @@ static bool trans_slli(DisasContext *ctx, arg_slli *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
}
+static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
+{
+ tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
+}
+
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
- return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
+ return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+ tcg_gen_shri_tl, gen_srliw);
+}
+
+static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
+{
+ tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
- return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
+ return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+ tcg_gen_sari_tl, gen_sraiw);
}
static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -344,11 +356,6 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
}
-static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
-{
- tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
-}
-
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
@@ -356,11 +363,6 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
}
-static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
-{
- tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
-}
-
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
@ 2021-10-14 5:54 ` LIU Zhiwei
2021-10-15 5:08 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: LIU Zhiwei @ 2021-10-14 5:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 2021/10/14 上午4:50, Richard Henderson wrote:
> Use the same REQUIRE_64BIT check that we use elsewhere,
> rather than open-coding the use of is_32bit.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Zhiwei
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index fa451938f1..bbc5c93ef1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
>
> static bool amo_check64(DisasContext *s, arg_rwdvm* a)
> {
> - return !is_32bit(s) && amo_check(s, a);
> + REQUIRE_64BIT(s);
> + return amo_check(s, a);
> }
>
> GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op
2021-10-13 20:50 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
@ 2021-10-14 5:55 ` LIU Zhiwei
2021-10-15 5:09 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: LIU Zhiwei @ 2021-10-14 5:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 2021/10/14 上午4:50, Richard Henderson wrote:
> We're currently assuming SEW <= 3, and the "else" from
> the SEW == 3 must be less. Use a switch and explicitly
> bound both SEW and SEQ for all cases.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Zhiwei
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index bbc5c93ef1..91fca4a2d1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
> gen_helper_exit_atomic(cpu_env);
> s->base.is_jmp = DISAS_NORETURN;
> return true;
> - } else {
> - if (s->sew == 3) {
> - if (!is_32bit(s)) {
> - fn = fnsd[seq];
> - } else {
> - /* Check done in amo_check(). */
> - g_assert_not_reached();
> - }
> - } else {
> - assert(seq < ARRAY_SIZE(fnsw));
> - fn = fnsw[seq];
> - }
> + }
> +
> + switch (s->sew) {
> + case 0 ... 2:
> + assert(seq < ARRAY_SIZE(fnsw));
> + fn = fnsw[seq];
> + break;
> + case 3:
> + /* XLEN check done in amo_check(). */
> + assert(seq < ARRAY_SIZE(fnsd));
> + fn = fnsd[seq];
> + break;
> + default:
> + g_assert_not_reached();
> }
>
> data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
@ 2021-10-14 7:08 ` LIU Zhiwei
2021-10-14 16:01 ` Richard Henderson
2021-10-15 5:05 ` Alistair Francis
1 sibling, 1 reply; 34+ messages in thread
From: LIU Zhiwei @ 2021-10-14 7:08 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 2021/10/14 上午4:50, Richard Henderson wrote:
> Shortly, the set of supported XL will not be just 32 and 64,
> and representing that properly using the enumeration will be
> imperative.
>
> Two places, booting and gdb, intentionally use misa_mxl_max
> to emphasize the use of the reset value of misa.mxl, and not
> the current cpu state.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/cpu.h | 9 ++++++++-
> hw/riscv/boot.c | 2 +-
> semihosting/arm-compat-semi.c | 2 +-
> target/riscv/cpu.c | 24 ++++++++++++++----------
> target/riscv/cpu_helper.c | 12 ++++++------
> target/riscv/csr.c | 24 ++++++++++++------------
> target/riscv/gdbstub.c | 2 +-
> target/riscv/monitor.c | 4 ++--
> 8 files changed, 45 insertions(+), 34 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e708fcc168..87248b562a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1)
> FIELD(TB_FLAGS, HLSX, 9, 1)
> FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
>
> -bool riscv_cpu_is_32bit(CPURISCVState *env);
> +#ifdef CONFIG_RISCV32
> +#define riscv_cpu_mxl(env) MXL_RV32
> +#else
> +static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
> +{
> + return env->misa_mxl;
> +}
> +#endif
>
Hi Richard,
I don't know why we use CONFIG_RISCV32 here. I looked through the target
source code. It doesn't use this macro before.
And why we need special process of CONFIG_RISCV32.
> /*
> * A simplification for VLMAX
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 993bf89064..d1ffc7b56c 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -35,7 +35,7 @@
>
> bool riscv_is_32bit(RISCVHartArrayState *harts)
> {
> - return riscv_cpu_is_32bit(&harts->harts[0].env);
> + return harts->harts[0].env.misa_mxl_max == MXL_RV32;
Why not use misa_mxl here? As this is just a replacement of
riscv_cpu_is_32bit like many other places.
I think it should give more explicitly explanation when we use misa_mxl_max.
Thanks,
Zhiwei
> }
>
> target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
> diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
> index 01badea99c..37963becae 100644
> --- a/semihosting/arm-compat-semi.c
> +++ b/semihosting/arm-compat-semi.c
> @@ -775,7 +775,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env)
> #if defined(TARGET_ARM)
> return is_a64(env);
> #elif defined(TARGET_RISCV)
> - return !riscv_cpu_is_32bit(env);
> + return riscv_cpu_mxl(env) != MXL_RV32;
> #else
> #error un-handled architecture
> #endif
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fdf031a394..1857670a69 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -108,11 +108,6 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
> }
> }
>
> -bool riscv_cpu_is_32bit(CPURISCVState *env)
> -{
> - return env->misa_mxl == MXL_RV32;
> -}
> -
> static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
> {
> env->misa_mxl_max = env->misa_mxl = mxl;
> @@ -249,7 +244,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> #ifndef CONFIG_USER_ONLY
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
> (target_ulong)(env->mstatus >> 32));
> }
> @@ -372,10 +367,16 @@ static void riscv_cpu_reset(DeviceState *dev)
> static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
> {
> RISCVCPU *cpu = RISCV_CPU(s);
> - if (riscv_cpu_is_32bit(&cpu->env)) {
> +
> + switch (riscv_cpu_mxl(&cpu->env)) {
> + case MXL_RV32:
> info->print_insn = print_insn_riscv32;
> - } else {
> + break;
> + case MXL_RV64:
> info->print_insn = print_insn_riscv64;
> + break;
> + default:
> + g_assert_not_reached();
> }
> }
>
> @@ -631,10 +632,13 @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
>
> - if (riscv_cpu_is_32bit(env)) {
> + switch (riscv_cpu_mxl(env)) {
> + case MXL_RV32:
> return g_strdup("riscv:rv32");
> - } else {
> + case MXL_RV64:
> return g_strdup("riscv:rv64");
> + default:
> + g_assert_not_reached();
> }
> }
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 14d1d3cb72..403f54171d 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -152,7 +152,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
>
> void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
> {
> - uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
> + uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
> uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
> MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
> MSTATUS64_UXL | sd;
> @@ -447,7 +447,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>
> if (first_stage == true) {
> if (use_background) {
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
> vm = get_field(env->vsatp, SATP32_MODE);
> } else {
> @@ -455,7 +455,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> vm = get_field(env->vsatp, SATP64_MODE);
> }
> } else {
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
> vm = get_field(env->satp, SATP32_MODE);
> } else {
> @@ -465,7 +465,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> }
> widened = 0;
> } else {
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
> vm = get_field(env->hgatp, SATP32_MODE);
> } else {
> @@ -558,7 +558,7 @@ restart:
> }
>
> target_ulong pte;
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
> } else {
> pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
> @@ -678,7 +678,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
> int page_fault_exceptions, vm;
> uint64_t stap_mode;
>
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> stap_mode = SATP32_MODE;
> } else {
> stap_mode = SATP64_MODE;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d0c86a300d..9c0753bc8b 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -95,7 +95,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> }
> break;
> }
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> switch (csrno) {
> case CSR_CYCLEH:
> if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> @@ -130,7 +130,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>
> static RISCVException ctr32(CPURISCVState *env, int csrno)
> {
> - if (!riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) != MXL_RV32) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -145,7 +145,7 @@ static RISCVException any(CPURISCVState *env, int csrno)
>
> static RISCVException any32(CPURISCVState *env, int csrno)
> {
> - if (!riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) != MXL_RV32) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> @@ -180,7 +180,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
>
> static RISCVException hmode32(CPURISCVState *env, int csrno)
> {
> - if (!riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) != MXL_RV32) {
> if (riscv_cpu_virt_enabled(env)) {
> return RISCV_EXCP_ILLEGAL_INST;
> } else {
> @@ -486,7 +486,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
>
> static int validate_vm(CPURISCVState *env, target_ulong vm)
> {
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> return valid_vm_1_10_32[vm & 0xf];
> } else {
> return valid_vm_1_10_64[vm & 0xf];
> @@ -510,7 +510,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> MSTATUS_TW;
>
> - if (!riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) != MXL_RV32) {
> /*
> * RV32: MPV and GVA are not in mstatus. The current plan is to
> * add them to mstatush. For now, we just don't support it.
> @@ -522,7 +522,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
>
> dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
> ((mstatus & MSTATUS_XS) == MSTATUS_XS);
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
> } else {
> mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
> @@ -795,7 +795,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
> {
> target_ulong mask = (sstatus_v1_10_mask);
>
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> mask |= SSTATUS32_SD;
> } else {
> mask |= SSTATUS64_SD;
> @@ -1006,7 +1006,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> vm = validate_vm(env, get_field(val, SATP32_MODE));
> mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
> asid = (val ^ env->satp) & SATP32_ASID;
> @@ -1034,7 +1034,7 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> *val = env->hstatus;
> - if (!riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) != MXL_RV32) {
> /* We only support 64-bit VSXL */
> *val = set_field(*val, HSTATUS_VSXL, 2);
> }
> @@ -1047,7 +1047,7 @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> env->hstatus = val;
> - if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
> + if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
> qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
> }
> if (get_field(val, HSTATUS_VSBE) != 0) {
> @@ -1215,7 +1215,7 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
> } else {
> env->htimedelta = val;
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 5257df0217..23429179e2 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -161,7 +161,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
> CPURISCVState *env = &cpu->env;
> GString *s = g_string_new(NULL);
> riscv_csr_predicate_fn predicate;
> - int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
> + int bitsize = 16 << env->misa_mxl_max;
> int i;
>
> g_string_printf(s, "<?xml version=\"1.0\"?>");
> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> index f7e6ea72b3..7efb4b62c1 100644
> --- a/target/riscv/monitor.c
> +++ b/target/riscv/monitor.c
> @@ -150,7 +150,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
> target_ulong last_size;
> int last_attr;
>
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
> vm = get_field(env->satp, SATP32_MODE);
> } else {
> @@ -220,7 +220,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
> return;
> }
>
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> if (!(env->satp & SATP32_MODE)) {
> monitor_printf(mon, "No translation or protection\n");
> return;
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
@ 2021-10-14 7:52 ` LIU Zhiwei
2021-10-14 15:52 ` Richard Henderson
2021-10-15 5:01 ` Alistair Francis
1 sibling, 1 reply; 34+ messages in thread
From: LIU Zhiwei @ 2021-10-14 7:52 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 2021/10/14 上午4:50, Richard Henderson wrote:
> The hw representation of misa.mxl is at the high bits of the
> misa csr. Representing this in the same way inside QEMU
> results in overly complex code trying to check that field.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v2: Reset misa.mxl.
> ---
> target/riscv/cpu.h | 15 +++----
> linux-user/elfload.c | 2 +-
> linux-user/riscv/cpu_loop.c | 2 +-
> target/riscv/cpu.c | 78 +++++++++++++++++++++----------------
> target/riscv/csr.c | 44 ++++++++++++++-------
> target/riscv/gdbstub.c | 8 ++--
> target/riscv/machine.c | 10 +++--
> target/riscv/translate.c | 10 +++--
> 8 files changed, 100 insertions(+), 69 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7084efc452..e708fcc168 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -25,6 +25,7 @@
> #include "exec/cpu-defs.h"
> #include "fpu/softfloat-types.h"
> #include "qom/object.h"
> +#include "cpu_bits.h"
>
> #define TCG_GUEST_DEFAULT_MO 0
>
> @@ -51,9 +52,6 @@
> # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
> #endif
>
> -#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
> -#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> -
> #define RV(x) ((target_ulong)1 << (x - 'A'))
>
> #define RVI RV('I')
> @@ -133,8 +131,12 @@ struct CPURISCVState {
> target_ulong priv_ver;
> target_ulong bext_ver;
> target_ulong vext_ver;
> - target_ulong misa;
> - target_ulong misa_mask;
> +
> + /* RISCVMXL, but uint32_t for vmstate migration */
> + uint32_t misa_mxl; /* current mxl */
> + uint32_t misa_mxl_max; /* max mxl for this cpu */
> + uint32_t misa_ext; /* current extensions */
> + uint32_t misa_ext_mask; /* max ext for this cpu */
>
> uint32_t features;
>
> @@ -313,7 +315,7 @@ struct RISCVCPU {
>
> static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
> {
> - return (env->misa & ext) != 0;
> + return (env->misa_ext & ext) != 0;
> }
>
> static inline bool riscv_feature(CPURISCVState *env, int feature)
> @@ -322,7 +324,6 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
> }
>
> #include "cpu_user.h"
> -#include "cpu_bits.h"
>
> extern const char * const riscv_int_regnames[];
> extern const char * const riscv_fpr_regnames[];
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 2404d482ba..214c1aa40d 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1448,7 +1448,7 @@ static uint32_t get_elf_hwcap(void)
> uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
> | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
>
> - return cpu->env.misa & mask;
> + return cpu->env.misa_ext & mask;
> #undef MISA_BIT
> }
>
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 9859a366e4..e5bb6d908a 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -133,7 +133,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
> env->gpr[xSP] = regs->sp;
> env->elf_flags = info->elf_flags;
>
> - if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
> + if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
> error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
> exit(EXIT_FAILURE);
> }
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1d69d1887e..fdf031a394 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -110,16 +110,13 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
>
> bool riscv_cpu_is_32bit(CPURISCVState *env)
> {
> - if (env->misa & RV64) {
> - return false;
> - }
> -
> - return true;
> + return env->misa_mxl == MXL_RV32;
> }
>
> -static void set_misa(CPURISCVState *env, target_ulong misa)
> +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
> {
> - env->misa_mask = env->misa = misa;
> + env->misa_mxl_max = env->misa_mxl = mxl;
> + env->misa_ext_mask = env->misa_ext = ext;
> }
>
> static void set_priv_version(CPURISCVState *env, int priv_ver)
> @@ -148,9 +145,9 @@ static void riscv_any_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> #if defined(TARGET_RISCV32)
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> #elif defined(TARGET_RISCV64)
> - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> #endif
> set_priv_version(env, PRIV_VERSION_1_11_0);
> }
> @@ -160,20 +157,20 @@ static void rv64_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> - set_misa(env, RV64);
> + set_misa(env, MXL_RV64, 0);
> }
>
> static void rv64_sifive_u_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> }
>
> static void rv64_sifive_e_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
> + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
> @@ -182,20 +179,20 @@ static void rv32_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> - set_misa(env, RV32);
> + set_misa(env, MXL_RV32, 0);
> }
>
> static void rv32_sifive_u_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> }
>
> static void rv32_sifive_e_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
> @@ -203,7 +200,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
> static void rv32_ibex_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
> @@ -212,7 +209,7 @@ static void rv32_ibex_cpu_init(Object *obj)
> static void rv32_imafcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> set_resetvec(env, DEFAULT_RSTVEC);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> @@ -360,6 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev)
>
> mcc->parent_reset(dev);
> #ifndef CONFIG_USER_ONLY
> + env->misa_mxl = env->misa_mxl_max;
As we have set misa_mxl in cpu_init_fn, why set it again here?
Thanks,Zhiwei
> env->priv = PRV_M;
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> env->mcause = 0;
> @@ -388,7 +386,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> CPURISCVState *env = &cpu->env;
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> int priv_version = 0;
> - target_ulong target_misa = env->misa;
> Error *local_err = NULL;
>
> cpu_exec_realizefn(cs, &local_err);
> @@ -434,8 +431,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>
> set_resetvec(env, cpu->cfg.resetvec);
>
> - /* If only XLEN is set for misa, then set misa from properties */
> - if (env->misa == RV32 || env->misa == RV64) {
> + /* Validate that MISA_MXL is set properly. */
> + switch (env->misa_mxl_max) {
> +#ifdef TARGET_RISCV64
> + case MXL_RV64:
> + break;
> +#endif
> + case MXL_RV32:
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + assert(env->misa_mxl_max == env->misa_mxl);
> +
> + /* If only MISA_EXT is unset for misa, then set it from properties */
> + if (env->misa_ext == 0) {
> + uint32_t ext = 0;
> +
> /* Do some ISA extension error checking */
> if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
> error_setg(errp,
> @@ -462,38 +474,38 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>
> /* Set the ISA extensions, checks should have happened above */
> if (cpu->cfg.ext_i) {
> - target_misa |= RVI;
> + ext |= RVI;
> }
> if (cpu->cfg.ext_e) {
> - target_misa |= RVE;
> + ext |= RVE;
> }
> if (cpu->cfg.ext_m) {
> - target_misa |= RVM;
> + ext |= RVM;
> }
> if (cpu->cfg.ext_a) {
> - target_misa |= RVA;
> + ext |= RVA;
> }
> if (cpu->cfg.ext_f) {
> - target_misa |= RVF;
> + ext |= RVF;
> }
> if (cpu->cfg.ext_d) {
> - target_misa |= RVD;
> + ext |= RVD;
> }
> if (cpu->cfg.ext_c) {
> - target_misa |= RVC;
> + ext |= RVC;
> }
> if (cpu->cfg.ext_s) {
> - target_misa |= RVS;
> + ext |= RVS;
> }
> if (cpu->cfg.ext_u) {
> - target_misa |= RVU;
> + ext |= RVU;
> }
> if (cpu->cfg.ext_h) {
> - target_misa |= RVH;
> + ext |= RVH;
> }
> if (cpu->cfg.ext_v) {
> int vext_version = VEXT_VERSION_0_07_1;
> - target_misa |= RVV;
> + ext |= RVV;
> if (!is_power_of_2(cpu->cfg.vlen)) {
> error_setg(errp,
> "Vector extension VLEN must be power of 2");
> @@ -532,7 +544,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> set_vext_version(env, vext_version);
> }
>
> - set_misa(env, target_misa);
> + set_misa(env, env->misa_mxl, ext);
> }
>
> riscv_cpu_register_gdb_regs_for_features(cs);
> @@ -705,7 +717,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> char *isa_str = g_new(char, maxlen);
> char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> for (i = 0; i < sizeof(riscv_exts); i++) {
> - if (cpu->env.misa & RV(riscv_exts[i])) {
> + if (cpu->env.misa_ext & RV(riscv_exts[i])) {
> *p++ = qemu_tolower(riscv_exts[i]);
> }
> }
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 23fbbd3216..d0c86a300d 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -39,7 +39,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* loose check condition for fcsr in vector extension */
> - if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
> + if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
> return RISCV_EXCP_NONE;
> }
> if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> @@ -51,7 +51,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
>
> static RISCVException vs(CPURISCVState *env, int csrno)
> {
> - if (env->misa & RVV) {
> + if (env->misa_ext & RVV) {
> return RISCV_EXCP_NONE;
> }
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -557,7 +557,22 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
> static RISCVException read_misa(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> - *val = env->misa;
> + target_ulong misa;
> +
> + switch (env->misa_mxl) {
> + case MXL_RV32:
> + misa = (target_ulong)MXL_RV32 << 30;
> + break;
> +#ifdef TARGET_RISCV64
> + case MXL_RV64:
> + misa = (target_ulong)MXL_RV64 << 62;
> + break;
> +#endif
> + default:
> + g_assert_not_reached();
> + }
> +
> + *val = misa | env->misa_ext;
> return RISCV_EXCP_NONE;
> }
>
> @@ -583,8 +598,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> + /*
> + * misa.MXL writes are not supported by QEMU.
> + * Drop writes to those bits.
> + */
> +
> /* Mask extensions that are not supported by this hart */
> - val &= env->misa_mask;
> + val &= env->misa_ext_mask;
>
> /* Mask extensions that are not supported by QEMU */
> val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> @@ -601,20 +621,14 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
> val &= ~RVC;
> }
>
> - /* misa.MXL writes are not supported by QEMU */
> - if (riscv_cpu_is_32bit(env)) {
> - val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
> - } else {
> - val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
> + /* If nothing changed, do nothing. */
> + if (val == env->misa_ext) {
> + return RISCV_EXCP_NONE;
> }
>
> /* flush translation cache */
> - if (val != env->misa) {
> - tb_flush(env_cpu(env));
> - }
> -
> - env->misa = val;
> -
> + tb_flush(env_cpu(env));
> + env->misa_ext = val;
> return RISCV_EXCP_NONE;
> }
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index a7a9c0b1fe..5257df0217 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -54,10 +54,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
> {
> if (n < 32) {
> - if (env->misa & RVD) {
> + if (env->misa_ext & RVD) {
> return gdb_get_reg64(buf, env->fpr[n]);
> }
> - if (env->misa & RVF) {
> + if (env->misa_ext & RVF) {
> return gdb_get_reg32(buf, env->fpr[n]);
> }
> /* there is hole between ft11 and fflags in fpu.xml */
> @@ -191,10 +191,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - if (env->misa & RVD) {
> + if (env->misa_ext & RVD) {
> gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> 36, "riscv-64bit-fpu.xml", 0);
> - } else if (env->misa & RVF) {
> + } else if (env->misa_ext & RVF) {
> gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> 36, "riscv-32bit-fpu.xml", 0);
> }
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 16a08302da..f64b2a96c1 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = {
>
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> - .version_id = 2,
> - .minimum_version_id = 2,
> + .version_id = 3,
> + .minimum_version_id = 3,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
> @@ -153,8 +153,10 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
> VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
> VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
> - VMSTATE_UINTTL(env.misa, RISCVCPU),
> - VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
> + VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
> + VMSTATE_UINT32(env.misa_ext, RISCVCPU),
> + VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
> + VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
> VMSTATE_UINT32(env.features, RISCVCPU),
> VMSTATE_UINTTL(env.priv, RISCVCPU),
> VMSTATE_UINTTL(env.virt, RISCVCPU),
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index d2442f0cf5..422f8ab8d0 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -55,7 +55,8 @@ typedef struct DisasContext {
> /* pc_succ_insn points to the instruction following base.pc_next */
> target_ulong pc_succ_insn;
> target_ulong priv_ver;
> - target_ulong misa;
> + RISCVMXL xl;
> + uint32_t misa_ext;
> uint32_t opcode;
> uint32_t mstatus_fs;
> uint32_t mstatus_hs_fs;
> @@ -86,7 +87,7 @@ typedef struct DisasContext {
>
> static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> {
> - return ctx->misa & ext;
> + return ctx->misa_ext & ext;
> }
>
> #ifdef TARGET_RISCV32
> @@ -96,7 +97,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> #else
> static inline bool is_32bit(DisasContext *ctx)
> {
> - return (ctx->misa & RV32) == RV32;
> + return ctx->xl == MXL_RV32;
> }
> #endif
>
> @@ -538,7 +539,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> #else
> ctx->virt_enabled = false;
> #endif
> - ctx->misa = env->misa;
> + ctx->xl = env->misa_mxl;
> + ctx->misa_ext = env->misa_ext;
> ctx->frm = -1; /* unknown rounding mode */
> ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> ctx->vlen = cpu->cfg.vlen;
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
@ 2021-10-14 8:20 ` LIU Zhiwei
2021-10-14 16:12 ` Richard Henderson
2021-10-15 12:37 ` Alistair Francis
1 sibling, 1 reply; 34+ messages in thread
From: LIU Zhiwei @ 2021-10-14 8:20 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 2021/10/14 上午4:50, Richard Henderson wrote:
> Begin adding support for switching XLEN at runtime. Extract the
> effective XLEN from MISA and MSTATUS and store for use during translation.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v2: Force SXL and UXL to valid values.
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu.c | 8 ++++++++
> target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++
> target/riscv/csr.c | 3 +++
> target/riscv/translate.c | 2 +-
> 5 files changed, 47 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 87248b562a..445ba5b395 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -395,6 +395,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
> /* Is a Hypervisor instruction load/store allowed? */
> FIELD(TB_FLAGS, HLSX, 9, 1)
> FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
> +/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
> +FIELD(TB_FLAGS, XL, 12, 2)
>
> #ifdef CONFIG_RISCV32
> #define riscv_cpu_mxl(env) MXL_RV32
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1857670a69..840edd66f8 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -355,6 +355,14 @@ static void riscv_cpu_reset(DeviceState *dev)
> env->misa_mxl = env->misa_mxl_max;
> env->priv = PRV_M;
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> + if (env->misa_mxl > MXL_RV32) {
> + /*
> + * The reset status of SXL/UXL is officially undefined,
> + * but invalid settings would result in a tcg assert.
> + */
> + env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
> + env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
> + }
Can you give more explanation about the assert? As the cpu will always
reset to M mode, I think we can omit the the setting of UXL or SXL.
Thanks,
Zhiwei
> env->mcause = 0;
> env->pc = env->resetvec;
> env->two_stage_lookup = false;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 403f54171d..429afd1f48 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -35,6 +35,37 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
> #endif
> }
>
> +static RISCVMXL cpu_get_xl(CPURISCVState *env)
> +{
> +#if defined(TARGET_RISCV32)
> + return MXL_RV32;
> +#elif defined(CONFIG_USER_ONLY)
> + return MXL_RV64;
> +#else
> + RISCVMXL xl = riscv_cpu_mxl(env);
> +
> + /*
> + * When emulating a 32-bit-only cpu, use RV32.
> + * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
> + * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
> + * back to RV64 for lower privs.
> + */
> + if (xl != MXL_RV32) {
> + switch (env->priv) {
> + case PRV_M:
> + break;
> + case PRV_U:
> + xl = get_field(env->mstatus, MSTATUS64_UXL);
> + break;
> + default: /* PRV_S | PRV_H */
> + xl = get_field(env->mstatus, MSTATUS64_SXL);
> + break;
> + }
> + }
> + return xl;
> +#endif
> +}
> +
> void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> target_ulong *cs_base, uint32_t *pflags)
> {
> @@ -78,6 +109,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> }
> #endif
>
> + flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
> +
> *pflags = flags;
> }
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9c0753bc8b..c4a479ddd2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -526,6 +526,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
> } else {
> mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
> + /* SXL and UXL fields are for now read only */
> + mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
> + mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
> }
> env->mstatus = mstatus;
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 422f8ab8d0..7e7bb67d15 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -539,7 +539,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> #else
> ctx->virt_enabled = false;
> #endif
> - ctx->xl = env->misa_mxl;
> ctx->misa_ext = env->misa_ext;
> ctx->frm = -1; /* unknown rounding mode */
> ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> @@ -551,6 +550,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
> ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> + ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> ctx->cs = cs;
> ctx->w = false;
> ctx->ntemp = 0;
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
2021-10-13 20:50 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
@ 2021-10-14 8:26 ` LIU Zhiwei
2021-10-15 5:11 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: LIU Zhiwei @ 2021-10-14 8:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 2021/10/14 上午4:50, Richard Henderson wrote:
> In preparation for RV128, replace a simple predicate
> with a more versatile test.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Zhiwei
> ---
> target/riscv/translate.c | 32 +++++++++++++++++---------------
> 1 file changed, 17 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 7e7bb67d15..5724a62bb0 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -91,16 +91,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> }
>
> #ifdef TARGET_RISCV32
> -# define is_32bit(ctx) true
> +#define get_xl(ctx) MXL_RV32
> #elif defined(CONFIG_USER_ONLY)
> -# define is_32bit(ctx) false
> +#define get_xl(ctx) MXL_RV64
> #else
> -static inline bool is_32bit(DisasContext *ctx)
> -{
> - return ctx->xl == MXL_RV32;
> -}
> +#define get_xl(ctx) ((ctx)->xl)
> #endif
>
> +static inline int get_xlen(DisasContext *ctx)
> +{
> + return 16 << get_xl(ctx);
> +}
> +
> /* The word size for this operation. */
> static inline int oper_len(DisasContext *ctx)
> {
> @@ -282,7 +284,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
> static void mark_fs_dirty(DisasContext *ctx)
> {
> TCGv tmp;
> - target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
> + target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
>
> if (ctx->mstatus_fs != MSTATUS_FS) {
> /* Remember the state change for the rest of the TB. */
> @@ -341,16 +343,16 @@ EX_SH(12)
> } \
> } while (0)
>
> -#define REQUIRE_32BIT(ctx) do { \
> - if (!is_32bit(ctx)) { \
> - return false; \
> - } \
> +#define REQUIRE_32BIT(ctx) do { \
> + if (get_xl(ctx) != MXL_RV32) { \
> + return false; \
> + } \
> } while (0)
>
> -#define REQUIRE_64BIT(ctx) do { \
> - if (is_32bit(ctx)) { \
> - return false; \
> - } \
> +#define REQUIRE_64BIT(ctx) do { \
> + if (get_xl(ctx) < MXL_RV64) { \
> + return false; \
> + } \
> } while (0)
>
> static int ex_rvc_register(DisasContext *ctx, int reg)
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
@ 2021-10-14 8:40 ` LIU Zhiwei
2021-10-14 8:57 ` Frédéric Pétrot
2021-10-15 5:19 ` Alistair Francis
1 sibling, 1 reply; 34+ messages in thread
From: LIU Zhiwei @ 2021-10-14 8:40 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 2021/10/14 上午4:51, Richard Henderson wrote:
> In preparation for RV128, consider more than just "w" for
> operand size modification. This will be used for the "d"
> insns from RV128 as well.
>
> Rename oper_len to get_olen to better match get_xlen.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/translate.c | 71 ++++++++++++++++---------
> target/riscv/insn_trans/trans_rvb.c.inc | 8 +--
> target/riscv/insn_trans/trans_rvi.c.inc | 18 +++----
> target/riscv/insn_trans/trans_rvm.c.inc | 10 ++--
> 4 files changed, 63 insertions(+), 44 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5724a62bb0..6ab5c6aa58 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -67,7 +67,7 @@ typedef struct DisasContext {
> to any system register, which includes CSR_FRM, so we do not have
> to reset this known value. */
> int frm;
> - bool w;
> + RISCVMXL ol;
Why not directly use the xl?
Thanks,
Zhiwei
> bool virt_enabled;
> bool ext_ifencei;
> bool hlsx;
> @@ -103,12 +103,17 @@ static inline int get_xlen(DisasContext *ctx)
> return 16 << get_xl(ctx);
> }
>
> -/* The word size for this operation. */
> -static inline int oper_len(DisasContext *ctx)
> -{
> - return ctx->w ? 32 : TARGET_LONG_BITS;
> -}
> +/* The operation length, as opposed to the xlen. */
> +#ifdef TARGET_RISCV32
> +#define get_ol(ctx) MXL_RV32
> +#else
> +#define get_ol(ctx) ((ctx)->ol)
> +#endif
>
> +static inline int get_olen(DisasContext *ctx)
> +{
> + return 16 << get_ol(ctx);
> +}
>
> /*
> * RISC-V requires NaN-boxing of narrower width floating point values.
> @@ -221,24 +226,34 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
> return ctx->zero;
> }
>
> - switch (ctx->w ? ext : EXT_NONE) {
> - case EXT_NONE:
> - return cpu_gpr[reg_num];
> - case EXT_SIGN:
> - t = temp_new(ctx);
> - tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
> - return t;
> - case EXT_ZERO:
> - t = temp_new(ctx);
> - tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
> - return t;
> + switch (get_ol(ctx)) {
> + case MXL_RV32:
> + switch (ext) {
> + case EXT_NONE:
> + break;
> + case EXT_SIGN:
> + t = temp_new(ctx);
> + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
> + return t;
> + case EXT_ZERO:
> + t = temp_new(ctx);
> + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
> + return t;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> + case MXL_RV64:
> + break;
> + default:
> + g_assert_not_reached();
> }
> - g_assert_not_reached();
> + return cpu_gpr[reg_num];
> }
>
> static TCGv dest_gpr(DisasContext *ctx, int reg_num)
> {
> - if (reg_num == 0 || ctx->w) {
> + if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
> return temp_new(ctx);
> }
> return cpu_gpr[reg_num];
> @@ -247,10 +262,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
> static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
> {
> if (reg_num != 0) {
> - if (ctx->w) {
> + switch (get_ol(ctx)) {
> + case MXL_RV32:
> tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
> - } else {
> + break;
> + case MXL_RV64:
> tcg_gen_mov_tl(cpu_gpr[reg_num], t);
> + break;
> + default:
> + g_assert_not_reached();
> }
> }
> }
> @@ -411,7 +431,7 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
> void (*func)(TCGv, TCGv, target_long))
> {
> TCGv dest, src1;
> - int max_len = oper_len(ctx);
> + int max_len = get_olen(ctx);
>
> if (a->shamt >= max_len) {
> return false;
> @@ -430,7 +450,7 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
> void (*func)(TCGv, TCGv, TCGv))
> {
> TCGv dest, src1, src2;
> - int max_len = oper_len(ctx);
> + int max_len = get_olen(ctx);
>
> if (a->shamt >= max_len) {
> return false;
> @@ -454,7 +474,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
> TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> TCGv ext2 = tcg_temp_new();
>
> - tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
> + tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
> func(dest, src1, ext2);
>
> gen_set_gpr(ctx, a->rd, dest);
> @@ -554,7 +574,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> ctx->cs = cs;
> - ctx->w = false;
> ctx->ntemp = 0;
> memset(ctx->temp, 0, sizeof(ctx->temp));
>
> @@ -578,9 +597,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> CPURISCVState *env = cpu->env_ptr;
> uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
>
> + ctx->ol = ctx->xl;
> decode_opc(env, ctx, opcode16);
> ctx->base.pc_next = ctx->pc_succ_insn;
> - ctx->w = false;
>
> for (int i = ctx->ntemp - 1; i >= 0; --i) {
> tcg_temp_free(ctx->temp[i]);
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 185c3e9a60..66dd51de49 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -341,7 +341,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBB(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
> }
>
> @@ -367,7 +367,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBB(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, gen_rorw);
> }
>
> @@ -375,7 +375,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBB(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
> }
>
> @@ -401,7 +401,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBB(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, gen_rolw);
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 920ae0edb3..c0a46d823f 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -333,14 +333,14 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
> static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
> }
>
> static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
> }
>
> @@ -352,7 +352,7 @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
> static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
> }
>
> @@ -364,42 +364,42 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
> static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
> }
>
> static bool trans_addw(DisasContext *ctx, arg_addw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
> }
>
> static bool trans_subw(DisasContext *ctx, arg_subw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
> }
>
> static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
> }
>
> static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
> }
>
> static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
> index b89a85ad3a..9a1fe3c799 100644
> --- a/target/riscv/insn_trans/trans_rvm.c.inc
> +++ b/target/riscv/insn_trans/trans_rvm.c.inc
> @@ -214,7 +214,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
> }
>
> @@ -222,7 +222,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_SIGN, gen_div);
> }
>
> @@ -230,7 +230,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_ZERO, gen_divu);
> }
>
> @@ -238,7 +238,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_SIGN, gen_rem);
> }
>
> @@ -246,6 +246,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_ZERO, gen_remu);
> }
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
2021-10-14 8:40 ` LIU Zhiwei
@ 2021-10-14 8:57 ` Frédéric Pétrot
2021-10-14 15:39 ` Richard Henderson
0 siblings, 1 reply; 34+ messages in thread
From: Frédéric Pétrot @ 2021-10-14 8:57 UTC (permalink / raw)
To: LIU Zhiwei, Richard Henderson, qemu-devel
Cc: alistair.francis, qemu-riscv, fabien.portas
Hi,
Le 14/10/2021 à 10:40, LIU Zhiwei a écrit :
>
> On 2021/10/14 上午4:51, Richard Henderson wrote:
>> In preparation for RV128, consider more than just "w" for
>> operand size modification. This will be used for the "d"
>> insns from RV128 as well.
>>
>> Rename oper_len to get_olen to better match get_xlen.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/riscv/translate.c | 71 ++++++++++++++++---------
>> target/riscv/insn_trans/trans_rvb.c.inc | 8 +--
>> target/riscv/insn_trans/trans_rvi.c.inc | 18 +++----
>> target/riscv/insn_trans/trans_rvm.c.inc | 10 ++--
>> 4 files changed, 63 insertions(+), 44 deletions(-)
>>
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index 5724a62bb0..6ab5c6aa58 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -67,7 +67,7 @@ typedef struct DisasContext {
>> to any system register, which includes CSR_FRM, so we do not have
>> to reset this known value. */
>> int frm;
>> - bool w;
>> + RISCVMXL ol;
>
> Why not directly use the xl?
Hi Zhiwei,
I am not speaking for Richard, but my understanding is that 'ol' is linked to
the instruction being translated, suffixed by 'w' in rv64 and 'w' and 'd' in
rv128, while 'xl' is the value in mstatus (or misa) depending on the register
size of the current execution (mxl, sxl, uxl).
Note that the spec says that the insns results should be sign-extended to the
maximum mxl size supported by the processor (held in misa_mxl_max, that is
implicitely in tl right now, but that will need to be put into the disas
context in 128-bit).
To summarize, we have the maximum (processor instanciation time) register size
in misa_mxl_max, the current register size in xl, and the current insn size in
ol.
Frédéric
>
> Thanks,
> Zhiwei
>
>> bool virt_enabled;
>> bool ext_ifencei;
>> bool hlsx;
>> @@ -103,12 +103,17 @@ static inline int get_xlen(DisasContext *ctx)
>> return 16 << get_xl(ctx);
>> }
>> -/* The word size for this operation. */
>> -static inline int oper_len(DisasContext *ctx)
>> -{
>> - return ctx->w ? 32 : TARGET_LONG_BITS;
>> -}
>> +/* The operation length, as opposed to the xlen. */
>> +#ifdef TARGET_RISCV32
>> +#define get_ol(ctx) MXL_RV32
>> +#else
>> +#define get_ol(ctx) ((ctx)->ol)
>> +#endif
>> +static inline int get_olen(DisasContext *ctx)
>> +{
>> + return 16 << get_ol(ctx);
>> +}
>> /*
>> * RISC-V requires NaN-boxing of narrower width floating point values.
>> @@ -221,24 +226,34 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num,
>> DisasExtend ext)
>> return ctx->zero;
>> }
>> - switch (ctx->w ? ext : EXT_NONE) {
>> - case EXT_NONE:
>> - return cpu_gpr[reg_num];
>> - case EXT_SIGN:
>> - t = temp_new(ctx);
>> - tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
>> - return t;
>> - case EXT_ZERO:
>> - t = temp_new(ctx);
>> - tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
>> - return t;
>> + switch (get_ol(ctx)) {
>> + case MXL_RV32:
>> + switch (ext) {
>> + case EXT_NONE:
>> + break;
>> + case EXT_SIGN:
>> + t = temp_new(ctx);
>> + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
>> + return t;
>> + case EXT_ZERO:
>> + t = temp_new(ctx);
>> + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
>> + return t;
>> + default:
>> + g_assert_not_reached();
>> + }
>> + break;
>> + case MXL_RV64:
>> + break;
>> + default:
>> + g_assert_not_reached();
>> }
>> - g_assert_not_reached();
>> + return cpu_gpr[reg_num];
>> }
>> static TCGv dest_gpr(DisasContext *ctx, int reg_num)
>> {
>> - if (reg_num == 0 || ctx->w) {
>> + if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
>> return temp_new(ctx);
>> }
>> return cpu_gpr[reg_num];
>> @@ -247,10 +262,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
>> static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
>> {
>> if (reg_num != 0) {
>> - if (ctx->w) {
>> + switch (get_ol(ctx)) {
>> + case MXL_RV32:
>> tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
>> - } else {
>> + break;
>> + case MXL_RV64:
>> tcg_gen_mov_tl(cpu_gpr[reg_num], t);
>> + break;
>> + default:
>> + g_assert_not_reached();
>> }
>> }
>> }
>> @@ -411,7 +431,7 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift
>> *a, DisasExtend ext,
>> void (*func)(TCGv, TCGv, target_long))
>> {
>> TCGv dest, src1;
>> - int max_len = oper_len(ctx);
>> + int max_len = get_olen(ctx);
>> if (a->shamt >= max_len) {
>> return false;
>> @@ -430,7 +450,7 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift
>> *a, DisasExtend ext,
>> void (*func)(TCGv, TCGv, TCGv))
>> {
>> TCGv dest, src1, src2;
>> - int max_len = oper_len(ctx);
>> + int max_len = get_olen(ctx);
>> if (a->shamt >= max_len) {
>> return false;
>> @@ -454,7 +474,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>> DisasExtend ext,
>> TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
>> TCGv ext2 = tcg_temp_new();
>> - tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
>> + tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
>> func(dest, src1, ext2);
>> gen_set_gpr(ctx, a->rd, dest);
>> @@ -554,7 +574,6 @@ static void riscv_tr_init_disas_context(DisasContextBase
>> *dcbase, CPUState *cs)
>> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
>> ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
>> ctx->cs = cs;
>> - ctx->w = false;
>> ctx->ntemp = 0;
>> memset(ctx->temp, 0, sizeof(ctx->temp));
>> @@ -578,9 +597,9 @@ static void riscv_tr_translate_insn(DisasContextBase
>> *dcbase, CPUState *cpu)
>> CPURISCVState *env = cpu->env_ptr;
>> uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
>> + ctx->ol = ctx->xl;
>> decode_opc(env, ctx, opcode16);
>> ctx->base.pc_next = ctx->pc_succ_insn;
>> - ctx->w = false;
>> for (int i = ctx->ntemp - 1; i >= 0; --i) {
>> tcg_temp_free(ctx->temp[i]);
>> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
>> b/target/riscv/insn_trans/trans_rvb.c.inc
>> index 185c3e9a60..66dd51de49 100644
>> --- a/target/riscv/insn_trans/trans_rvb.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
>> @@ -341,7 +341,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> REQUIRE_ZBB(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
>> }
>> @@ -367,7 +367,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> REQUIRE_ZBB(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_shift(ctx, a, EXT_NONE, gen_rorw);
>> }
>> @@ -375,7 +375,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> REQUIRE_ZBB(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
>> }
>> @@ -401,7 +401,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> REQUIRE_ZBB(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_shift(ctx, a, EXT_NONE, gen_rolw);
>> }
>> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
>> b/target/riscv/insn_trans/trans_rvi.c.inc
>> index 920ae0edb3..c0a46d823f 100644
>> --- a/target/riscv/insn_trans/trans_rvi.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
>> @@ -333,14 +333,14 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
>> static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
>> }
>> static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
>> }
>> @@ -352,7 +352,7 @@ static void gen_srliw(TCGv dst, TCGv src, target_long
>> shamt)
>> static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
>> }
>> @@ -364,42 +364,42 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long
>> shamt)
>> static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
>> }
>> static bool trans_addw(DisasContext *ctx, arg_addw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
>> }
>> static bool trans_subw(DisasContext *ctx, arg_subw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
>> }
>> static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
>> }
>> static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
>> }
>> static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
>> }
>> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc
>> b/target/riscv/insn_trans/trans_rvm.c.inc
>> index b89a85ad3a..9a1fe3c799 100644
>> --- a/target/riscv/insn_trans/trans_rvm.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvm.c.inc
>> @@ -214,7 +214,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> REQUIRE_EXT(ctx, RVM);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
>> }
>> @@ -222,7 +222,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> REQUIRE_EXT(ctx, RVM);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_arith(ctx, a, EXT_SIGN, gen_div);
>> }
>> @@ -230,7 +230,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> REQUIRE_EXT(ctx, RVM);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_arith(ctx, a, EXT_ZERO, gen_divu);
>> }
>> @@ -238,7 +238,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> REQUIRE_EXT(ctx, RVM);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_arith(ctx, a, EXT_SIGN, gen_rem);
>> }
>> @@ -246,6 +246,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
>> {
>> REQUIRE_64BIT(ctx);
>> REQUIRE_EXT(ctx, RVM);
>> - ctx->w = true;
>> + ctx->ol = MXL_RV32;
>> return gen_arith(ctx, a, EXT_ZERO, gen_remu);
>> }
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
2021-10-14 8:57 ` Frédéric Pétrot
@ 2021-10-14 15:39 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-14 15:39 UTC (permalink / raw)
To: Frédéric Pétrot, LIU Zhiwei, qemu-devel
Cc: alistair.francis, qemu-riscv, fabien.portas
On 10/14/21 1:57 AM, Frédéric Pétrot wrote:
>>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>>> index 5724a62bb0..6ab5c6aa58 100644
>>> --- a/target/riscv/translate.c
>>> +++ b/target/riscv/translate.c
>>> @@ -67,7 +67,7 @@ typedef struct DisasContext {
>>> to any system register, which includes CSR_FRM, so we do not have
>>> to reset this known value. */
>>> int frm;
>>> - bool w;
>>> + RISCVMXL ol;
>>
>> Why not directly use the xl?
>
> Hi Zhiwei,
>
> I am not speaking for Richard, but my understanding is that 'ol' is linked to
> the instruction being translated, suffixed by 'w' in rv64 and 'w' and 'd' in
> rv128, while 'xl' is the value in mstatus (or misa) depending on the register
> size of the current execution (mxl, sxl, uxl).
Correct.
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext
2021-10-14 7:52 ` LIU Zhiwei
@ 2021-10-14 15:52 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-14 15:52 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 10/14/21 12:52 AM, LIU Zhiwei wrote:
>> @@ -360,6 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev)
>> mcc->parent_reset(dev);
>> #ifndef CONFIG_USER_ONLY
>> + env->misa_mxl = env->misa_mxl_max;
>
> As we have set misa_mxl in cpu_init_fn, why set it again here?
I guess we could drop this for now, but we'd need to add it back as soon as we can modify
MXL in write_misa, as this is part of the reset spec.
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-14 7:08 ` LIU Zhiwei
@ 2021-10-14 16:01 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-14 16:01 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 10/14/21 12:08 AM, LIU Zhiwei wrote:
>
> On 2021/10/14 上午4:50, Richard Henderson wrote:
>> Shortly, the set of supported XL will not be just 32 and 64,
>> and representing that properly using the enumeration will be
>> imperative.
>>
>> Two places, booting and gdb, intentionally use misa_mxl_max
>> to emphasize the use of the reset value of misa.mxl, and not
>> the current cpu state.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/riscv/cpu.h | 9 ++++++++-
>> hw/riscv/boot.c | 2 +-
>> semihosting/arm-compat-semi.c | 2 +-
>> target/riscv/cpu.c | 24 ++++++++++++++----------
>> target/riscv/cpu_helper.c | 12 ++++++------
>> target/riscv/csr.c | 24 ++++++++++++------------
>> target/riscv/gdbstub.c | 2 +-
>> target/riscv/monitor.c | 4 ++--
>> 8 files changed, 45 insertions(+), 34 deletions(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index e708fcc168..87248b562a 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1)
>> FIELD(TB_FLAGS, HLSX, 9, 1)
>> FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
>> -bool riscv_cpu_is_32bit(CPURISCVState *env);
>> +#ifdef CONFIG_RISCV32
>> +#define riscv_cpu_mxl(env) MXL_RV32
>> +#else
>> +static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
>> +{
>> + return env->misa_mxl;
>> +}
>> +#endif
>
> Hi Richard,
>
> I don't know why we use CONFIG_RISCV32 here. I looked through the target source code. It
> doesn't use this macro before.
Typo, should be TARGET_RISCV32.
But the reason to have the ifdef is so that riscv_cpu_mxl becomes a constant and the
compiler can fold away more code.
>> bool riscv_is_32bit(RISCVHartArrayState *harts)
>> {
>> - return riscv_cpu_is_32bit(&harts->harts[0].env);
>> + return harts->harts[0].env.misa_mxl_max == MXL_RV32;
>
> Why not use misa_mxl here? As this is just a replacement of riscv_cpu_is_32bit like
> many other places.
It isn't clear to me that all uses of this are at boot time. Once MXL may be changed at
runtime, that (potentially) changes this test, and it seems unlikely that the board would
really change based on the current status of the cpu.
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
2021-10-14 8:20 ` LIU Zhiwei
@ 2021-10-14 16:12 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2021-10-14 16:12 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: alistair.francis, frederic.petrot, qemu-riscv, fabien.portas
On 10/14/21 1:20 AM, LIU Zhiwei wrote:
>
> On 2021/10/14 上午4:50, Richard Henderson wrote:
>> Begin adding support for switching XLEN at runtime. Extract the
>> effective XLEN from MISA and MSTATUS and store for use during translation.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> v2: Force SXL and UXL to valid values.
>> ---
>> target/riscv/cpu.h | 2 ++
>> target/riscv/cpu.c | 8 ++++++++
>> target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++
>> target/riscv/csr.c | 3 +++
>> target/riscv/translate.c | 2 +-
>> 5 files changed, 47 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 87248b562a..445ba5b395 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -395,6 +395,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
>> /* Is a Hypervisor instruction load/store allowed? */
>> FIELD(TB_FLAGS, HLSX, 9, 1)
>> FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
>> +/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
>> +FIELD(TB_FLAGS, XL, 12, 2)
>> #ifdef CONFIG_RISCV32
>> #define riscv_cpu_mxl(env) MXL_RV32
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 1857670a69..840edd66f8 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -355,6 +355,14 @@ static void riscv_cpu_reset(DeviceState *dev)
>> env->misa_mxl = env->misa_mxl_max;
>> env->priv = PRV_M;
>> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
>> + if (env->misa_mxl > MXL_RV32) {
>> + /*
>> + * The reset status of SXL/UXL is officially undefined,
>> + * but invalid settings would result in a tcg assert.
>> + */
>> + env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
>> + env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
>> + }
>
> Can you give more explanation about the assert? As the cpu will always reset to M mode, I
> think we can omit the the setting of UXL or SXL.
The mstatus csr is WARL, which means that we should always be able to read a valid value.
On init, these fields will still be 0, which isn't right.
I guess the assert that I was considering can't really happen, because we'd need to write
to mstatus to exit M-mode, and write_mstatus will force these fields to the correct value
(as found by Frederic).
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-14 7:52 ` LIU Zhiwei
@ 2021-10-15 5:01 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-10-15 5:01 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis, Fabien Portas, Frédéric Pétrot,
liuzhiwei
On Thu, Oct 14, 2021 at 6:51 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The hw representation of misa.mxl is at the high bits of the
> misa csr. Representing this in the same way inside QEMU
> results in overly complex code trying to check that field.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> v2: Reset misa.mxl.
> ---
> target/riscv/cpu.h | 15 +++----
> linux-user/elfload.c | 2 +-
> linux-user/riscv/cpu_loop.c | 2 +-
> target/riscv/cpu.c | 78 +++++++++++++++++++++----------------
> target/riscv/csr.c | 44 ++++++++++++++-------
> target/riscv/gdbstub.c | 8 ++--
> target/riscv/machine.c | 10 +++--
> target/riscv/translate.c | 10 +++--
> 8 files changed, 100 insertions(+), 69 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7084efc452..e708fcc168 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -25,6 +25,7 @@
> #include "exec/cpu-defs.h"
> #include "fpu/softfloat-types.h"
> #include "qom/object.h"
> +#include "cpu_bits.h"
>
> #define TCG_GUEST_DEFAULT_MO 0
>
> @@ -51,9 +52,6 @@
> # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
> #endif
>
> -#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
> -#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> -
> #define RV(x) ((target_ulong)1 << (x - 'A'))
>
> #define RVI RV('I')
> @@ -133,8 +131,12 @@ struct CPURISCVState {
> target_ulong priv_ver;
> target_ulong bext_ver;
> target_ulong vext_ver;
> - target_ulong misa;
> - target_ulong misa_mask;
> +
> + /* RISCVMXL, but uint32_t for vmstate migration */
> + uint32_t misa_mxl; /* current mxl */
> + uint32_t misa_mxl_max; /* max mxl for this cpu */
> + uint32_t misa_ext; /* current extensions */
> + uint32_t misa_ext_mask; /* max ext for this cpu */
>
> uint32_t features;
>
> @@ -313,7 +315,7 @@ struct RISCVCPU {
>
> static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
> {
> - return (env->misa & ext) != 0;
> + return (env->misa_ext & ext) != 0;
> }
>
> static inline bool riscv_feature(CPURISCVState *env, int feature)
> @@ -322,7 +324,6 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
> }
>
> #include "cpu_user.h"
> -#include "cpu_bits.h"
>
> extern const char * const riscv_int_regnames[];
> extern const char * const riscv_fpr_regnames[];
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 2404d482ba..214c1aa40d 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1448,7 +1448,7 @@ static uint32_t get_elf_hwcap(void)
> uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
> | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
>
> - return cpu->env.misa & mask;
> + return cpu->env.misa_ext & mask;
> #undef MISA_BIT
> }
>
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 9859a366e4..e5bb6d908a 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -133,7 +133,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
> env->gpr[xSP] = regs->sp;
> env->elf_flags = info->elf_flags;
>
> - if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
> + if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
> error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
> exit(EXIT_FAILURE);
> }
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1d69d1887e..fdf031a394 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -110,16 +110,13 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
>
> bool riscv_cpu_is_32bit(CPURISCVState *env)
> {
> - if (env->misa & RV64) {
> - return false;
> - }
> -
> - return true;
> + return env->misa_mxl == MXL_RV32;
> }
>
> -static void set_misa(CPURISCVState *env, target_ulong misa)
> +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
> {
> - env->misa_mask = env->misa = misa;
> + env->misa_mxl_max = env->misa_mxl = mxl;
> + env->misa_ext_mask = env->misa_ext = ext;
> }
>
> static void set_priv_version(CPURISCVState *env, int priv_ver)
> @@ -148,9 +145,9 @@ static void riscv_any_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> #if defined(TARGET_RISCV32)
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> #elif defined(TARGET_RISCV64)
> - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> #endif
> set_priv_version(env, PRIV_VERSION_1_11_0);
> }
> @@ -160,20 +157,20 @@ static void rv64_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> - set_misa(env, RV64);
> + set_misa(env, MXL_RV64, 0);
> }
>
> static void rv64_sifive_u_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> }
>
> static void rv64_sifive_e_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
> + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
> @@ -182,20 +179,20 @@ static void rv32_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> - set_misa(env, RV32);
> + set_misa(env, MXL_RV32, 0);
> }
>
> static void rv32_sifive_u_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> }
>
> static void rv32_sifive_e_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
> @@ -203,7 +200,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
> static void rv32_ibex_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
> @@ -212,7 +209,7 @@ static void rv32_ibex_cpu_init(Object *obj)
> static void rv32_imafcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
> + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> set_resetvec(env, DEFAULT_RSTVEC);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> @@ -360,6 +357,7 @@ static void riscv_cpu_reset(DeviceState *dev)
>
> mcc->parent_reset(dev);
> #ifndef CONFIG_USER_ONLY
> + env->misa_mxl = env->misa_mxl_max;
> env->priv = PRV_M;
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> env->mcause = 0;
> @@ -388,7 +386,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> CPURISCVState *env = &cpu->env;
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> int priv_version = 0;
> - target_ulong target_misa = env->misa;
> Error *local_err = NULL;
>
> cpu_exec_realizefn(cs, &local_err);
> @@ -434,8 +431,23 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>
> set_resetvec(env, cpu->cfg.resetvec);
>
> - /* If only XLEN is set for misa, then set misa from properties */
> - if (env->misa == RV32 || env->misa == RV64) {
> + /* Validate that MISA_MXL is set properly. */
> + switch (env->misa_mxl_max) {
> +#ifdef TARGET_RISCV64
> + case MXL_RV64:
> + break;
> +#endif
> + case MXL_RV32:
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + assert(env->misa_mxl_max == env->misa_mxl);
> +
> + /* If only MISA_EXT is unset for misa, then set it from properties */
> + if (env->misa_ext == 0) {
> + uint32_t ext = 0;
> +
> /* Do some ISA extension error checking */
> if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
> error_setg(errp,
> @@ -462,38 +474,38 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>
> /* Set the ISA extensions, checks should have happened above */
> if (cpu->cfg.ext_i) {
> - target_misa |= RVI;
> + ext |= RVI;
> }
> if (cpu->cfg.ext_e) {
> - target_misa |= RVE;
> + ext |= RVE;
> }
> if (cpu->cfg.ext_m) {
> - target_misa |= RVM;
> + ext |= RVM;
> }
> if (cpu->cfg.ext_a) {
> - target_misa |= RVA;
> + ext |= RVA;
> }
> if (cpu->cfg.ext_f) {
> - target_misa |= RVF;
> + ext |= RVF;
> }
> if (cpu->cfg.ext_d) {
> - target_misa |= RVD;
> + ext |= RVD;
> }
> if (cpu->cfg.ext_c) {
> - target_misa |= RVC;
> + ext |= RVC;
> }
> if (cpu->cfg.ext_s) {
> - target_misa |= RVS;
> + ext |= RVS;
> }
> if (cpu->cfg.ext_u) {
> - target_misa |= RVU;
> + ext |= RVU;
> }
> if (cpu->cfg.ext_h) {
> - target_misa |= RVH;
> + ext |= RVH;
> }
> if (cpu->cfg.ext_v) {
> int vext_version = VEXT_VERSION_0_07_1;
> - target_misa |= RVV;
> + ext |= RVV;
> if (!is_power_of_2(cpu->cfg.vlen)) {
> error_setg(errp,
> "Vector extension VLEN must be power of 2");
> @@ -532,7 +544,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> set_vext_version(env, vext_version);
> }
>
> - set_misa(env, target_misa);
> + set_misa(env, env->misa_mxl, ext);
> }
>
> riscv_cpu_register_gdb_regs_for_features(cs);
> @@ -705,7 +717,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> char *isa_str = g_new(char, maxlen);
> char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> for (i = 0; i < sizeof(riscv_exts); i++) {
> - if (cpu->env.misa & RV(riscv_exts[i])) {
> + if (cpu->env.misa_ext & RV(riscv_exts[i])) {
> *p++ = qemu_tolower(riscv_exts[i]);
> }
> }
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 23fbbd3216..d0c86a300d 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -39,7 +39,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
> {
> #if !defined(CONFIG_USER_ONLY)
> /* loose check condition for fcsr in vector extension */
> - if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
> + if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
> return RISCV_EXCP_NONE;
> }
> if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> @@ -51,7 +51,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
>
> static RISCVException vs(CPURISCVState *env, int csrno)
> {
> - if (env->misa & RVV) {
> + if (env->misa_ext & RVV) {
> return RISCV_EXCP_NONE;
> }
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -557,7 +557,22 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
> static RISCVException read_misa(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> - *val = env->misa;
> + target_ulong misa;
> +
> + switch (env->misa_mxl) {
> + case MXL_RV32:
> + misa = (target_ulong)MXL_RV32 << 30;
> + break;
> +#ifdef TARGET_RISCV64
> + case MXL_RV64:
> + misa = (target_ulong)MXL_RV64 << 62;
> + break;
> +#endif
> + default:
> + g_assert_not_reached();
> + }
> +
> + *val = misa | env->misa_ext;
> return RISCV_EXCP_NONE;
> }
>
> @@ -583,8 +598,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> + /*
> + * misa.MXL writes are not supported by QEMU.
> + * Drop writes to those bits.
> + */
> +
> /* Mask extensions that are not supported by this hart */
> - val &= env->misa_mask;
> + val &= env->misa_ext_mask;
>
> /* Mask extensions that are not supported by QEMU */
> val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> @@ -601,20 +621,14 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
> val &= ~RVC;
> }
>
> - /* misa.MXL writes are not supported by QEMU */
> - if (riscv_cpu_is_32bit(env)) {
> - val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
> - } else {
> - val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
> + /* If nothing changed, do nothing. */
> + if (val == env->misa_ext) {
> + return RISCV_EXCP_NONE;
> }
>
> /* flush translation cache */
> - if (val != env->misa) {
> - tb_flush(env_cpu(env));
> - }
> -
> - env->misa = val;
> -
> + tb_flush(env_cpu(env));
> + env->misa_ext = val;
> return RISCV_EXCP_NONE;
> }
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index a7a9c0b1fe..5257df0217 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -54,10 +54,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
> {
> if (n < 32) {
> - if (env->misa & RVD) {
> + if (env->misa_ext & RVD) {
> return gdb_get_reg64(buf, env->fpr[n]);
> }
> - if (env->misa & RVF) {
> + if (env->misa_ext & RVF) {
> return gdb_get_reg32(buf, env->fpr[n]);
> }
> /* there is hole between ft11 and fflags in fpu.xml */
> @@ -191,10 +191,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - if (env->misa & RVD) {
> + if (env->misa_ext & RVD) {
> gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> 36, "riscv-64bit-fpu.xml", 0);
> - } else if (env->misa & RVF) {
> + } else if (env->misa_ext & RVF) {
> gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> 36, "riscv-32bit-fpu.xml", 0);
> }
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 16a08302da..f64b2a96c1 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -140,8 +140,8 @@ static const VMStateDescription vmstate_hyper = {
>
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> - .version_id = 2,
> - .minimum_version_id = 2,
> + .version_id = 3,
> + .minimum_version_id = 3,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
> @@ -153,8 +153,10 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
> VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
> VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
> - VMSTATE_UINTTL(env.misa, RISCVCPU),
> - VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
> + VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
> + VMSTATE_UINT32(env.misa_ext, RISCVCPU),
> + VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
> + VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
> VMSTATE_UINT32(env.features, RISCVCPU),
> VMSTATE_UINTTL(env.priv, RISCVCPU),
> VMSTATE_UINTTL(env.virt, RISCVCPU),
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index d2442f0cf5..422f8ab8d0 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -55,7 +55,8 @@ typedef struct DisasContext {
> /* pc_succ_insn points to the instruction following base.pc_next */
> target_ulong pc_succ_insn;
> target_ulong priv_ver;
> - target_ulong misa;
> + RISCVMXL xl;
> + uint32_t misa_ext;
> uint32_t opcode;
> uint32_t mstatus_fs;
> uint32_t mstatus_hs_fs;
> @@ -86,7 +87,7 @@ typedef struct DisasContext {
>
> static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> {
> - return ctx->misa & ext;
> + return ctx->misa_ext & ext;
> }
>
> #ifdef TARGET_RISCV32
> @@ -96,7 +97,7 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> #else
> static inline bool is_32bit(DisasContext *ctx)
> {
> - return (ctx->misa & RV32) == RV32;
> + return ctx->xl == MXL_RV32;
> }
> #endif
>
> @@ -538,7 +539,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> #else
> ctx->virt_enabled = false;
> #endif
> - ctx->misa = env->misa;
> + ctx->xl = env->misa_mxl;
> + ctx->misa_ext = env->misa_ext;
> ctx->frm = -1; /* unknown rounding mode */
> ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> ctx->vlen = cpu->cfg.vlen;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-14 7:08 ` LIU Zhiwei
@ 2021-10-15 5:05 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-10-15 5:05 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis, Fabien Portas, Frédéric Pétrot,
liuzhiwei
On Thu, Oct 14, 2021 at 6:54 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Shortly, the set of supported XL will not be just 32 and 64,
> and representing that properly using the enumeration will be
> imperative.
>
> Two places, booting and gdb, intentionally use misa_mxl_max
> to emphasize the use of the reset value of misa.mxl, and not
> the current cpu state.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/cpu.h | 9 ++++++++-
> hw/riscv/boot.c | 2 +-
> semihosting/arm-compat-semi.c | 2 +-
> target/riscv/cpu.c | 24 ++++++++++++++----------
> target/riscv/cpu_helper.c | 12 ++++++------
> target/riscv/csr.c | 24 ++++++++++++------------
> target/riscv/gdbstub.c | 2 +-
> target/riscv/monitor.c | 4 ++--
> 8 files changed, 45 insertions(+), 34 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e708fcc168..87248b562a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -396,7 +396,14 @@ FIELD(TB_FLAGS, VILL, 8, 1)
> FIELD(TB_FLAGS, HLSX, 9, 1)
> FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
>
> -bool riscv_cpu_is_32bit(CPURISCVState *env);
> +#ifdef CONFIG_RISCV32
Besides the typo:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-14 5:54 ` LIU Zhiwei
@ 2021-10-15 5:08 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-10-15 5:08 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis, Fabien Portas, Frédéric Pétrot,
liuzhiwei
On Thu, Oct 14, 2021 at 6:57 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use the same REQUIRE_64BIT check that we use elsewhere,
> rather than open-coding the use of is_32bit.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index fa451938f1..bbc5c93ef1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
>
> static bool amo_check64(DisasContext *s, arg_rwdvm* a)
> {
> - return !is_32bit(s) && amo_check(s, a);
> + REQUIRE_64BIT(s);
> + return amo_check(s, a);
> }
>
> GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op
2021-10-13 20:50 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-14 5:55 ` LIU Zhiwei
@ 2021-10-15 5:09 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-10-15 5:09 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis, Fabien Portas, Frédéric Pétrot,
liuzhiwei
On Thu, Oct 14, 2021 at 6:55 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We're currently assuming SEW <= 3, and the "else" from
> the SEW == 3 must be less. Use a switch and explicitly
> bound both SEW and SEQ for all cases.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index bbc5c93ef1..91fca4a2d1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
> gen_helper_exit_atomic(cpu_env);
> s->base.is_jmp = DISAS_NORETURN;
> return true;
> - } else {
> - if (s->sew == 3) {
> - if (!is_32bit(s)) {
> - fn = fnsd[seq];
> - } else {
> - /* Check done in amo_check(). */
> - g_assert_not_reached();
> - }
> - } else {
> - assert(seq < ARRAY_SIZE(fnsw));
> - fn = fnsw[seq];
> - }
> + }
> +
> + switch (s->sew) {
> + case 0 ... 2:
> + assert(seq < ARRAY_SIZE(fnsw));
> + fn = fnsw[seq];
> + break;
> + case 3:
> + /* XLEN check done in amo_check(). */
> + assert(seq < ARRAY_SIZE(fnsd));
> + fn = fnsd[seq];
> + break;
> + default:
> + g_assert_not_reached();
> }
>
> data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
2021-10-13 20:50 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-14 8:26 ` LIU Zhiwei
@ 2021-10-15 5:11 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-10-15 5:11 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis, Fabien Portas, Frédéric Pétrot,
liuzhiwei
On Thu, Oct 14, 2021 at 6:59 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> In preparation for RV128, replace a simple predicate
> with a more versatile test.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 32 +++++++++++++++++---------------
> 1 file changed, 17 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 7e7bb67d15..5724a62bb0 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -91,16 +91,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> }
>
> #ifdef TARGET_RISCV32
> -# define is_32bit(ctx) true
> +#define get_xl(ctx) MXL_RV32
> #elif defined(CONFIG_USER_ONLY)
> -# define is_32bit(ctx) false
> +#define get_xl(ctx) MXL_RV64
> #else
> -static inline bool is_32bit(DisasContext *ctx)
> -{
> - return ctx->xl == MXL_RV32;
> -}
> +#define get_xl(ctx) ((ctx)->xl)
> #endif
>
> +static inline int get_xlen(DisasContext *ctx)
> +{
> + return 16 << get_xl(ctx);
> +}
> +
> /* The word size for this operation. */
> static inline int oper_len(DisasContext *ctx)
> {
> @@ -282,7 +284,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
> static void mark_fs_dirty(DisasContext *ctx)
> {
> TCGv tmp;
> - target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
> + target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
>
> if (ctx->mstatus_fs != MSTATUS_FS) {
> /* Remember the state change for the rest of the TB. */
> @@ -341,16 +343,16 @@ EX_SH(12)
> } \
> } while (0)
>
> -#define REQUIRE_32BIT(ctx) do { \
> - if (!is_32bit(ctx)) { \
> - return false; \
> - } \
> +#define REQUIRE_32BIT(ctx) do { \
> + if (get_xl(ctx) != MXL_RV32) { \
> + return false; \
> + } \
> } while (0)
>
> -#define REQUIRE_64BIT(ctx) do { \
> - if (is_32bit(ctx)) { \
> - return false; \
> - } \
> +#define REQUIRE_64BIT(ctx) do { \
> + if (get_xl(ctx) < MXL_RV64) { \
> + return false; \
> + } \
> } while (0)
>
> static int ex_rvc_register(DisasContext *ctx, int reg)
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-14 8:40 ` LIU Zhiwei
@ 2021-10-15 5:19 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-10-15 5:19 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis, Fabien Portas, Frédéric Pétrot,
liuzhiwei
On Thu, Oct 14, 2021 at 7:03 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> In preparation for RV128, consider more than just "w" for
> operand size modification. This will be used for the "d"
> insns from RV128 as well.
>
> Rename oper_len to get_olen to better match get_xlen.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 71 ++++++++++++++++---------
> target/riscv/insn_trans/trans_rvb.c.inc | 8 +--
> target/riscv/insn_trans/trans_rvi.c.inc | 18 +++----
> target/riscv/insn_trans/trans_rvm.c.inc | 10 ++--
> 4 files changed, 63 insertions(+), 44 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5724a62bb0..6ab5c6aa58 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -67,7 +67,7 @@ typedef struct DisasContext {
> to any system register, which includes CSR_FRM, so we do not have
> to reset this known value. */
> int frm;
> - bool w;
> + RISCVMXL ol;
> bool virt_enabled;
> bool ext_ifencei;
> bool hlsx;
> @@ -103,12 +103,17 @@ static inline int get_xlen(DisasContext *ctx)
> return 16 << get_xl(ctx);
> }
>
> -/* The word size for this operation. */
> -static inline int oper_len(DisasContext *ctx)
> -{
> - return ctx->w ? 32 : TARGET_LONG_BITS;
> -}
> +/* The operation length, as opposed to the xlen. */
> +#ifdef TARGET_RISCV32
> +#define get_ol(ctx) MXL_RV32
> +#else
> +#define get_ol(ctx) ((ctx)->ol)
> +#endif
>
> +static inline int get_olen(DisasContext *ctx)
> +{
> + return 16 << get_ol(ctx);
> +}
>
> /*
> * RISC-V requires NaN-boxing of narrower width floating point values.
> @@ -221,24 +226,34 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
> return ctx->zero;
> }
>
> - switch (ctx->w ? ext : EXT_NONE) {
> - case EXT_NONE:
> - return cpu_gpr[reg_num];
> - case EXT_SIGN:
> - t = temp_new(ctx);
> - tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
> - return t;
> - case EXT_ZERO:
> - t = temp_new(ctx);
> - tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
> - return t;
> + switch (get_ol(ctx)) {
> + case MXL_RV32:
> + switch (ext) {
> + case EXT_NONE:
> + break;
> + case EXT_SIGN:
> + t = temp_new(ctx);
> + tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
> + return t;
> + case EXT_ZERO:
> + t = temp_new(ctx);
> + tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
> + return t;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> + case MXL_RV64:
> + break;
> + default:
> + g_assert_not_reached();
> }
> - g_assert_not_reached();
> + return cpu_gpr[reg_num];
> }
>
> static TCGv dest_gpr(DisasContext *ctx, int reg_num)
> {
> - if (reg_num == 0 || ctx->w) {
> + if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
> return temp_new(ctx);
> }
> return cpu_gpr[reg_num];
> @@ -247,10 +262,15 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
> static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
> {
> if (reg_num != 0) {
> - if (ctx->w) {
> + switch (get_ol(ctx)) {
> + case MXL_RV32:
> tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
> - } else {
> + break;
> + case MXL_RV64:
> tcg_gen_mov_tl(cpu_gpr[reg_num], t);
> + break;
> + default:
> + g_assert_not_reached();
> }
> }
> }
> @@ -411,7 +431,7 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
> void (*func)(TCGv, TCGv, target_long))
> {
> TCGv dest, src1;
> - int max_len = oper_len(ctx);
> + int max_len = get_olen(ctx);
>
> if (a->shamt >= max_len) {
> return false;
> @@ -430,7 +450,7 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
> void (*func)(TCGv, TCGv, TCGv))
> {
> TCGv dest, src1, src2;
> - int max_len = oper_len(ctx);
> + int max_len = get_olen(ctx);
>
> if (a->shamt >= max_len) {
> return false;
> @@ -454,7 +474,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
> TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> TCGv ext2 = tcg_temp_new();
>
> - tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
> + tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
> func(dest, src1, ext2);
>
> gen_set_gpr(ctx, a->rd, dest);
> @@ -554,7 +574,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> ctx->cs = cs;
> - ctx->w = false;
> ctx->ntemp = 0;
> memset(ctx->temp, 0, sizeof(ctx->temp));
>
> @@ -578,9 +597,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> CPURISCVState *env = cpu->env_ptr;
> uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
>
> + ctx->ol = ctx->xl;
> decode_opc(env, ctx, opcode16);
> ctx->base.pc_next = ctx->pc_succ_insn;
> - ctx->w = false;
>
> for (int i = ctx->ntemp - 1; i >= 0; --i) {
> tcg_temp_free(ctx->temp[i]);
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 185c3e9a60..66dd51de49 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -341,7 +341,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBB(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
> }
>
> @@ -367,7 +367,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBB(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, gen_rorw);
> }
>
> @@ -375,7 +375,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBB(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
> }
>
> @@ -401,7 +401,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_ZBB(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, gen_rolw);
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 920ae0edb3..c0a46d823f 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -333,14 +333,14 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
> static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
> }
>
> static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
> }
>
> @@ -352,7 +352,7 @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
> static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
> }
>
> @@ -364,42 +364,42 @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
> static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
> }
>
> static bool trans_addw(DisasContext *ctx, arg_addw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
> }
>
> static bool trans_subw(DisasContext *ctx, arg_subw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
> }
>
> static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
> }
>
> static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
> }
>
> static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
> {
> REQUIRE_64BIT(ctx);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
> index b89a85ad3a..9a1fe3c799 100644
> --- a/target/riscv/insn_trans/trans_rvm.c.inc
> +++ b/target/riscv/insn_trans/trans_rvm.c.inc
> @@ -214,7 +214,7 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
> }
>
> @@ -222,7 +222,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_SIGN, gen_div);
> }
>
> @@ -230,7 +230,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_ZERO, gen_divu);
> }
>
> @@ -238,7 +238,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_SIGN, gen_rem);
> }
>
> @@ -246,6 +246,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
> {
> REQUIRE_64BIT(ctx);
> REQUIRE_EXT(ctx, RVM);
> - ctx->w = true;
> + ctx->ol = MXL_RV32;
> return gen_arith(ctx, a, EXT_ZERO, gen_remu);
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
2021-10-13 20:51 ` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
@ 2021-10-15 5:21 ` Alistair Francis
0 siblings, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-10-15 5:21 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis, Fabien Portas, Frédéric Pétrot,
liuzhiwei
On Thu, Oct 14, 2021 at 7:08 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> When target_long is 64-bit, we still want a 32-bit bswap for rev8.
> Since this opcode is specific to RV32, we need not conditionalize.
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 66dd51de49..c62eea433a 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
> return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
> }
>
> +static void gen_rev8_32(TCGv ret, TCGv src1)
> +{
> + tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
> +}
> +
> static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
> {
> REQUIRE_32BIT(ctx);
> REQUIRE_ZBB(ctx);
> - return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
> + return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
> }
>
> static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-14 8:20 ` LIU Zhiwei
@ 2021-10-15 12:37 ` Alistair Francis
1 sibling, 0 replies; 34+ messages in thread
From: Alistair Francis @ 2021-10-15 12:37 UTC (permalink / raw)
To: Richard Henderson
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis, Fabien Portas, Frédéric Pétrot,
liuzhiwei
On Thu, Oct 14, 2021 at 6:56 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Begin adding support for switching XLEN at runtime. Extract the
> effective XLEN from MISA and MSTATUS and store for use during translation.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> v2: Force SXL and UXL to valid values.
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu.c | 8 ++++++++
> target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++
> target/riscv/csr.c | 3 +++
> target/riscv/translate.c | 2 +-
> 5 files changed, 47 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 87248b562a..445ba5b395 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -395,6 +395,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
> /* Is a Hypervisor instruction load/store allowed? */
> FIELD(TB_FLAGS, HLSX, 9, 1)
> FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
> +/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
> +FIELD(TB_FLAGS, XL, 12, 2)
>
> #ifdef CONFIG_RISCV32
> #define riscv_cpu_mxl(env) MXL_RV32
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1857670a69..840edd66f8 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -355,6 +355,14 @@ static void riscv_cpu_reset(DeviceState *dev)
> env->misa_mxl = env->misa_mxl_max;
> env->priv = PRV_M;
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> + if (env->misa_mxl > MXL_RV32) {
> + /*
> + * The reset status of SXL/UXL is officially undefined,
> + * but invalid settings would result in a tcg assert.
> + */
> + env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
> + env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
> + }
> env->mcause = 0;
> env->pc = env->resetvec;
> env->two_stage_lookup = false;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 403f54171d..429afd1f48 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -35,6 +35,37 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
> #endif
> }
>
> +static RISCVMXL cpu_get_xl(CPURISCVState *env)
> +{
> +#if defined(TARGET_RISCV32)
> + return MXL_RV32;
> +#elif defined(CONFIG_USER_ONLY)
> + return MXL_RV64;
> +#else
> + RISCVMXL xl = riscv_cpu_mxl(env);
> +
> + /*
> + * When emulating a 32-bit-only cpu, use RV32.
> + * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
> + * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
> + * back to RV64 for lower privs.
> + */
> + if (xl != MXL_RV32) {
> + switch (env->priv) {
> + case PRV_M:
> + break;
> + case PRV_U:
> + xl = get_field(env->mstatus, MSTATUS64_UXL);
> + break;
> + default: /* PRV_S | PRV_H */
> + xl = get_field(env->mstatus, MSTATUS64_SXL);
> + break;
> + }
> + }
> + return xl;
> +#endif
> +}
> +
> void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> target_ulong *cs_base, uint32_t *pflags)
> {
> @@ -78,6 +109,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> }
> #endif
>
> + flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
> +
> *pflags = flags;
> }
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9c0753bc8b..c4a479ddd2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -526,6 +526,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
> } else {
> mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
> + /* SXL and UXL fields are for now read only */
> + mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
> + mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
> }
> env->mstatus = mstatus;
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 422f8ab8d0..7e7bb67d15 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -539,7 +539,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> #else
> ctx->virt_enabled = false;
> #endif
> - ctx->xl = env->misa_mxl;
> ctx->misa_ext = env->misa_ext;
> ctx->frm = -1; /* unknown rounding mode */
> ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> @@ -551,6 +550,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
> ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
> ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
> + ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> ctx->cs = cs;
> ctx->w = false;
> ctx->ntemp = 0;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2021-10-15 12:39 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-13 20:50 ` [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-13 20:50 ` [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-14 7:52 ` LIU Zhiwei
2021-10-14 15:52 ` Richard Henderson
2021-10-15 5:01 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-14 7:08 ` LIU Zhiwei
2021-10-14 16:01 ` Richard Henderson
2021-10-15 5:05 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-14 8:20 ` LIU Zhiwei
2021-10-14 16:12 ` Richard Henderson
2021-10-15 12:37 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-14 5:54 ` LIU Zhiwei
2021-10-15 5:08 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-14 5:55 ` LIU Zhiwei
2021-10-15 5:09 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-14 8:26 ` LIU Zhiwei
2021-10-15 5:11 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-14 8:40 ` LIU Zhiwei
2021-10-14 8:57 ` Frédéric Pétrot
2021-10-14 15:39 ` Richard Henderson
2021-10-15 5:19 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-13 20:51 ` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-15 5:21 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-13 20:51 ` [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
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