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From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Andrew Jeffery" <andrew@aj.id.au>,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	"Cédric Le Goater" <clg@kaod.org>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Joel Stanley" <joel@jms.id.au>
Subject: [PATCH v2 5/5] speed/sdhci: Add trace events
Date: Mon, 18 Oct 2021 15:26:09 +0200	[thread overview]
Message-ID: <20211018132609.160008-6-clg@kaod.org> (raw)
In-Reply-To: <20211018132609.160008-1-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/sd/aspeed_sdhci.c | 5 +++++
 hw/sd/trace-events   | 4 ++++
 2 files changed, 9 insertions(+)

diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index 3299844de6dc..df1bdf1fa4ed 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -14,6 +14,7 @@
 #include "hw/irq.h"
 #include "migration/vmstate.h"
 #include "hw/qdev-properties.h"
+#include "trace.h"
 
 #define ASPEED_SDHCI_INFO            0x00
 #define  ASPEED_SDHCI_INFO_SLOT1     (1 << 17)
@@ -60,6 +61,8 @@ static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
         }
     }
 
+    trace_aspeed_sdhci_read(addr, size, (uint64_t) val);
+
     return (uint64_t)val;
 }
 
@@ -68,6 +71,8 @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
 {
     AspeedSDHCIState *sdhci = opaque;
 
+    trace_aspeed_sdhci_write(addr, size, val);
+
     switch (addr) {
     case ASPEED_SDHCI_INFO:
         /* The RESET bit automatically clears. */
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
index 3cc2ef89ba6b..94a00557b26f 100644
--- a/hw/sd/trace-events
+++ b/hw/sd/trace-events
@@ -68,3 +68,7 @@ pl181_fifo_push(uint32_t data) "FIFO push 0x%08" PRIx32
 pl181_fifo_pop(uint32_t data) "FIFO pop 0x%08" PRIx32
 pl181_fifo_transfer_complete(void) "FIFO transfer complete"
 pl181_data_engine_idle(void) "data engine idle"
+
+# aspeed_sdhci.c
+aspeed_sdhci_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
+aspeed_sdhci_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
-- 
2.31.1



  parent reply	other threads:[~2021-10-18 13:41 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-18 13:26 [PATCH v2 0/5] aspeed/smc: Improve support for the alternate boot function Cédric Le Goater
2021-10-18 13:26 ` [PATCH v2 1/5] aspeed/wdt: Introduce a container for the MMIO region Cédric Le Goater
2021-10-20 21:57   ` Philippe Mathieu-Daudé
2021-10-21  7:25   ` Francisco Iglesias
2021-10-18 13:26 ` [PATCH v2 2/5] aspeed: Initialize the watchdog device models before the FMC models Cédric Le Goater
2021-10-20 21:58   ` Philippe Mathieu-Daudé
2021-10-21  7:25   ` Francisco Iglesias
2021-10-18 13:26 ` [PATCH v2 3/5] aspeed/smc: Improve support for the alternate boot function Cédric Le Goater
2021-10-18 13:26 ` [PATCH v2 4/5] aspeed/smc: Use a container for the flash mmio address space Cédric Le Goater
2021-10-20 22:00   ` Philippe Mathieu-Daudé
2021-10-21  7:26   ` Francisco Iglesias
2021-10-18 13:26 ` Cédric Le Goater [this message]
2021-10-20 22:01   ` [PATCH v2 5/5] speed/sdhci: Add trace events Philippe Mathieu-Daudé
2021-10-20 22:34   ` Francisco Iglesias
2021-10-20  4:57 ` [PATCH v2 0/5] aspeed/smc: Improve support for the alternate boot function Peter Delevoryas
2021-10-20  8:26   ` Cédric Le Goater
2021-10-22  6:11     ` Cédric Le Goater
2021-10-22  7:05       ` Peter Delevoryas

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