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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id q9sm2186461ejf.70.2021.10.21.01.43.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Oct 2021 01:43:25 -0700 (PDT) Date: Thu, 21 Oct 2021 10:43:24 +0200 From: Igor Mammedov To: Bin Meng Subject: Re: [PATCH v2 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id Message-ID: <20211021104324.384470d6@redhat.com> In-Reply-To: <20211020014112.7336-5-bmeng.cn@gmail.com> References: <20211020014112.7336-1-bmeng.cn@gmail.com> <20211020014112.7336-5-bmeng.cn@gmail.com> X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.33; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=imammedo@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , qemu-devel@nongnu.org, Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 20 Oct 2021 09:41:10 +0800 Bin Meng wrote: > Using memory_region_init_ram(), which can't possibly handle vhost-user, > and can't work as expected with '-numa node,memdev' options. > > Use MachineState::ram instead of manually initializing RAM memory > region, as well as by providing MachineClass::default_ram_id to > opt in to memdev scheme. > > While at it add check for user supplied RAM size and error out if it > mismatches board expected value. > > Signed-off-by: Bin Meng Reviewed-by: Igor Mammedov > > --- > > Changes in v2: > - add RAM size check > - assign mc->default_ram_size > > hw/riscv/sifive_e.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 6e95ea5896..9b206407a6 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -29,6 +29,7 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/cutils.h" > #include "qemu/error-report.h" > #include "qapi/error.h" > #include "hw/boards.h" > @@ -71,22 +72,27 @@ static const MemMapEntry sifive_e_memmap[] = { > > static void sifive_e_machine_init(MachineState *machine) > { > + MachineClass *mc = MACHINE_GET_CLASS(machine); > const MemMapEntry *memmap = sifive_e_memmap; > > SiFiveEState *s = RISCV_E_MACHINE(machine); > MemoryRegion *sys_mem = get_system_memory(); > - MemoryRegion *main_mem = g_new(MemoryRegion, 1); > int i; > > + if (machine->ram_size != mc->default_ram_size) { > + char *sz = size_to_str(mc->default_ram_size); > + error_report("Invalid RAM size, should be %s", sz); > + g_free(sz); > + exit(EXIT_FAILURE); > + } > + > /* Initialize SoC */ > object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); > qdev_realize(DEVICE(&s->soc), NULL, &error_abort); > > /* Data Tightly Integrated Memory */ > - memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", > - memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal); > memory_region_add_subregion(sys_mem, > - memmap[SIFIVE_E_DEV_DTIM].base, main_mem); > + memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); > > /* Mask ROM reset vector */ > uint32_t reset_vec[4]; > @@ -142,6 +148,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data) > mc->init = sifive_e_machine_init; > mc->max_cpus = 1; > mc->default_cpu_type = SIFIVE_E_CPU; > + mc->default_ram_id = "riscv.sifive.e.ram"; > + mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; > > object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb, > sifive_e_machine_set_revb);