From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: lucas.castro@eldorado.org.br, richard.henderson@linaro.org,
groug@kaod.org, luis.pires@eldorado.org.br,
matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au
Subject: [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree
Date: Thu, 21 Oct 2021 16:45:35 -0300 [thread overview]
Message-ID: <20211021194547.672988-22-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20211021194547.672988-1-matheus.ferst@eldorado.org.br>
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Moved stxv and lxv implementation from the legacy system to
decodetree.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 8 ++++
target/ppc/translate.c | 17 +-------
target/ppc/translate/vsx-impl.c.inc | 60 ++++++++++++++++++++++++++++-
3 files changed, 68 insertions(+), 17 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e438177b32..296d6d6c5a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -28,6 +28,9 @@
%dq_rtp 22:4 !function=times_2
@DQ_rtp ...... ....0 ra:5 ............ .... &D rt=%dq_rtp si=%dq_si
+%dq_rt_tsx 3:1 21:5
+@DQ_TSX ...... ..... ra:5 ............ .... &D si=%dq_si rt=%dq_rt_tsx
+
%ds_si 2:s14 !function=times_4
@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
@@ -385,3 +388,8 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
+
+# VSX Load/Store Instructions
+
+LXV 111101 ..... ..... ............ . 001 @DQ_TSX
+STXV 111101 ..... ..... ............ . 101 @DQ_TSX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d11029d03a..f109830207 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7444,20 +7444,7 @@ static void gen_dform39(DisasContext *ctx)
/* handles stfdp, lxv, stxsd, stxssp lxvx */
static void gen_dform3D(DisasContext *ctx)
{
- if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
- switch (ctx->opcode & 0x7) {
- case 1: /* lxv */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_lxv(ctx);
- }
- break;
- case 5: /* stxv */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_stxv(ctx);
- }
- break;
- }
- } else { /* DS-FORM */
+ if ((ctx->opcode & 3) != 1) { /* DS-FORM */
switch (ctx->opcode & 0x3) {
case 0: /* stfdp */
if (ctx->insns_flags2 & PPC2_ISA205) {
@@ -7582,7 +7569,7 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
#endif
/* handles lfdp, lxsd, lxssp */
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
-/* handles stfdp, lxv, stxsd, stxssp, stxv */
+/* handles stfdp, stxsd, stxssp */
GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 57a7f73bba..dd14be6ee5 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -317,7 +317,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xtl); \
}
-VSX_VECTOR_LOAD(lxv, ld_i64, 0)
VSX_VECTOR_LOAD(lxvx, ld_i64, 1)
#define VSX_VECTOR_STORE(name, op, indexed) \
@@ -370,7 +369,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xtl); \
}
-VSX_VECTOR_STORE(stxv, st_i64, 0)
VSX_VECTOR_STORE(stxvx, st_i64, 1)
#ifdef TARGET_PPC64
@@ -2077,6 +2075,64 @@ static void gen_xvxsigdp(DisasContext *ctx)
tcg_temp_free_i64(xbl);
}
+static bool do_lstxv(DisasContext *ctx, int ra, int displ,
+ int rt, bool store)
+{
+ TCGv ea;
+ TCGv_i64 xt;
+ MemOp mop;
+ int offset;
+
+ ea = tcg_temp_new();
+ xt = tcg_temp_new_i64();
+
+ mop = DEF_MEMOP(MO_Q);
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ do_ea_calc(ctx, ra, tcg_const_tl(displ), ea);
+
+ if (ctx->le_mode) {
+ gen_addr_add(ctx, ea, ea, 8);
+ offset = -8;
+ } else {
+ offset = 8;
+ }
+
+ if (store) {
+ get_cpu_vsrh(xt, rt);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ gen_addr_add(ctx, ea, ea, offset);
+ get_cpu_vsrl(xt, rt);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsrh(rt, xt);
+ gen_addr_add(ctx, ea, ea, offset);
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsrl(rt, xt);
+ }
+
+ tcg_temp_free(ea);
+ tcg_temp_free_i64(xt);
+ return true;
+}
+
+static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+
+ if (a->rt >= 32) {
+ REQUIRE_VSX(ctx);
+ } else {
+ REQUIRE_VECTOR(ctx);
+ }
+
+ return do_lstxv(ctx, a->ra, a->si, a->rt, store);
+}
+
+TRANS(STXV, do_lstxv_D, true)
+TRANS(LXV, do_lstxv_D, false)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.25.1
next prev parent reply other threads:[~2021-10-21 20:15 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-21 19:45 [PATCH 00/33] PowerISA v3.1 instruction batch matheus.ferst
2021-10-21 19:45 ` [PATCH 01/33] target/ppc: introduce do_ea_calc matheus.ferst
2021-10-22 21:51 ` Richard Henderson
2021-10-22 21:57 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 02/33] target/ppc: move resolve_PLS_D to translate.c matheus.ferst
2021-10-22 22:01 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 03/33] target/ppc: Move load and store floating point instructions to decodetree matheus.ferst
2021-10-22 22:19 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 04/33] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions matheus.ferst
2021-10-22 22:24 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 05/33] target/ppc: Move LQ and STQ to decodetree matheus.ferst
2021-10-22 22:53 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 06/33] target/ppc: Implement PLQ and PSTQ matheus.ferst
2021-10-22 22:54 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 07/33] target/ppc: Implement cntlzdm matheus.ferst
2021-10-22 23:16 ` Richard Henderson
2021-10-26 14:33 ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 08/33] target/ppc: Implement cnttzdm matheus.ferst
2021-10-22 23:55 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 09/33] target/ppc: Implement pdepd instruction matheus.ferst
2021-10-23 0:04 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 10/33] target/ppc: Implement pextd instruction matheus.ferst
2021-10-23 0:26 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 11/33] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
2021-10-23 0:31 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 12/33] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
2021-10-23 0:34 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 13/33] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
2021-10-23 0:38 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 14/33] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
2021-10-23 4:07 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 15/33] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
2021-10-23 4:37 ` Richard Henderson
2021-10-23 4:40 ` Richard Henderson
2021-10-23 10:12 ` BALATON Zoltan
2021-10-23 18:36 ` Richard Henderson
2021-10-23 20:02 ` BALATON Zoltan
2021-10-23 20:09 ` Richard Henderson
2021-10-26 14:33 ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
2021-10-23 4:42 ` Richard Henderson
2021-10-26 14:33 ` Matheus K. Ferst
2021-10-26 16:58 ` Richard Henderson
2021-10-26 18:45 ` Paul A. Clarke
2021-10-27 11:49 ` Matheus K. Ferst
2021-10-21 19:45 ` [PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns matheus.ferst
2021-10-23 4:48 ` Richard Henderson
2021-10-23 4:54 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 18/33] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree matheus.ferst
2021-10-23 4:53 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
2021-10-23 20:01 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
2021-10-23 20:10 ` Richard Henderson
2021-10-21 19:45 ` matheus.ferst [this message]
2021-10-23 20:34 ` [PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree Richard Henderson
2021-10-23 20:39 ` Richard Henderson
2021-10-23 20:46 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 22/33] target/ppc: moved stxvx and lxvx " matheus.ferst
2021-10-23 20:38 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 23/33] target/ppc: added the instructions LXVP and STXVP matheus.ferst
2021-10-23 20:48 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 24/33] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
2021-10-23 20:49 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 25/33] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
2021-10-23 20:56 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 26/33] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
2021-10-23 20:57 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 27/33] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
2021-10-23 21:03 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 28/33] target/ppc: moved XXSPLTIB " matheus.ferst
2021-10-23 21:06 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 29/33] target/ppc: implemented XXSPLTI32DX matheus.ferst
2021-10-23 21:12 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 30/33] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
2021-10-23 21:15 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 31/33] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
2021-10-23 21:19 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 32/33] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions matheus.ferst
2021-10-23 21:24 ` Richard Henderson
2021-10-21 19:45 ` [PATCH 33/33] target/ppc: Implement lxvkq instruction matheus.ferst
2021-10-23 21:29 ` Richard Henderson
2021-10-22 2:06 ` [PATCH 00/33] PowerISA v3.1 instruction batch Richard Henderson
2021-10-22 11:13 ` Matheus K. Ferst
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