From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: lucas.castro@eldorado.org.br, richard.henderson@linaro.org,
groug@kaod.org, luis.pires@eldorado.org.br,
Bruno Larsen <bruno.larsen@eldorado.org.br>,
Matheus Ferst <matheus.ferst@eldorado.org.br>,
david@gibson.dropbear.id.au
Subject: [PATCH v3 23/25] target/ppc: Implement xxblendvb/xxblendvh/xxblendvw/xxblendvd instructions
Date: Thu, 4 Nov 2021 09:37:17 -0300 [thread overview]
Message-ID: <20211104123719.323713-24-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20211104123719.323713-1-matheus.ferst@eldorado.org.br>
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 4 +++
target/ppc/insn64.decode | 19 ++++++++++
target/ppc/int_helper.c | 15 ++++++++
target/ppc/translate/vsx-impl.c.inc | 55 +++++++++++++++++++++++++++++
4 files changed, 93 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 7ff1d055c4..627811cefc 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -520,6 +520,10 @@ DEF_HELPER_4(xxpermr, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr)
+DEF_HELPER_5(XXBLENDVB, void, vsr, vsr, vsr, vsr, i32)
+DEF_HELPER_5(XXBLENDVH, void, vsr, vsr, vsr, vsr, i32)
+DEF_HELPER_5(XXBLENDVW, void, vsr, vsr, vsr, vsr, i32)
+DEF_HELPER_5(XXBLENDVD, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 20aa2b4615..39e610913d 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -44,6 +44,16 @@
...... ..... .... . ................ \
&8RR_D si=%8rr_si xt=%8rr_xt
+# Format XX4
+&XX4 xt xa xb xc
+%xx4_xt 0:1 21:5
+%xx4_xa 2:1 16:5
+%xx4_xb 1:1 11:5
+%xx4_xc 3:1 6:5
+@XX4 ........ ........ ........ ........ \
+ ...... ..... ..... ..... ..... .. .... \
+ &XX4 xt=%xx4_xt xa=%xx4_xa xb=%xx4_xb xc=%xx4_xc
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -175,3 +185,12 @@ XXSPLTIW 000001 01 0000 -- -- ................ \
100000 ..... 0011 . ................ @8RR_D
XXSPLTI32DX 000001 01 0000 -- -- ................ \
100000 ..... 000 .. ................ @8RR_D_IX
+
+XXBLENDVD 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 11 .... @XX4
+XXBLENDVW 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 10 .... @XX4
+XXBLENDVH 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 01 .... @XX4
+XXBLENDVB 000001 01 0000 -- ------------------ \
+ 100001 ..... ..... ..... ..... 00 .... @XX4
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b7861776c2..9bc327bcba 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1737,6 +1737,21 @@ void helper_xxinsertw(CPUPPCState *env, ppc_vsr_t *xt,
*xt = t;
}
+#define XXBLEND(name, sz) \
+void glue(helper_XXBLENDV, name)(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
+ ppc_avr_t *c, uint32_t desc) \
+{ \
+ for (int i = 0; i < ARRAY_SIZE(t->glue(u, sz)); i++) { \
+ t->glue(u, sz)[i] = (c->glue(s, sz)[i] >> (sz - 1)) ? \
+ b->glue(u, sz)[i] : a->glue(u, sz)[i]; \
+ } \
+}
+XXBLEND(B, 8)
+XXBLEND(H, 16)
+XXBLEND(W, 32)
+XXBLEND(D, 64)
+#undef XXBLEND
+
#define VEXT_SIGNED(name, element, cast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 180d329f1a..d1de0da877 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2087,6 +2087,61 @@ TRANS64(PLXV, do_lstxv_PLS_D, false, false)
TRANS64(PSTXVP, do_lstxv_PLS_D, true, true)
TRANS64(PLXVP, do_lstxv_PLS_D, false, true)
+static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
+ TCGv_vec c)
+{
+ TCGv_vec tmp = tcg_temp_new_vec_matching(c);
+ tcg_gen_sari_vec(vece, tmp, c, (8 << vece) - 1);
+ tcg_gen_bitsel_vec(vece, t, tmp, b, a);
+ tcg_temp_free_vec(tmp);
+}
+
+static bool do_xxblendv(DisasContext *ctx, arg_XX4 *a, unsigned vece)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_sari_vec, 0
+ };
+ static const GVecGen4 ops[4] = {
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVB,
+ .opt_opc = vecop_list,
+ .vece = MO_8
+ },
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVH,
+ .opt_opc = vecop_list,
+ .vece = MO_16
+ },
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVW,
+ .opt_opc = vecop_list,
+ .vece = MO_32
+ },
+ {
+ .fniv = gen_xxblendv_vec,
+ .fno = gen_helper_XXBLENDVD,
+ .opt_opc = vecop_list,
+ .vece = MO_64
+ }
+ };
+
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_4(vsr_full_offset(a->xt), vsr_full_offset(a->xa),
+ vsr_full_offset(a->xb), vsr_full_offset(a->xc),
+ 16, 16, &ops[vece]);
+
+ return true;
+}
+
+TRANS(XXBLENDVB, do_xxblendv, MO_8)
+TRANS(XXBLENDVH, do_xxblendv, MO_16)
+TRANS(XXBLENDVW, do_xxblendv, MO_32)
+TRANS(XXBLENDVD, do_xxblendv, MO_64)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.25.1
next prev parent reply other threads:[~2021-11-04 13:01 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-04 12:36 [PATCH v3 00/25] PowerISA v3.1 instruction batch matheus.ferst
2021-11-04 12:36 ` [PATCH v3 01/25] target/ppc: Move vcfuged to vmx-impl.c.inc matheus.ferst
2021-11-04 12:36 ` [PATCH v3 02/25] target/ppc: Implement vclzdm/vctzdm instructions matheus.ferst
2021-11-04 12:36 ` [PATCH v3 03/25] target/ppc: Implement vpdepd/vpextd instruction matheus.ferst
2021-11-04 12:36 ` [PATCH v3 04/25] target/ppc: Implement vsldbi/vsrdbi instructions matheus.ferst
2021-11-04 12:36 ` [PATCH v3 05/25] target/ppc: Implement Vector Insert from GPR using GPR index insns matheus.ferst
2021-11-04 17:40 ` Richard Henderson
2021-11-04 12:37 ` [PATCH v3 06/25] target/ppc: Implement Vector Insert Word from GPR using Immediate insns matheus.ferst
2021-11-04 12:37 ` [PATCH v3 07/25] target/ppc: Implement Vector Insert from VSR using GPR index insns matheus.ferst
2021-11-04 12:37 ` [PATCH v3 08/25] target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree matheus.ferst
2021-11-04 12:37 ` [PATCH v3 09/25] target/ppc: Implement Vector Extract Double to VSR using GPR index insns matheus.ferst
2021-11-04 12:37 ` [PATCH v3 10/25] target/ppc: Introduce REQUIRE_VSX macro matheus.ferst
2021-11-04 12:37 ` [PATCH v3 11/25] target/ppc: receive high/low as argument in get/set_cpu_vsr matheus.ferst
2021-11-04 12:37 ` [PATCH v3 12/25] target/ppc: moved stxv and lxv from legacy to decodtree matheus.ferst
2021-11-04 12:37 ` [PATCH v3 13/25] target/ppc: moved stxvx and lxvx " matheus.ferst
2021-11-04 12:37 ` [PATCH v3 14/25] target/ppc: added the instructions LXVP and STXVP matheus.ferst
2021-11-04 12:37 ` [PATCH v3 15/25] target/ppc: added the instructions LXVPX and STXVPX matheus.ferst
2021-11-04 12:37 ` [PATCH v3 16/25] target/ppc: added the instructions PLXV and PSTXV matheus.ferst
2021-11-04 12:37 ` [PATCH v3 17/25] target/ppc: added the instructions PLXVP and PSTXVP matheus.ferst
2021-11-04 12:37 ` [PATCH v3 18/25] target/ppc: moved XXSPLTW to using decodetree matheus.ferst
2021-11-04 12:37 ` [PATCH v3 19/25] target/ppc: moved XXSPLTIB " matheus.ferst
2021-11-04 12:37 ` [PATCH v3 20/25] target/ppc: implemented XXSPLTI32DX matheus.ferst
2021-11-04 12:37 ` [PATCH v3 21/25] target/ppc: Implemented XXSPLTIW using decodetree matheus.ferst
2021-11-04 12:37 ` [PATCH v3 22/25] target/ppc: implemented XXSPLTIDP instruction matheus.ferst
2021-11-04 12:37 ` matheus.ferst [this message]
2021-11-04 12:37 ` [PATCH v3 24/25] target/ppc: Implement lxvkq instruction matheus.ferst
2021-11-04 12:37 ` [PATCH v3 25/25] target/ppc: cntlzdm/cnttzdm implementation without brcond matheus.ferst
2021-11-04 17:41 ` Richard Henderson
2021-11-05 1:26 ` [PATCH v3 00/25] PowerISA v3.1 instruction batch David Gibson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211104123719.323713-24-matheus.ferst@eldorado.org.br \
--to=matheus.ferst@eldorado.org.br \
--cc=bruno.larsen@eldorado.org.br \
--cc=david@gibson.dropbear.id.au \
--cc=groug@kaod.org \
--cc=lucas.castro@eldorado.org.br \
--cc=luis.pires@eldorado.org.br \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).