From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, Marcel Apfelbaum <marcel@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
Igor Mammedov <imammedo@redhat.com>
Cc: linux-cxl@vger.kernel.org,
"Ben Widawsky" <ben.widawsky@intel.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
linuxarm@huawei.com,
"Shameerali Kolothum Thodi"
<shameerali.kolothum.thodi@huawei.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Saransh Gupta1" <saransh@ibm.com>,
"Shreyas Shah" <shreyas.shah@elastics.cloud>,
"Chris Browy" <cbrowy@avery-design.com>,
"Samarth Saxena" <samarths@cadence.com>,
"Dan Williams" <dan.j.williams@intel.com>
Subject: [PATCH v4 34/42] mem/cxl_type3: Add read and write functions for associated hostmem.
Date: Mon, 24 Jan 2022 17:16:57 +0000 [thread overview]
Message-ID: <20220124171705.10432-35-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220124171705.10432-1-Jonathan.Cameron@huawei.com>
From: Jonathan Cameron <jonathan.cameron@huawei.com>
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then directly access the hostmem->mr to fullfil the actual
operation. Note that failed writes are silent, but failed reads
return poison. Note this is based loosely on:
https://lore.kernel.org/qemu-devel/20200817161853.593247-6-f4bug@amsat.org/
[RFC PATCH 0/9] hw/misc: Add support for interleaved memory accesses
Only lightly tested so far. More complex test cases yet to be written.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/mem/cxl_type3.c | 81 +++++++++++++++++++++++++++++++++++++
include/hw/cxl/cxl_device.h | 5 +++
2 files changed, 86 insertions(+)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index e99d84c92d..eb0203dcbc 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -161,6 +161,87 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
&ct3d->cxl_dstate.device_registers);
}
+/* TODO: Support multiple HDM decoders and DPA skip */
+static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr host_addr, uint64_t *dpa)
+{
+ uint32_t *cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers;
+ uint64_t decoder_base, decoder_size, hpa_offset;
+ uint32_t hdm0_ctrl;
+ int ig, iw;
+
+ decoder_base = (((uint64_t)cache_mem[R_CXL_HDM_DECODER0_BASE_HI] << 32) |
+ cache_mem[R_CXL_HDM_DECODER0_BASE_LO]);
+ if ((uint64_t)host_addr < decoder_base) {
+ return false;
+ }
+
+ hpa_offset = (uint64_t)host_addr - decoder_base;
+
+ decoder_size = ((uint64_t)cache_mem[R_CXL_HDM_DECODER0_SIZE_HI] << 32) |
+ cache_mem[R_CXL_HDM_DECODER0_SIZE_LO];
+ if (hpa_offset >= decoder_size) {
+ return false;
+ }
+
+ hdm0_ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
+ iw = FIELD_EX32(hdm0_ctrl, CXL_HDM_DECODER0_CTRL, IW);
+ ig = FIELD_EX32(hdm0_ctrl, CXL_HDM_DECODER0_CTRL, IG);
+
+ *dpa = (MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) |
+ ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset) >> iw);
+
+ return true;
+}
+
+MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ CXLType3Dev *ct3d = CT3(d);
+ uint64_t dpa_offset;
+ MemoryRegion *mr;
+
+ /* TODO support volatile region */
+ mr = host_memory_backend_get_memory(ct3d->hostmem);
+ if (!mr) {
+ return MEMTX_ERROR;
+ }
+
+ if (!cxl_type3_dpa(ct3d, host_addr, &dpa_offset)) {
+ return MEMTX_ERROR;
+ }
+
+ if (dpa_offset > mr->size) {
+ return MEMTX_ERROR;
+ }
+
+ return memory_region_dispatch_read(mr, dpa_offset, data,
+ size_memop(size), attrs);
+}
+
+MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
+ unsigned size, MemTxAttrs attrs)
+{
+ CXLType3Dev *ct3d = CT3(d);
+ uint64_t dpa_offset;
+ MemoryRegion *mr;
+
+ mr = host_memory_backend_get_memory(ct3d->hostmem);
+ if (!mr) {
+ return MEMTX_OK;
+ }
+
+ if (!cxl_type3_dpa(ct3d, host_addr, &dpa_offset)) {
+ return MEMTX_OK;
+ }
+
+ if (dpa_offset > mr->size) {
+ return MEMTX_OK;
+ }
+
+ return memory_region_dispatch_write(mr, dpa_offset, data,
+ size_memop(size), attrs);
+}
+
static void ct3d_reset(DeviceState *dev)
{
CXLType3Dev *ct3d = CT3(dev);
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 0426714e9b..0f6adbae32 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -258,4 +258,9 @@ struct CXLType3Class {
uint64_t offset);
};
+MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs);
+MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
+ unsigned size, MemTxAttrs attrs);
+
#endif
--
2.32.0
next prev parent reply other threads:[~2022-01-24 18:06 UTC|newest]
Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 17:16 [PATCH v4 00/42] CXl 2.0 emulation Support Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 01/42] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron via
2022-01-25 13:53 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 02/42] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron via
2022-01-26 12:32 ` Alex Bennée
2022-01-28 14:22 ` Jonathan Cameron via
2022-01-28 14:46 ` Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 03/42] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron via
2022-01-26 18:06 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 04/42] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron via
2022-01-26 18:07 ` Alex Bennée
2022-01-28 15:02 ` Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 05/42] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron via
2022-01-26 18:17 ` Alex Bennée
2022-01-28 15:16 ` Jonathan Cameron via
2022-01-28 16:37 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 06/42] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron via
2022-01-26 18:22 ` Alex Bennée
2022-01-28 15:52 ` Jonathan Cameron via
2022-01-27 11:31 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 07/42] hw/cxl/device: Add memory device utilities Jonathan Cameron via
2022-01-27 11:28 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 08/42] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron via
2022-01-27 11:43 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 09/42] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron via
2022-01-27 11:50 ` Alex Bennée
2022-01-28 17:52 ` Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 10/42] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron via
2022-01-27 11:55 ` Alex Bennée
2022-01-28 16:47 ` Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 11/42] hw/pxb: Use a type for realizing expanders Jonathan Cameron via
2022-01-27 12:01 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 12/42] hw/pci/cxl: Create a CXL bus type Jonathan Cameron via
2022-01-27 12:05 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 13/42] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron via
2022-01-27 13:59 ` Alex Bennée
2022-01-28 18:20 ` Jonathan Cameron via
2022-01-28 18:48 ` Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 14/42] tests/acpi: allow DSDT.viot table changes Jonathan Cameron via
2022-01-27 14:06 ` Alex Bennée
2022-01-28 18:26 ` Jonathan Cameron via
2022-01-28 18:34 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 15/42] acpi/pci: Consolidate host bridge setup Jonathan Cameron via
2022-01-27 14:10 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 16/42] tests/acpi: Add update DSDT.viot Jonathan Cameron via
2022-01-27 14:12 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 17/42] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron via
2022-01-27 14:18 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 18/42] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 19/42] hw/cxl/rp: Add a root port Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 20/42] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 21/42] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 22/42] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 23/42] tests/acpi: allow CEDT table addition Jonathan Cameron via
2022-02-09 18:18 ` Jonathan Cameron via
2022-02-09 19:09 ` Michael S. Tsirkin
2022-01-24 17:16 ` [PATCH v4 24/42] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 25/42] hw/cxl/device: Add some trivial commands Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 26/42] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 27/42] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron via
2022-01-28 17:29 ` Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 28/42] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 29/42] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron via
2022-01-25 17:02 ` Alex Bennée
2022-01-25 17:51 ` Jonathan Cameron via
2022-01-25 22:53 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 30/42] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 31/42] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron via
2022-01-25 17:15 ` Alex Bennée
2022-01-25 18:13 ` Jonathan Cameron via
2022-01-25 18:16 ` Michael S. Tsirkin
2022-01-26 12:24 ` Alex Bennée
2022-01-24 17:16 ` [PATCH v4 32/42] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 33/42] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron via
2022-01-24 17:16 ` Jonathan Cameron via [this message]
2022-01-24 17:16 ` [PATCH v4 35/42] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron via
2022-01-24 17:16 ` [PATCH v4 36/42] arm/virt: Allow virt/CEDT creation Jonathan Cameron via
2022-01-24 17:17 ` [PATCH v4 37/42] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron via
2022-01-24 17:17 ` [PATCH v4 38/42] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file Jonathan Cameron via
2022-01-24 17:17 ` [PATCH v4 39/42] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron via
2022-01-24 17:17 ` [PATCH v4 40/42] i386/pc: Enable CXL fixed memory windows Jonathan Cameron via
2022-01-24 17:17 ` [PATCH v4 41/42] qtest/acpi: Add reference CEDT tables Jonathan Cameron via
2022-01-24 17:17 ` [PATCH v4 42/42] qtest/cxl: Add very basic sanity tests Jonathan Cameron via
2022-01-24 18:11 ` [PATCH v4 00/42] CXl 2.0 emulation Support Jonathan Cameron via
2022-01-25 13:55 ` Alex Bennée
2022-01-25 15:49 ` Jonathan Cameron via
2022-01-25 19:18 ` Ben Widawsky
2022-01-25 23:55 ` Ben Widawsky
2022-01-26 9:46 ` Jonathan Cameron via
2022-01-27 14:22 ` Alex Bennée
2022-01-27 16:42 ` Jonathan Cameron via
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