From: Damien Hedde <damien.hedde@greensocs.com>
To: qemu-devel@nongnu.org
Cc: Damien Hedde <damien.hedde@greensocs.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
qemu-riscv@nongnu.org
Subject: [PATCH 0/5] RiscV cleanups for user-related life cycles
Date: Fri, 18 Feb 2022 17:46:41 +0100 [thread overview]
Message-ID: <20220218164646.132112-1-damien.hedde@greensocs.com> (raw)
Hi,
This is a few cleanups regarding user oriented life-cycle use cases.
When a device is accessible to user creation, there are a few
life-cycle use cases to consider:
+ init -> finalize (happen when introspection the object).
+ init -> realize-failure -> finalize (realize must report errors due
to miss configuration and leave in a 'good' state)
This series fixes issues I've spotted in the riscv hart array and
interrupt controllers. It is organized as follows:
+ patch 1 prevent memory leak in riscv array array
+ patch 2 introduce a new function in the riscv cpu needed by next
pacthes
+ patches 3/4/5 prevent memory leaks and add error reporting in plic and
aclint devices
Thanks,
--
Damien
Damien Hedde (5):
hw/riscv/riscv_hart: free the harts array when the object is finalized
target/riscv: add riscv_cpu_release_claimed_interrupts function
hw/intc/sifive_plic: report errors and free allocated memory
hw/intc/riscv_aclint: swi: report errors and free allocated memory
hw/intc/riscv_aclint: mtimer: report errors and free allocated memory
target/riscv/cpu.h | 7 +++
hw/intc/riscv_aclint.c | 112 ++++++++++++++++++++++++++++----------
hw/intc/sifive_plic.c | 90 ++++++++++++++++++++----------
hw/riscv/riscv_hart.c | 8 +++
target/riscv/cpu_helper.c | 8 +++
5 files changed, 168 insertions(+), 57 deletions(-)
--
2.35.1
next reply other threads:[~2022-02-18 16:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-18 16:46 Damien Hedde [this message]
2022-02-18 16:46 ` [PATCH 1/5] hw/riscv/riscv_hart: free the harts array when the object is finalized Damien Hedde
2022-02-18 17:23 ` Peter Maydell
2022-02-18 17:39 ` Damien Hedde
2022-02-18 17:46 ` Peter Maydell
2022-02-21 10:29 ` Damien Hedde
2022-02-18 16:46 ` [PATCH 2/5] target/riscv: add riscv_cpu_release_claimed_interrupts function Damien Hedde
2022-02-18 16:46 ` [PATCH 3/5] hw/intc/sifive_plic: report errors and free allocated memory Damien Hedde
2022-02-18 16:46 ` [PATCH 4/5] hw/intc/riscv_aclint: swi: " Damien Hedde
2022-02-18 16:46 ` [PATCH 5/5] hw/intc/riscv_aclint: mtimer: " Damien Hedde
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